Freescale 56F8356, 56F8156 DATA SHEET
56F8356/56F8156
Data Sheet
Preliminary Technical Data
56F8300
16-bit Digital Signal Controllers
MC56F8356
Rev. 10.0
12/2005
freescale.com
Document Revision History
Version History Description of Change
Rev 1.0
Rev 2.0
Rev 3.0
Rev 4.0
Rev 5.0
Rev 6.0
Rev 7.0 Added 56F8156 information; edited to indicate differences in 56F8356 and 56F8 156. Refor-
Rev 8.0 Added output voltage maximum value and note to clarify in Table 10-1; also removed overall
Rev 9.0 Updated Table 10-24 to reflect new value for maximum Uncalibrated Gain Error
Rev 10.0 Deleted RSTO from Pin Group 2 (listed after Table 10-1). Deleted formula for Max Ambient
Initial Public Release
Added Package Pins to GPIO Table in Part 8 General Purpose Input/Output (GPIO). Added
“Typical Min” values to Table 10-18. Editing grammar, spelling, consistency of language
throughout family. Updated values in Regulator Parameters Table 10-9, External Clock
Operation Timing Requirements Table 10-13, SPI Timing Table 10-18, ADC Parameters
Table 10-24, and IO Loading Coefficients at 10MHz Table 10-25.
Added Part 4.8, added the word “access” to FM Error Interrupt in Table 4-5, documenting only
Typ. numbers for LVI in Table 10-6, updated EMI numbers and writeup in Part 10.8.
Updated numbers in Table 10-7 and Table 10-8 with more recent data, Corrected typo in
Table 10-3 in Pd characteristics.
Replace any reference to Flash Interface Unit with Flash Memory Module; corrected thermal
numbers for 144 LQFP in Table 10-3; removed unneccessary notes in Table 10-12; corrected
temperature range in Table 10-14; added ADC calibration information to Table 10-24 and new
graphs in Figure 10-22
Adding/clarifing notes to Table 4-4 to help clarify independen t program flash blocks and other
Program Flash modes, clarification to Table 1 0-23, corrected Digital Input Current Low (pull-up
enabled) numbers in
Table 10-1.
matted for Freescale look and feel. Updated Temperature Sensor and ADC tables, then
updated balance of electrical tables for consistency throughout family. Clarified I/O power
description in Table 2-2, added note to Table 10-7 and clarified Section 12.3.
life expectancy note, since life expectancy is dependent on customer usage and must be
determined by reliability engineering. Clarified value and unit measure for Maximum allowed
in Table 10-3. Corrected note about average value for Flash Data Retention in Table 10-4.
P
D
Added new RoHS-compliant orderable part numbers in Table 13-1.
Operating Temperature (Automotive) and Max Ambient Operating Temperature (Industrial) in
Table 10-4. Added RoHS-compliance and “pb-free” language to back cover.
Table 10-5. Removed text and Table 10-2; replaced with note to
Please see http://www.freescale.com for the most current Data Sheet revision.
56F8356 Technical Data, Rev. 10.0
2 Freescale Semiconductor
Preliminary
56F8356/56F8156 General Description
Note: Features in italics are NOT available in the 56F8156 device.
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Access up to 1MB of off-chip program and data memory
• Chip Select Logic for glueless interface to ROM and
SRAM
• 256KB of Program Flash
• 4KB of Program RAM
• 8KB of Data Flash
• 16KB of Data RAM
• 16KB of Boot Flash
• Up to two 6-channel PWM modules
• Four 4-channel, 12-bit ADCs
EMI_MODE
6
3
3
6
3
4
4
4
5
4
4
TEMP_SENSE
4
4
1
2
2
PWM Outputs
Current Sense Inputs
or GPIOC
Fault Inputs
PWM Outputs
Current Sense Inputs
or GPIOD
Fault Inputs
AD0
ADCA
AD1
VREF
ADCB
Program Memory
128K x 16 Flash
Data Memory
4K x 16 Flash
8K x 16 RAM
Decoding
Peripherals
AD0
AD1
Quadrature
Decoder 0 or
Quad
Timer A or
GPIOC
Quadrature
Decoder 1 or
Quad
Timer B or
SPI1 or
GPIOC
Quad
Timer C o r
GPIOE
Quad
Timer D or
GPIOE
FlexCAN
PWMA
PWMB
Memory
2K x 16 RAM
8K x 16 Boot
Flash
SPI0 or
GPIOE
4
RSTO
Hardware Looping Unit
SCI1 or
GPIOD
2
EXTBOOT
RESET
Program Controller
and
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
Peripheral
Device Selects
SCI0 or
GPIOE
2
5
JTAG/
EOnCE
Port
Address
Generation Unit
PAB
PDB
CDBR
CDBW
IPBus Bridge (IPBB)
RW
Control
COP/
Watchdog
IRQA
• Temperature Sensor
• Up to two Quadrature Decoders
• Optional on-chip regulator
• FlexCAN module
• Two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Up to four general-purpose Quad Timers
• Computer Operating Properly (COP) / Watchdog
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 62 GPIO lines
• 144-pin LQFP Package
OCR_DIS
V
V
PP
2
56800E Core
IPAB IPWDB IPRDB
Interrupt
Controller
IRQB
V
CAP
DD
47
Digital Reg
16-Bit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
System Bus
Control
System
Integration
Module
V
ss
5
Analog Reg
Low Voltage
Supervisor
R/W Control
Clock
resets
P
O
R
CLKO
V
DDA
2
Manipulation
Address Bus
External Data
Bus Switch
External Bus
Interface Unit
Bus Control
PLL
Clock
Generator
CLKMODE
V
SSA
Bit
Unit
External
Switch
O
S
C
6
2
8
7
9
2
XTAL
EXTAL
A0-5 or GPIOA8-13
A6-7 or GPIOE2-3
A8-15 or GPIOA0-7
GPIOB0 or A16
D0-6 or GPIOF9-15
D7-15 or GPIOF0-8
WR
RD
GPIOD0-1 or CS2-3
PS or CS0 or GPIOD8
or CS1 or GPIOD9
DS
56F8356 / 56F8156 Block Diagram
56F8356 Technical Data, Rev. 10.0
Freescale Semiconductor 3
Preliminary
Table of Contents
Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . .5
1.1. 56F8356/56F8156 Features . . . . . . . . . . . . . 5
1.2. Device Description . . . . . . . . . . . . . . . . . . . . 7
1.3. Award-Winning Development Environment . 9
1.4. Architecture Block Diagram . . . . . . . . . . . . 10
1.5. Product Documentation . . . . . . . . . . . . . . . 14
1.6. Data Sheet Conventions . . . . . . . . . . . . . . 14
Part 2: Signal/Connection Descriptions . . .15
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . 18
Part 3: On-Chip Clock Synthesis (OCCS) . .37
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.2. External Clock Operation . . . . . . . . . . . . . . 37
3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Part 4: Memory Map . . . . . . . . . . . . . . . . . . .39
4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.2. Program Map . . . . . . . . . . . . . . . . . . . . . . . 40
4.3. Interrupt Vector Table . . . . . . . . . . . . . . . . . 42
4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.5. Flash Memory Map . . . . . . . . . . . . . . . . . . . 46
4.6. EOnCE Memory Map . . . . . . . . . . . . . . . . . 48
4.7. Peripheral Memory Mapped Registers . . . . 49
4.8. Factory Programmed Memory . . . . . . . . . . 76
Part 5: Interrupt Controller (ITCN) . . . . . . . .77
5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.3. Functional Description . . . . . . . . . . . . . . . . 77
5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . 79
5.5. Operating Modes . . . . . . . . . . . . . . . . . . . . 79
5.6. Register Descriptions . . . . . . . . . . . . . . . . . 80
5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Part 6: System Integration Module (SIM) .107
6.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3. Operating Modes . . . . . . . . . . . . . . . . . . . 108
6.4. Operating Mode Register . . . . . . . . . . . . . 108
6.5. Register Descriptions . . . . . . . . . . . . . . . . 109
6.6. Clock Generation Overview . . . . . . . . . . . 122
6.7. Power-Down Modes Overview . . . . . . . . . 123
6.8. Stop and Wait Mode Disable Func tion . . . 123
6.9. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Part 8: General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . . 127
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . .127
8.2. Memory Maps . . . . . . . . . . . . . . . . . . . . . .128
8.3. Configuration . . . . . . . . . . . . . . . . . . . . . . .128
Part 9: Joint Test Action Group (JTAG) . 133
9.1. 56F8356 Information . . . . . . . . . . . . . . . . .133
Part 10: Specifications . . . . . . . . . . . . . . . 134
10.1. General Characteristics . . . . . . . . . . . . . .134
10.2. DC Electrical Characteristics . . . . . . . . . .138
10.3. AC Electrical Characteristics . . . . . . . . . .142
10.4. Flash Memory Characteristics . . . . . . . . .142
10.5. External Clock Operation Timing . . . . . . .143
10.6. Phase Locked Loop Timing . . . . . . . . . . .143
10.7. Crystal Oscillator Timing . . . . . . . . . . . . .144
10.8. External Memory Interface Timing . . . . . .144
10.9. Reset, Stop, Wait, Mode Select, and
Interrupt Timing . . . . . . . . . . . . . .147
10.10. Serial Peripheral Interface (SPI) Timing .149
10.11. Quad Timer Timing . . . . . . . . . . . . . . . .153
10.12. Quadrature Decoder Timing . . . . . . . . . .153
10.13. Serial Communication Interface (SCI)
Timing . . . . . . . . . . . . . . . . . . . . .154
10.14. Controller Area Network (CAN) Timing .155
10.15. JTAG Timing . . . . . . . . . . . . . . . . . . . . .155
10.16. Analog-to-Digital Converter (ADC)
Parameters . . . . . . . . . . . . . . . . .157
10.17. Equivalent Circuit for ADC Inputs . . . . . .160
10.18. Power Consumption . . . . . . . . . . . . . . . .160
Part 11: Packaging . . . . . . . . . . . . . . . . . . 162
11.1. 56F8356 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . .162
11.2. 56F8156 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . .165
Part 12: Design Considerations . . . . . . . . 169
12.1. Thermal Design Considerations . . . . . . . .169
12.2. Electrical Design Considerations . . . . . . .170
12.3. Power Distribution and I/O Ring
Implementation . . . . . . . . . . . . . .171
Part 13: Ordering Information . . . . . . . . . 172
Part 7: Security Features . . . . . . . . . . . . . .124
7.1. Operat ion with Security Enabled . . . . . . . 124
7.2. Flash Access Blocking Mechanisms . . . . 125
56F8356 Technical Data, Rev. 10.0
4 Freescale Semiconductor
Preliminary
Part 1 Overview
1.1 56F8356/56F8156 Features
1.1.1 Core
• Efficient 16-bit 56800E family controller engine with dual Harvard architecture
• Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Four 36-bit accumulators, including extension bits
• Arithmetic and logic multi-bit shifter
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Three internal address buses
• Four internal data buses
• Instruction set supports both DSP and controller functions
• Controller style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/EOnCE debug programming interface
56F8356/56F8156 Features
1.1.2 Differences Between Devices
Table 1-1 outlines the key differences between the 56F8356 and 56F8156 devices.
Table 1-1 Device Differences
Feature 56F8356 56F8156
Guaranteed Speed 60MHz/60 MIPS 40MHz/40 MIPS
Program RAM 4KB Not Available
Data Flash 8KB Not Available
PWM 2 x 6 1 x 6
CAN 1 Not Available
Quad Timer 4 2
Quadrature Decoder 2 x 4 1 x 4
Temperature Sensor 1 Not Available
Dedicated GPIO — 5
56F8356 Technical Data, Rev. 10.0
Freescale Semiconductor 5
Preliminary
1.1.3 Memory
Note: Features in italics ae NOT available in the 56F8156 device.
• Harvard architecture permits as many as three simultaneous accesses to program and data memory
• Flash security protection feature
• On-chip memory, including a low-cost, high-volume Flash solution
— 256KB of Program Flash
— 4KB of Program RAM
— 8KB of Data Flash
— 16KB of Data RAM
— 16KB of Boot Flash
• Off-chip memory expansion capabilities programmable for 0 - 30 wait states
— Access up to 1MB of program memory or 1MB of data memory
— Chip select logic for glueless interface to ROM and SRAM
• EEPROM emulation capability
1.1.4 Peripheral Circuits
Note: Features in italics are NOT available in the 56F8156 device.
• Pulse Width Modulator:
— In the 56F8356, two Pulse W idth Modulator mod ules, each with six PWM out puts, three Current Sense
inputs, and three Fault inputs; fault-tolerant design with dead time insertion; supports both
center-aligned and edge-aligned modes
— In the 56F8156, one Pulse Width Modulator module with six PWM outputs, three Current Sense inputs,
and three Fault inputs; fault-tolerant design with dead time insertion; supports both center-aligned and
edge-aligned modes
• Four 12-bit, Analog-to-Digital Converters (ADCs), which support four simultane ous conversions with
quad, 4-pin multiplexed inputs; ADC and PWM modules can be synchronized through Timer C, channels
2 and 3
• Quadrature Decoder:
— In the 56F8356, two four-input Quadrature Decoders or two additional Quad Timers
— In the 56F8156, one four-input Quadrature Decoder, which works in conjunction with Quad Timer A
• Temperature Sensor can be connected, on the board, to any of the ADC inputs to monitor the on-chip
temperature
•Quad Timer:
— In the 56F8356, four dedicated general-purpose Quad Timers totaling three dedicated pins: Timer C
with one pin and Timer D with two pins
— In the 56F8156, two Quad Timers; Timer A and Timer C both work in conjunction with GPIO
• Optional on-chip regulator
• FlexCAN (CAN Version 2.0 B-compliant ) module with 2-pin port for transmit and receive
56F8356 Technical Data, Rev. 10.0
6 Freescale Semiconductor
Preliminary
Device Description
• Two Serial Communication Interfaces (SCIs), each with two pins (or four additional GPIO lines)
• Up to two Serial Peripheral Interfaces (SPIs), both with configurable 4-pin port (or eight additional GPIO
lines)
— In the 56F8356, SPI1 can also be used as Quadrature Decoder 1 or Quad Timer B
— In the 56F8156, SPI1 can alternately be used only as GPIO
• Computer Operating Properly (COP) / Watchdog timer
• Two dedicated external interrupt pins
• 62 General Purpose I/O (GPIO) pins
• External reset input pin for hardware reset
• External reset output pin for system reset
• Integrated low-voltage interrupt module
• JTAG/Enhanced On-Ch ip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time
debugging
• Software-programmable, Phase Lock Loop (PLL)-based frequency synthesizer for the core clock
1.1.5 Energy Information
• Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
• On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories; can be disabled
• On-chip regulators for digital and analog circuitry to lower cost and reduce noise
• Wait and Stop modes available
• ADC smart power management
• Each peripheral can be individually disabled to save power
1.2 Device Description
The 56F8356 and 56F8156 are members of the 56800E core-based family of controllers. Each combines,
on a single chip, the processing power of a Digital Signal Processor (DSP) and the functionality of a
microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because
of its low cost, configuration flexibility, and compact program code, the 56F8356 and 56F8156 are
well-suited for many applications. The devices include many peripherals that are especially useful for
motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and
control, automotive control (56F8156 only), engine management, noise suppression, remote utility
metering, industrial control for power, lighting, and automation applications.
The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and
optimized instruction set allow straightforward generation of efficient, compact DSP and control code.
The instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized
control applications.
The 56F8356 and 56F8156 support program execution from either internal or external memories. Two
data operands can be accessed from the on-chip data RAM per instruction cycle. These devices also
provide two external dedicated interrupt lines and up to 62 General Purpose Input/Output (GPIO) lines,
depending on peripheral configuration.
56F8356 Technical Data, Rev. 10.0
Freescale Semiconductor 7
Preliminary
1.2.1 56F8356 Features
The 56F8356 controller includes 256KB of Program Flash and 8KB of Data Flash (each programmable
through the JTAG port) with 4KB of Program RAM and 16KB of Data RAM. It also supports program
execution from external memory.
A total of 16KB of Boot Flash is incorporated for easy customer inclusion of field-programmable software
routines that can be used to program the main Program and Data Flash memory areas. Both Program and
Data Flash memories can be independently bulk erased or erased in pages. Program Flash page erase size
is 1KB. Boot and Data Flash page erase size is 512 bytes. The Boot Flash memory can also be either bulk
or page erased.
A key application-specific feature of the 56F8356 is the inclusion of two Pulse Width Modulator (PWM)
modules. These modules each incorporate three complementary, individually programmable PWM signal
output pairs (each module is also capable of supporting six independent PWM functions, for a total of 12
PWM outputs) to enhance motor control functionality. Complementary operation permits programmable
dead time insertion, distortion correction via current sensing by software, and separate top and bottom
output polarity control. The up-counter value is programmable to support a continuously variable PWM
frequency. Edge-aligned and center-aligned synchronous pulse width control (0% to 100% modulation) is
supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors); both
BDC and BLDC (Brush and Brushless DC motors); SRM and VRM (Switched and Variable Reluctance
Motors); and stepper motors. The PWMs incorporate fault protection and cycle-by-cycle current limiting
with sufficient output drive capability to directly drive standard optoisolators. A “smoke-inhibit”,
write-once protection feature for key parameters is also included. A patented PWM waveform distortion
correction circuit is also provided. Each PWM is double-buffered and includes interrupt controls to permit
integral reload rates to be programmable from 1 to 16. The PWM modules provide reference outputs to
synchronize the Analog-to-Digital Converters through two channels of Quad Timer C.
The 56F8356 incorporates two Quadrature Decoders capable of capturing all four transitions on the
two-phase inputs, permitting generation of a number proportional to actual position. Speed computation
capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the
Quadrature Decoder can be programmed with a time-out value to alert when no shaft motion is detected.
Each input is filtered to ensure only true transitions are recorded.
This controller also provides a full set of standard programmable peripherals that include two Serial
Communications Interfaces (SCIs); two Serial Peripheral Interfaces (SPIs); and four Quad Timers. Any of
these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function is not required. A
Flex Controller Area Network (FlexCAN) interface (CAN Version 2.0 B-compliant) and an internal
interrupt controller are a part of the 56F8356.
1.2.2 56F8156 Features
The 56F8156 controller includes 256KB of Program Flash, programmable through the JTAG port, with
16KB of Data RAM. It also supports program execution from external memory.
A total of 16KB of Boot Flash is incorporated for easy customer inclusion of field-programmable software
routines that can be used to program the main Program Flash memory areas, which can be independently
bulk erased or erased in pages. Program Flash page erase size is 1KB. Boot Flash page erase size is 512
bytes. and the Boot Flash memory can also be either bulk or page erased.
56F8356 Technical Data, Rev. 10.0
8 Freescale Semiconductor
Preliminary
Award-Winning Development Environment
A key application-specific feature of the 56F8156 is the inclusion of one Pulse Width Modulator (PWM)
module. This module incorporates three complementary, individually programmable PWM signal output
pairs and can also support six independent PWM functions to enhance motor control functionality.
Complementary operation permits programmable dead time insertion, distortion correction via current
sensing by software, and separate top and bottom output polarity control. The up-counter value is
programmable to support a continuously variable PWM frequency. Edge-aligned and center-aligned
synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of
controlling most motor types: ACIM (AC Induction Motors); both BDC and BLDC (Brush and Brushless
DC motors); SRM and VRM (Switched and Variable Reluctance Motors); and stepper motors. The PWM
incorporates fault protection and cycle-by-cycle current limiting with sufficient output drive capability to
directly drive standard optoisolators. A “smoke-inhibit”, write-once protection feature for key parameters
is also included. A patented PWM waveform distortion correction circuit is also provided. Each PWM is
double-buffered and includes interrupt controls to permit integral reload rates to be programmable from 1
to 16. The PWM module provides reference outputs to synchronize the Analog-to-Digital Converters
through two channels of Quad Timer C.
The 56F8156 incorporates a Quadrature Decoder capable of capturing all four transitions on the two-phase
inputs, permitting generation of a number proportional to actual position. Speed computation capabilities
accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the Quadrature Decoder
can be programmed with a time-out value to alert when no shaft motion is detected. Each input is filtered
to ensure only true transitions are recorded.
This controller also provides a full set of standard programmable peripherals that include two Serial
Communications Interfaces (SCIs); two Serial Peripheral Interfaces (SPIs); and two Quad Timers. Any of
these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function is not required. An
internal interrupt controller are a part of the 56F8156.
1.3 Award-Winning Development Environment
Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, PE, CodeWarrior and EVMs create a complete, scalable
tools solution for easy, fast, and efficient development.
56F8356 Technical Data, Rev. 10.0
Freescale Semiconductor 9
Preliminary
1.4 Architecture Block Diagram
Note: Features in italics are NOT available in the 56F8156 device and are shaded in the following figures.
The 56F8356/56F8156 architecture is shown in Figure 1-1 and Figure 1-2. Figure 1-1 illustrates how the
56800E system buses communicate with internal memories, the external memory interface and the IPBus
Bridge. Table 1-2 lists the internal buses in the 56800E architecture and provides a brief description of
their function. Figure 1-2 shows the peripherals and control blocks connected to the IPBus Bridge. The
figures do not show the on-board regulator and power and ground signals. They also do not show the
multiplexing between peripherals or the dedicated GPIOs. Please see Part 2, Signal/Connection
Descriptions, to see which signals are multiplexed with those of other peripherals.
Also shown in Figure 1-2 are connections between the PWM, Timer C and ADC blocks. These
connections allow the PWM and/or Timer C to control the timing of the start of ADC conversions. The
Timer C channel indicated can generate periodic start (SYNC) signals to the ADC to start its conversions.
In another operating mode, the PWM load interrupt (SYNC output) signal is routed internally to the Timer
C input channel as indicated. The timer can then be used to introduce a controllable delay before
generating its output signal. The timer output then triggers the ADC. To fully understand this interaction,
please see the 56F8300 Peripheral User Manual for clarification on the operation of all three of these
peripherals.
56F8356 Technical Data, Rev. 10.0
10 Freescale Semiconductor
Preliminary
Architecture Block Diagram
CHIP
TAP
Controller
TAP
Linking
5
JTAG / EOnCE
pdb_m[15:0]
pab[20:0]
cdbw[31:0]
Boot
Flash
Program
Flash
Program
RAM
56800E
xab1[23:0]
xab2[23:0]
EMI
Data RAM
17
16
6
Address
Data
Control
External
JTAG
Port
cdbr_m[31:0]
xdb2_m[15:0]
Data Flash
IPBus
To Flash
Control Logic
Bridge
Flash
Module
NOT available on the 56F8156 device.
IPBus
Figure 1-1 System Bus Interfaces
Note: Flash memories are encapsulated within the Flash Module(FM). Flash control is accomplished by the
I/O to the FM over the peripheral bus, while reads and writes are completed between the core and the
Flash memories.
Note: The primary data RAM port is 32 bits wide. Other data ports are 16 bits.
56F8356 Technical Data, Rev. 10.0
Freescale Semiconductor 11
Preliminary
To/From IPBus Bridge
CLKGEN
(OSC/PLL)
Interrupt
Controller
Low Voltage Interrupt
Timer A
POR & LVI
4
2
Quadrature Decoder 0
Timer D
Timer B
4
Quadrature Decoder 1
SPI 1
GPIOA
System POR
SIM
COP Reset
COP
FlexCAN
PWMA
PWMB
RESET
2
12
SYNC Output
13
GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
4
2
2
SPI0
SCI0
SCI1
NOT available on the 56F8156 device.
Figure 1-2 Peripheral Subsystem
IPBus
SYNC Output
ch3i
Timer C
ch3o
ch2i
1
ch2o
8
ADCB
, V
1
REFP
8
, V
REFMID
ADCA
TEMP_SENSE
Note: ADCA and ADCB use the same voltage
reference circuit with V
, and V
V
REFN
REFLO
REFH
pins.
,
56F8356 Technical Data, Rev. 10.0
12 Freescale Semiconductor
Preliminary
Architecture Block Diagram
Table 1-2 Bus Signal Names
Name Function
Program Memory Interface
pdb_m[15:0] Program data bus for instruction word fetches or read operations.
cdbw[15:0] Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus
are used for writes to program memory.)
pab[20:0] Program memory address bus. Data is returned on pdb_m bus.
Primary Data Memory Interface Bus
cdbr_m[31:0] Pri mar y core data bus for memory reads. Addressed via xab1 bus.
cdbw[31:0] Primary core data bus for memory writes. Addressed via xab1 bus.
xab1[23:0]
Primary data address bus. Capable of addressing bytes
on cdbw and returned on cdbr_m. Also used to access memory-mapped I/O.
Secondary Data Memory Interface
xdb2_m[15:0] Secondary data bus used for secondary data address bus xab2 in the dual memory reads.
xab2[23:0] Secondary data address bus used for the second of two simultaneous accesses. Capable of
addressing only words. Data is returned on xdb2_m.
Peripheral Interface Bus
IPBus [15:0] Peripheral bus accesses all on-chip peripherals registers. This bus operates at the same clock rate
as the Primary Data Memory and therefore generates no delays when accessing the processor.
Write data is obtained from cdbw. Read data is provided to cdbr_m.
1. Byte accesses can only occur in the bottom half of the memory address space. The MSB of the address will be forced
to 0.
1
, words, and long data types. Data is written
56F8356 Technical Data, Rev. 10.0
Freescale Semiconductor 13
Preliminary
1.5 Product Documentation
The documents in Table 1-3 are required for a complete description and proper design with the
56F8356/56F8156 devices. Documentation is available from local Freescale distributors, Freescale
semiconductor sales offices, Freescale Literature Distribution Centers, or online at
http://www.freescale.com.
Table 1-3 Chip Documentation
Topic Description Order Number
DSP56800E
Reference Manual
56F8300 Peripheral
User Manual
56F8300 SCI/CAN
Bootloader User
Manual
56F8356/56F8156
Technical Data Sheet
Errata Details any chip issues that might be present MC56F8356E
Detailed description of the 56800E family architecture,
and 16-bit controller core processor and the instruction
set
Detailed description of peripherals of the 56F8300
devices
Detailed description of the SCI/CAN Bootloaders
56F8300 family of devices
Electrical and timing specifications, pin descriptions,
and package descriptions (this document)
DSP56800ERM
MC56F8300UM
MC56F83xxBLUM
MC56F8356
MC56F8156E
1.6 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
“asserted” A high true (active high) signal is high or a low true (active low) signal is low.
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
“deasserted” A high true (active high) signal is low or a low true (active low) signal is high.
Examples: Signal/Symbol Logic State Signal State
PIN True Asserted VIL/V
PIN False Deasserted VIH/V
PIN True Asserted VIH/V
PIN False Deasserted VIL/V
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
56F8356 Technical Data, Rev. 10.0
14 Freescale Semiconductor
Voltage
1
OL
OH
OH
OL
Preliminary
Introduction
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F8356 and 56F8156 are organized into functional groups, as detailed
in Table 2-1 and as illustrated in Figure 2-1. In Table 2-2, each table row describes the signal or signals
present on a pin.
Table 2-1 Functional Group Pin Allocations
Functional Group
Power (V
Power Option Control 1 1
Ground (VSS or V
Supply Capacitors1 & V
PLL and Clock 4 4
Address Bus 17 17
Data Bus 16 16
Bus Control 6 6
Interrupt and Program Control 6 6
Pulse Width Modulator (PWM) Ports 25 13
Serial Peripheral Interface (SPI) Port 0 4 4
Serial Peripheral Interface (SPI) Port 1 — 4
Quadrature Decoder Port 0
Quadrature Decoder Port 1
Serial Communications Interface (SCI) Ports 4 4
CAN Ports 2 —
Analog to Digital Converter (ADC) Ports 21 21
DD
or V
)99
DDA
)66
SSA
PP
2
3
Number of Pins in Package
56F8356 56F8156
66
44
4—
Quad Timer Module Ports 3 1
JTAG/Enhanced On-Chip Emulation (EOnCE) 5 5
Temperature Sense 1 —
Dedicated GPIO — 5
1. If the on-chip regulator is disabled, the V
2. Alternately, can function as Quad Timer pins or GPIO
3. Pins in this section can function as Quad Timer, SPI #1, or GPIO
Freescale Semiconductor 15
Preliminary
pins serve as 2.5V V
CAP
56F8356 Technical Data, Rev. 10.0
DD_CORE
power inputs
Power
Power
Power
Ground
Ground
Other
Supply
Ports
PLL
and
Clock
External
Address
Bus
or GPIO
V
DD_IO
V
DDA_ADC
V
DDA_OSC_PLL
V
SS
V
SSA_ADC
OCR_DIS
V
1 - V
CAP
CAP
V
1 & VPP2
PP
CLKMODE
EXTAL
XTAL
CLKO
A0 - A5 (GPIOA8 - 13)
A6 - A7 (GPIOE2 - 3)
A8 - A15 (GPIOA0 - 7)
GPIOB0 (A16)
7
PHASEA0 (TA0, GPIOC4)
1
1
5
1
1
56F8356
4
4
2
1
PHASEB0 (TA1, GPIOC5)
1
INDEX0 (TA2, GPIOC6)
1
HOME0 (TA3, GPIOC7)
1
SCLK0 (GPIOE4)
1
MOSI0 (GPIOE5)
1
MISO0 (GPIOE6)
1
1
SS0
(GPIOE7)
Quadrature
Decoder 0
or Quad
Timer A or
GPIO
SPI0 or
GPIO
1
1
1
1
PHASEA1(TB0, SCLK1, GPIOC0)
1
PHASEB1 (TB1, MOSI1, GPIOC1)
1
INDEX1 (TB2, MISO1, GPIOC2)
1
HOME1 (TB3, SS1
1
, GPIOC3)
Quadrature
Decoder 1 or
Quad Timer B
or SPI 1 or
GPIO
6
2
8
1
PWMA0 - 5
6
ISA0 - 2 (GPIOC8 - 10)
3
FAULTA0 - 2
3
PWMA or
GPIO
External
Data Bus
or GPIO
External
Bus
Control or
GPIO
SCI 0 or
GPIO
SCI 1
or GPIO
JTAG/
EOnCE
Port
D0 - D6 (GPIOF9 - 15)
D7 - D15 (GPIOF0 - 8)
RD
WR
PS / CS0 (GPIOD8)
DS / CS1 (GPIOD9)
GPIOD0 - 1 (CS2 - 3)
TXD0 (GPIOE0)
RXD0 (GPIOE1)
TXD1 (GPIOD6)
RXD1 (GPIOD7)
TCK
TMS
TDI
TDO
TRST
PWMB0 - 5
7
9
1
1
1
1
2
1
1
1
1
1
1
1
1
1
6
ISB0 - 2 (GPIOD10 - 12)
3
FAULTB0 - 3
4
ANA0 - 7
8
V
REF
5
ANB0 - 7
8
TEMP_SENSE
1
CAN_RX
1
CAN_TX
1
TC0 (GPIOE8)
1
TD0 - 1 (GPIOE10 - 11)
2
IRQA
1
IRQB
1
EXTBOOT
1
EMI_MODE
1
RESET
1
RSTO
1
PWMB or
GPIO
ADCA
ADCB
Temperature
Sensor
FlexCAN
QUAD
TIMER C and
D or GPIO
INTERRUPT/
PROGRAM
CONTROL
Figure 2-1 56F8356 Signals Identified by Functional Group1 (144-pin LQFP)
1. Alternate pin functionality is shown in parenthesis; pin direction/type shown is the default functionality.
56F8356 Technical Data, Rev. 10.0
16 Freescale Semiconductor
Preliminary
Power
Power
Power
Ground
Ground
Other
Supply
Ports
PLL
and
Clock
External
Address
Bus
or GPIO
V
DD_IO
V
DDA_ADC
V
DDA_OSC_PLL
V
SS
V
SSA_ADC
OCR_DIS
V
1 - V
CAP
V
PP
CAP
1 & VPP2
CLKMODE
EXTAL
XTAL
CLKO
A0 - A5 (GPIOA8 - 13)
A6 - A7 (GPIOE2 - 3)
A8 - A15 (GPIOA0 - 7)
GPIOB0 (A16)
Introduction
7
1
1
5
PHASEA0 (TA0, GPIOC4)
1
PHASEB0 (TA1, GPIOC5)
1
INDEX0 (TA2, GPIOC6)
1
HOME0 (TA3, GPIOC7)
1
Quadrature
Decoder 0
or Quad
Timer A or
GPIO
1
56F8356
1
4
4
2
1
1
1
1
SCLK0 (GPIOE4)
1
MOSI0 (GPIOE5)
1
MISO0 (GPIOE6)
1
SS0
1
(SCLK1, GPIOC0)
1
(MOSI1, GPIOC1)
1
(MISO1, GPIOC2)
1
(S
1
SPI0 or
GPIO
(GPIOE7)
SPI 1 or
GPIO
S1, GPIOC3)
6
2
8
3
(GPIOC8 - 10)
GPIO
1
External
Data Bus
or GPIO
External
Bus
Control or
GPIO
SCI 0 or
GPIO
SCI 1
or GPIO
JTAG/
EOnCE
Port
D0 - D6 (GPIOF9 - 15)
D7 - D15 (GPIOF0 - 8)
RD
WR
PS / CS0 (GPIOD8)
DS / CS1 (GPIOD9)
GPIOD0 - 1 (CS2 - 3)
TXD0 (GPIOE0)
RXD0 (GPIOE1)
TXD1 (GPIOD6)
RXD1 (GPIOD7)
TCK
TMS
TDI
TDO
TRST
PWMB0 - 5
6
ISB0 - 2 (GPIOD10 - 12)
7
9
1
1
3
4
8
5
8
FAULTB0 - 3
ANA0 - 7
V
REF
ANB0 - 7
PWMB or
GPIO
ADCA
ADCB
1
1
2
1
1
1
TC0 (GPIOE8)
1
TD0 - 1 (GPIOE10 - 11)
2
QUAD
TIMER C or
GPIO
1
IRQA
1
1
1
1
1
1
1
1
1
1
1
IRQB
EXTBOOT
EMI_MODE
RESET
RSTO
INTERRUPT/
PROGRAM
CONTROL
Figure 2-2 56F8156 Signals Identified by Functional Group1 (144-pin LQFP)
1. Alternate pin functionality is shown in parenthesis; pin direction/type shown is the default functionality.
56F8356 Technical Data, Rev. 10.0
Freescale Semiconductor 17
Preliminary
2.2 Signal Pins
After reset, each pin is configured for its primary function (listed first). Any alternate functionality must
be programmed.
If the “State During Reset” lists more than one state for a pin, the first state is the actual reset state. Other
states show the reset condition of the alternate function, which you get if the alternate pin function is
selected without changing the configuration of the alternate peripheral. For example, the A8/GPIOA0 pin
shows that it is tri-stated during reset. If the GPIOA_PER is changed to select the GPIO function of the
pin, it will become an input if no other registers are changed.
Table 2-2 Signal and Package Information for the 144-Pin LQFP
State
Signal Name Pin No. Type
During
Reset
Signal Description
V
DD_IO
V
DD_IO
V
DD_IO
V
DD_IO
V
DD_IO
V
DD_IO
V
DD_IO
V
DDA_ADC
V
DDA_OSC_PLL
V
SS
V
SS
V
SS
1 Supply I/O Power — This pin supplies 3.3V power to the chip I/O interface
and also the Processor core throught the on-chip voltage
16
31
38
66
84
119
102 Supply ADC Power — This pin supplies 3.3V power to the ADC modules.
80 Supply Oscillator and PLL Power — This pin supplies 3.3V power to the
27 Supply V
37
63
regulator, if it is enabled.
It must be connected to a clean analog power supply.
OSC and to the internal regulator that in turn supplies the Phase
Locked Loop. It must be connected to a clean analog power
supply.
— These pins provide ground for chip logic and I/O drivers.
SS
V
SS
V
SS
V
SSA_ADC
18 Freescale Semiconductor
69
144
103 Supply ADC Analog Ground — This pin supplies an analog ground to the
ADC modules.
56F8356 Technical Data, Rev. 10.0
Preliminary
Table 2-2 Signal and Package Information for the 144-Pin LQFP
State
Signal Name Pin No. Type
OCR_DIS 79 Input Input On-Chip Regulator Disab le —
During
Reset
Signal Description
Tie this pin to V
Tie this pin to V
to enable the on-chip regulator
SS
to disable the on-chip regulator
DD
This pin is intended to be a static DC signal from power-up to
shut down. Do not try to toggle this pin for power savings
during operation.
Signal Pins
1 51 Supply Supply V
V
CAP
1 - 4 — When OCR_DIS is tied to VSS (regulator enabled),
CAP
connect each pin to a 2.2µF or greater bypass capacitor in order to
2 128
V
CAP
3 83
V
CAP
4 15
V
CAP
1 125 Input Input VPP1 - 2 — These pins should be left unconnected as an open
V
PP
bypass the core logic voltage regulator, required for proper chip
operation. When OCR_DIS is tied to V
these pins become V
DD_CORE
and should be connected to a
(regulator disabled),
DD
regulated 2.5V power supply.
circuit for normal functionality.
VPP2 2
CLKMODE 87 Input Input Clock Input Mode Selection — This input determines the
function of the XTAL and EXTAL pins.
1 = External clock input on XTAL is used to directly drive the input
clock of the chip. The EXTAL pin should be grounded.
0 = A crystal or ceramic resonator should be connected between
XTAL and EXTAL.
EXTAL 82 Input Input External Crystal Oscillator Input — This input can be connected
to an 8MHz external crystal. Tie this pin low if XTAL is driven by an
external clock source.
XTAL 81 Input/
Output
Chip-driven Crystal Oscillator Output — This output connects the internal
crystal oscillator output to an external crystal.
If an external clock is used, XTAL must be used as the input and
EXTAL connected to GND.
The input clock can be selected to provide the clock directly to the
core. This input clock can also be selected as the input clock for
the on-chip PLL.
CLKO 3 Output Tri-Stated Clock Output — This pin outputs a buffered clock signal. Using
the SIM CLKO Select Register (SIM_CLKOSR), this pin can be
programmed as any of the following: disabled, CLK_MSTR
(system clock), IPBus clock, oscillator output, prescaler clock and
postscaler clock. Other signals are also available for test
purposes.
See Part 6.5.7 for details.
56F8356 Technical Data, Rev. 10.0
Freescale Semiconductor 19
Preliminary
Table 2-2 Signal and Package Information for the 144-Pin LQFP
Signal Name Pin No. Type
State
During
Reset
Signal Description
A0
(GPIOA8)
A1
(GPIOA9)
A2
(GPIOA10)
A3
(GPIOA11)
A4
(GPIOA12)
A5
(GPIOA13)
A6
138 Output
Input/
Output
10
11
12
13
14
17 Output
Tri-stated Address Bus — A0 - A5 specify six of the address lines for
external program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), A0 - A5 and EMI control signals are tri-stated when
the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
Port A GPIO — These six GPIO pins can be individually
programmed as input or output pins.
After reset, the default state is Address Bus.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOA_PUR register.
Example: GPIOA8, clear bit 8 in the GPIOA_PUR register.
Tri-stated
Address Bus — A6 - A7 specify two of the address lines for
external program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), A6 - A7 and EMI control signals are tri-stated when
the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
(GPIOE2)
A7
(GPIOE3)
20 Freescale Semiconductor
18
Schmitt
Input/
Output
Input
56F8356 Technical Data, Rev. 10.0
Port E GPIO — These two GPIO pins can be individually
programmed as input or output pins.
After reset, the default state is Address Bus.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOE_PUR register.
Example: GPIOE2, clear bit 2 in the GPIOE_PUR register.
Preliminary
Table 2-2 Signal and Package Information for the 144-Pin LQFP
Signal Name Pin No. Type
State
During
Reset
Signal Pins
Signal Description
A8
(GPIOA0)
A9
(GPIOA1)
A10
(GPIOA2)
A11
(GPIOA3)
A12
(GPIOA4)
A13
(GPIOA5)
A14
(GPIOA6)
19 Output
Schmitt
20
21
22
23
24
25
Input/
Output
Tri-stated
Input
Address Bus— A8 - A15 specify eight of the address lines for
external program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), A8 - A15 and EMI control signals are tri-stated when
the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
Port A GPIO — These eight GPIO pins can be individually
programmed as input or output pins.
After reset, the default state is Address Bus.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOA_PUR register.
Example: GPIOA0, clear bit 0 in the GPIOA_PUR register.
A15
(GPIOA7)
Freescale Semiconductor 21
Preliminary
26
56F8356 Technical Data, Rev. 10.0
Table 2-2 Signal and Package Information for the 144-Pin LQFP
Signal Name Pin No. Type
State
During
Reset
Signal Description
GPIOB0
(A16)
D0
33 Schmitt
Input/
Output
Output
59 Input/
Output
Input
Tri-stated
Tri-stated
Port B GPIO — This GPIO pin can be programmed as an input or
output pin.
Address Bus — A16 specifies one of the address lines for
external program or data memory accesses. Depending upon the
state of the DRV bit in the EMI bus control register (BCR), A16 and
EMI control signals are tri-stated when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
After reset, the start-up state of GPIOB0 (GPIO or address) is
determined as a function of EXTBOOT, EMI_MODE and the Flash
security setting. See Table 4-4 for further information on when this
pin is configured as an address pin at reset. In all cases, this state
may be changed by writing to GPIOB_PER.
To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOB_PUR register.
Data Bus — D0 - D6 specify part of the data for external program or
data memory accesses.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), D0 - D6 are tri-stated when the external bus is
inactive.
(GPIOF9)
D1
(GPIOF10)
D2
(GPIOF11)
D3
(GPIOF12)
D4
(GPIOF13)
D5
(GPIOF14)
D6
(GPIOF15)
60
72
75
76
77
78
Input/
Output
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
Input
56F8356 Technical Data, Rev. 10.0
Port F GPIO — These seven GPIO pins can be individually
programmed as input or output pins.
At reset, these pins default to the EMI Data Bus function.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOF_PUR register.
Example: GPIOF9, clear bit 9 in the GPIOF_PUR reg i ste r.
22 Freescale Semiconductor
Preliminary
Table 2-2 Signal and Package Information for the 144-Pin LQFP
Signal Name Pin No. Type
State
During
Reset
Signal Pins
Signal Description
D7
(GPIOF0)
D8
(GPIOF1)
D9
(GPIOF2)
D10
(GPIOF3)
D11
(GPIOF4)
D12
(GPIOF5)
D13
(GPIOF6)
D14
(GPIOF7)
28 Input/
Output
Input/
Output
29
30
32
133
134
135
136
Tri-stated
Input
Data Bus — D7 - D14 specify part of the data for external program
or data memory accesses.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
Port F GPIO — These eight GPIO pins can be individually
programmed as input or output pins.
At reset, these pins default to Data Bus functionality.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOF_PUR register.
Example: GPIOF0, clear bit 0 in the GPIOF_PUR reg i ste r.
D15
(GPIOF8)
137 Input/
Output
Input/
Output
Tri-stated
Input
56F8356 Technical Data, Rev. 10.0
Data Bus — D15 specifies part of the data for external program or
data memory accesses.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
Port F GPIO — This GPIO pin can be individually programmed as
an input or output pin.
At reset, this pin defaults to the Data Bus function.
To deactivate the internal pull-up resistor, clear bit 8 in the
GPIOF_PUR register.
Freescale Semiconductor 23
Preliminary
Table 2-2 Signal and Package Information for the 144-Pin LQFP
State
Signal Name Pin No. Type
RD 45 Output Tri-stated Read Enable — RD is asserted during external memory read
During
Reset
Signal Description
cycles. When RD
and an external device is enabled onto the data bus. When RD
deasserted high, the external data is latched inside the device.
When RD is asserted, it qualifies the A0 - A16, PS, DS, and CSn
pins. RD
or ROM.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR ) , RD is
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
To deactivate the internal pull-up resistor, set the CTRL bit in the
SIM_PUDR register.
can be connected directly to the OE pin of a Static RAM
is asserted low, pins D0 - D15 become inputs
tri-stated when the external bus is inactive.
is
WR
PS
(CS0)
44 Output Tri-stated Write Enable — WR is asserted during external memory write
is asserted low, pins D0 - D15 become outputs
, DS, and CSn pins. WR can
is tri-stated when the external bus is inactive.
in the
signal. PS is asserted low for external program
is tri-stated when the external bus is inactive.
46 Output
Tri-stated
cycles. When WR
and the device puts data on the bus. When WR is deasserted high,
the external data is latched inside the external device. When WR is
asserted, it qualifies the A0 - A16, PS
be connected directly to the WE pin of a static RAM.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), WR
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
To deactivate the internal pull-up resistor, set the CTRL bit in the
SIM_PUDR register.
Program Memory Select — This signal is actually CS0
EMI, which is programmed at reset for compatibility with the
56F80x PS
memory access.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), CS0
resets to provide the PS function as defined on the 56F80x
CS0
devices.
(GPIOD8)
24 Freescale Semiconductor
Input/
Output
Input
56F8356 Technical Data, Rev. 10.0
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
To deactivate the internal pull-up resistor, clear bit 8 in the
GPIOD_PUR register.
Preliminary
Table 2-2 Signal and Package Information for the 144-Pin LQFP
Signal Name Pin No. Type
State
During
Reset
Signal Pins
Signal Description
DS
(CS1)
(GPIOD9)
GPIOD0
)
(CS2
GPIOD1
)
(CS3
47 Output
Input/
Output
48 Input/
Output
Output
49
Tri-stated
Input
Input Port D GPIO — These two GPIO pins can be individually
Data Memory Select — This signal is actually CS1
which is programmed at reset for compatibility with the 56F80x DS
signal. DS
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), DS
CS1 resets to provide the DS function as defined on the 56F80x
devices.
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
To deactivate the internal pull-up resistor, clear bit 9 in the
GPIOD_PUR register.
programmed as input or output pins.
Chip Select — CS2 - CS3 may be programmed within the EMI
module to act as chip selects for specific areas of the external
memory map.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), A0–A16 and EMI control signals are tri-stated when
the external bus is inactive.
is asserted low for external data memory access.
is tri-stated when the external bus is inactive.
in the EMI,
TXD0
(GPIOE0)
4 Output
Input/
Output
Tri-stated
Input
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
At reset, these pins are configured as GPIO.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOD_PUR register.
Example: GPIOD0, clear bit 0 in the GPIOD_PUR register.
Transmit Data — SCI0 transmit data output
Port E GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOE_PUR register.
56F8356 Technical Data, Rev. 10.0
Freescale Semiconductor 25
Preliminary
Table 2-2 Signal and Package Information for the 144-Pin LQFP
Signal Name Pin No. Type
State
During
Reset
Signal Description
RXD0
(GPIOE1)
TXD1
(GPIOD6)
RXD1
(GPIOD7)
5 Input
Input/
Output
42 Output
Input/
Output
43 Input
Input/
Output
Input
Input
Tri-stated
Input
Input
Input
Receive Data — SCI0 receive data input
Port E GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 1 in the
GPIOE_PUR register.
Transmit Data — SCI1 transmit data output
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 6 in the
GPIOD_PUR register.
Receive Data — SCI1 receive data input
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is SCI input.
TCK 121 Schmitt
Input
TMS 122 Schmitt
Input
TDI 123 Schmitt
Input
Input,
pulled low
internally
Input,
pulled high
internally
Input,
pulled high
internally
To deactivate the internal pull-up resistor, clear bit 7 in the
GPIOD_PUR register.
Test Clock Input — This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/EOnCE
port. The pin is connected internally to a pull-down resistor.
Test Mode Select Input — This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.
To deactivate the internal pull-up resistor, set the JTAG bit in the
SIM_PUDR register.
Test Data Input — This input pin provides a serial input data
stream to the JTAG/EOnCE port. It is sampled on the rising edge
of TCK and has an on-chip pull-up resistor.
To deactivate the internal pull-up resistor, set the JTAG bit in the
SIM_PUDR register.
56F8356 Technical Data, Rev. 10.0
26 Freescale Semiconductor
Preliminary
Table 2-2 Signal and Package Information for the 144-Pin LQFP
State
Signal Name Pin No. Type
TDO 124 Output Tri-stated Test Data Output — This tri-stateable output pin provides a serial
During
Reset
Signal Description
output data stream from the JTAG/EOnCE port. It is driven in the
shift-IR and shift-DR controller states, and changes on the falling
edge of TCK.
Signal Pins
TRST
PHASEA0
(TA0)
(GPIOC4)
PHASEB0
120 Schmitt
Input
139 Schmitt
Input
Schmitt
Input/
Output
Schmitt
Input/
Output
140 Schmitt
Input
Input,
pulled high
internally
Input
Input
Input
Input
Test Reset — As an input, a low signal on this pin provides a reset
signal to the JTAG TAP controller. To ensure complete hardware
reset, TRST
The only exception occurs in a debugging environment when a
hardware device reset is required and the JTAG/EOnCE module
must not be reset. In this case, assert RESET
TRST.
To deactivate the internal pull-up resistor, set the JTAG bit in the
SIM_PUDR register.
Phase A — Quadrature Decoder 0, PHASEA input
TA0 — Timer A, Channel 0
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is PHASEA0.
To deactivate the internal pull-up resistor, clear bit 4 of the
GPIOC_PUR register.
Phase B — Quadrature Decoder 0, PHASEB input
should be asserted whenever RESET is asserted.
, but do not assert
(TA1)
(GPIOC5)
Freescale Semiconductor 27
Preliminary
Schmitt
Input/
Output
Schmitt
Input/
Output
Input
Input
56F8356 Technical Data, Rev. 10.0
TA1 — Timer A, Channel
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is PHASEB0.
To deactivate the internal pull-up resistor, clear bit 5 of the
GPIOC_PUR register.
Table 2-2 Signal and Package Information for the 144-Pin LQFP
Signal Name Pin No. Type
State
During
Reset
Signal Description
INDEX0
(TA2)
(GPOPC6)
HOME0
(TA3)
(GPIOC7)
141 Schmitt
Input
Schmitt
Input/
Output
Schmitt
Input/
Output
142 Schmitt
Input
Schmitt
Input/
Output
Schmitt
Input/
Output
Input
Input
Input
Input
Input
Input
Index — Quadrature Decoder 0, INDEX input
TA2 — Timer A, Channel 2
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is INDEX0.
To deactivate the internal pull-up resistor, clear bit 6 of the
GPIOC_PUR register.
Home — Quadrature Decoder 0, HOME input
TA3 — Timer A, Channel 3
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is HOME0.
SCLK0
(GPIOE4)
130 Schmitt
Input/
Output
Schmitt
Input/
Output
Input
Input
To deactivate the internal pull-up resistor, clear bit 7 of the
GPIOC_PUR register.
SPI 0 Serial Clock — In the master mode, this pin serves as an
output, clocking slaved listeners. In slave mode, this pin serves as
the data clock input.
Port E GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is SCLK0.
To deactivate the internal pull-up resistor, clear bit 4 in the
GPIOE_PUR register.
56F8356 Technical Data, Rev. 10.0
28 Freescale Semiconductor
Preliminary
Table 2-2 Signal and Package Information for the 144-Pin LQFP
Signal Name Pin No. Type
State
During
Reset
Signal Pins
Signal Description
MOSI0
(GPIOE5)
MISO0
(GPIOE6)
132 Input/
Output
Input/
Output
131 Input/
Output
Input/
Output
Tri-stated
Input
Input
Input
SPI 0 Master Out/Slave In — This serial data pin is an output from
a master device and an input to a slave device. The master device
places data on the MOSI line a half-cycle before the clock edge
the slave device uses to latch the data.
Port E GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is MOSI0.
To deactivate the internal pull-up resistor, clear bit 5 in the
GPIOE_PUR register.
SPI 0 Master In/Slave Out — This serial data pin is an input to a
master device and an output from a slave device. The MISO line of
a slave device is placed in the high-impedance state if the slave
device is not selected. The slave device places data on the MISO
line a half-cycle before the clock edge the master device uses to
latch the data.
Port E GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is MISO0.
To deactivate the internal pull-up resistor, clear bit 6 in the
GPIOE_PUR register.
SS0
(GPIOE7)
129 Input
Input/
Output
Input
Input
56F8356 Technical Data, Rev. 10.0
SPI 0 Slave Select — SS0
SPI module that the current transfer is to be received.
Port E GPIO — This GPIO pin can be individually programmed as
input or output pin.
After reset, the default state is SS0
To deactivate the internal pull-up resistor, clear bit 7 in the
GPIOE_PUR register.
is used in slave mode to indicate to the
.
Freescale Semiconductor 29
Preliminary
Table 2-2 Signal and Package Information for the 144-Pin LQFP
Signal Name Pin No. Type
State
During
Reset
Signal Description
PHASEA1
(TB0)
(SCLK1)
(GPIOC0)
PHASEB1
6Schmitt
Input
Schmitt
Input/
Output
Schmitt
Input/
Output
Schmitt
Input/
Output
7Schmitt
Input
Input
Input
Input
Input
Input
Phase A1 — Quadrature Decoder 1, PHASEA input for decoder 1.
TB0 — Timer B, Channel 0
SPI 1 Serial Clock — In the master mode, this pin serves as an
output, clocking slaved listeners. In slave mode, this pin serves as
the data clock input. To activate the SPI function, set the
PHSA_ALT bit in the SIM_GPS register. For details, see Part
6.5.8.
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
In the 56F8356, the default state after reset is PHASEA1.
In the 56F8156, the default state is not one of the functions offered
and must be reconfigured.
To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOC_PUR register.
Phase B1 — Quadrature Decoder 1, PHASEB input for decoder 1.
(TB1)
(MOSI1)
(GPIOC1)
Schmitt
Input/
Output
Schmitt
Input/
Output
Schmitt
Input/
Output
Input
Tri-stated
Input
56F8356 Technical Data, Rev. 10.0
TB1 — Timer B, Channel 1
SPI 1 Master Out/Slave In — This serial data pin is an output from
a master device and an input to a slave device. The master device
places data on the MOSI line a half-cycle before the clock edge
the slave device uses to latch the data. To activate the SPI
function, set the PHSB_ALT bit in the SIM_GPS register. For
details, see Part 6.5.8.
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
In the 56F8356, the default state after reset is PHASEB1.
In the 56F8156, the default state is not one of the functions offered
and must be reconfigured.
To deactivate the internal pull-up resistor, clear bit 1 in the
GPIOC_PUR register.
30 Freescale Semiconductor
Preliminary
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