Foxconn M61PMV Schematics
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Foxconn M61PMV (MCP61M05)
Fab :A
PAGE PAGECONTENT CONTENT
D D
1
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3
4
5
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7
8
9
C C
10
11
12
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15
16
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19
B B
20
21
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24
01. COVER
02. BLOCK DIAGRAM
03. RESET MAP
04. CLOCK DISTRIBUTION
05. PCI DEVICE / VID TABLE
06. M2-1 Hyper Transport
07. M2-2 DDRII -1
08. M2-2 DDRII -2
09. M2-3 MISC
10. M2-4 Power
11. DDRII SDRAM DIMM1-2
12. DDRII Terminator
13. MCP61_HT
14. MCP61_PCI-E_RGM_VGA
15. MCP61_POWER
16. MCP61_PCI
17. MCP61_SATA_IDE
18. MCP61_HDA_USB
19. PCI_E X16 Slot
20. PCI SLOT 1 2 3
21. SIO IT8716F
22. IDE / Floppy / PS2
23. PLT / COM
24. FAN / HARDWARE MONITOR /VID
25. USB CONNECTORS
25
26. LAN
26
27. PWR CONN / FNT PNL / VBAT
27
28. ACPI VREG
28
29. MCP61 CORE POWER
29
30. VRM
30
31. LAN CONN
31
32. AUDIO ALC888/ALC662
32
33. Power Map
33
34. Modify List
34
35. Optional Part
35
nVIDIA MCP61 Chipset for AMD M2 CPU (3/31/2008)
A A
FOXCONN PCEG
FOXCONN PCEG
LEADTEK RESEARCH INC. ASSUMES NO RESPONSIBILITY FOR ANY ERRORS IN DRAWING THESE SCHEMATICS.
THESE SCHEMATICS ARE SUBJECT TO CHANGE AT ANY TIME WITHOUT NOTICE.
COPYRIGHT 2002 LEADTEK RESEARCH INC. .
5
4
3
Title
Title
Title
Cover
Cover
Cover
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
FOXCONN PCEG
MCP61M05
MCP61M05
MCP61M05
1
135Friday, June 27, 2008
135Friday, June 27, 2008
135Friday, June 27, 2008
AC
AC
AC
of
of
of
5
D D
4
3
2
1
MCP61M05 Block Diagram
64-BIT 800/667/533/400MHZ
POWER
SUPPLY
CONNECTOR
2*12 = 24 pin
2*2 = 4 pin (12V)
VREG -> ISL6566 => 3 phase
60 Amp
SOCKET M2
DDRII Memory CH:A
DDRII Memory CH:B
DDRII SDRAM CONN 1
DDRII SDRAM CONN 2
S I/OPWRBTN#
SWPANSWHJ
HT 16X16 2GT/S
C C
B B
FLOPPY CONN
PS2/KB CONN
PARALLEL CONN
SERIAL CONN (COM1)
SERIAL Header (COM2)
PCI Express X16
PCI Express X1
PRIMARY IDE
SATA-II CONN * 4
PCI EXPRESS Lane * 16
PCI EXPRESS Lane * 1
ATA 133
INTEGRATED SATA
SIO
ITE IT8716F/FX
4MB FLASH
LPC BUS V1.0 / 33MHZ
NFORCE
MCP61
692 Ball BGA
PCI V2.3 / 33MHZ
HDA
X8 USB ( V2.0 EHCI / V1.1 OHCI )
RGMII/MII
PCI SLOT 1
PCI SLOT 2
Azalia / ALC888 (7.1 Audio)
BACK PANEL CONN => 4 Port
USB2 PORTS 7,8
USB2 PORTS 1,6
10/100Mb (Giga-Bit )LAN PHY
FRONT PANEL Header * 2 => 4 Port
USB2 PORTS 2,3
USB2 PORTS 4,5
AC131
PCI_RESET0*
CPU_VLD
HT_VLD
SB ACPIPS_ON#
SLP_S5*
SLP_S3*
VRM_EN
VRM
PWM_GD
PWRGD_PS
PS_OUT#
ATX POWER
A A
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Block Diagram
Block Diagram
Block Diagram
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
FOXCONN PCEG
MCP61M05
MCP61M05
MCP61M05
1
235Friday, June 27, 2008
235Friday, June 27, 2008
235Friday, June 27, 2008
AC
AC
AC
of
of
of
5
4
3
2
1
RESET MAP
D D
K8 Socket M2
CPU RST*
CPU PWRGD
MCP61
AUDIO_PHY
RESET*
PSON#
HT_CPU_PWRGD
HT_CPU_RST*
PCIRST_SLOT1*
PCIRST_SLOT2*
PCIRST_SLOT3*
PCIRST_IDE*
LPCRST_FLASH*
LPCRST_SIO*
ATX
Power
Supply
PWRGD_PS
PWRGD_PS
PWR_OK
(46)
MCP61
PWRGDPWROK
SEC IDE
TIGER ONE
ALL_PWR_OK
HT_VLD
(1)
HT_VLD
ALL_PWROK
PWM_GD
(8)
VRM_EN
(9)
PWM_GD
VRM_EN
CPU
PWROK
PGOOD
(35)
ENLL
(37)
PCI SLOT 1PCI SLOT 2VT6307PRI IDEFLASHSIO
VRM
PE_RESET*
PEX X16
PEX X1
PWR CONN
C C
B B
PS ON
PWR GOOD
PWRGD SB
CIRCUIT
PWR SWTCH
PWRBTN*
SLP_S3*
POWER_GOOD
PWRGD_SB
PWR BUTTON
SLP S3*
PWRGD
PWRGD_SB
GPIO_AUX*
LAN_PHY
RESET*
HT CPU PWRGD
HT CPU RST*
PCI RST0*
PCI RST1*
PCI RST2*
PCI RST3*
LPC_RST*
AC_RESET*
POWER ON SCHEME
MCP61
SLP_S3#
PWBTN#
SLP_S5#
PWRBTN#
Power button input
PANSWHJ
PWRON#
(72)
PANSWH#
IT8716F
PSIN
(71)
PSON#
TIGER ONE
PS_ON_IN#
(6)(75) (76)
PS_ON_OUT#
(7)
A A
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Reset Map
Reset Map
Reset Map
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
FOXCONN PCEG
MCP61M05
MCP61M05
MCP61M05
1
AC
AC
335Friday, June 27, 2008
335Friday, June 27, 2008
335Friday, June 27, 2008
AC
of
of
of
5
4
3
2
1
D D
HT_CPU_TXCLK0
HT_CPU_TXCLK0*
HT_CPU_RXCLK0
HT_CPU_RXCLK0*
HT_CPU_TXCLK1
HT_CPU_TXCLK1*
HT_CPU_RXCLK1
HT_CPU_RXCLK1*
CPUCLK_IN*
CPUCLK_IN
K8 M2 CPU
MEMCLK_L[0,5,7]
MEMCLK_H[0,5,7]
MEMCLK_L[2,3]
MEMCLK_H[2,3]
MEMCLK_L[1,4,6]
MEMCLK_H[1,4,6]
NC
CHANNEL A1 0-63
CHANNEL B1 0~63
DIMM 0
DIMM 1
MCP61
CLKOUT_200MHZ
CLKOUT_200MHZ*
HT_CPU_RXCLK1*
HT_CPU_RXCLK1
HT_CPU_TXCLK1*
C C
32.768 KHZ
B B
25 MHZ
HT_CPU_TXCLK1
HT_CPU_RXCLK0*
HT_CPU_RXCLK0
HT_CPU_TXCLK0*
HT_CPU_TXCLK0
RTC_XTAL
XTAL_IN
XTAL_OUT
PE0_REFCLK
PE0_REFCLK*
PE1_REFCLK
PE1_REFCLK*
PE2_REFCLK
PE2_REFCLK*
LPC_CLK0
PCI_CLK0
PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLK_FB
LPC_CLK1
AC_BITCLK
BUF_25MHZ
BUF_SIO
SUSCLK
14MHZ OR 24MHZ
SIO
AZALIA
CODEC
PEX X16
PEX X1
FLASH
LPC
HEADER
PCI SLOT 1
PCI SLOT 2
PCI SLOT 3
LAN
PHY
A A
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Clock Distribution
Clock Distribution
Clock Distribution
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
FOXCONN PCEG
MCP61M05
MCP61M05
MCP61M05
1
435Friday, June 27, 2008
435Friday, June 27, 2008
435Friday, June 27, 2008
AC
AC
AC
of
of
of
5
4
3
2
1
D D
VID [4..0]
0X00000
0X00001
0X00010
0X00011
0X00100
0X00101
0X00110
0X00111
0X01000
0X01001
0X01010
0X01011
0X01100
0X01101
0X01110
C C
B B
0X01111
CPU VID TABLE
VDD
1.550V
1.525V
1.500V
1.475V
1.450V
1.425V
1.400V
1.375V
1.350V
1.325V
1.300V
1.275V
1.250V
1.225V
1.200V
1.175V 0X11111
SMBUS ADDRESS MAP
DEVICE
DIMM 0 0
DIMM 1 0
DIMM 2
DIMM 3
SIO
PCI SLOT 1
PCI SLOT 2
1394
DDC BUS
DDC BUS
SMBUS #
VID [4..0]
0X10000
0X10001
0X10010
0X10011
0X10100
0X10101
0X10110
0X10111
0X11000
0X11001
0X11010
0X11011
0X11100
0X11101
0X11110
VDD
1.150V
1.125V
1.100V
1.075V
1.050V
1.025V
1.000V
0.975V
0.950V
0.925V
0.900V
0.875V
0.850V
0.825V
0.800V
OFF
ADDRESS
1010 000 = 0X50
1010 001 = 0X51
0
1010 010 = 0X52
0
1010 011 = 0X53
1
0101 101 = 0X2D
ARP
1
ARP
1
1
ARP
A
?
B
?
BACK PANEL
SLOT
VT6308
PCI 1
PCI DEVICE MAP
DEVICE
MCP 61
MAC /MAC
PCI-PCI BRIDGE
SATA1 X8 0
SATA0 0 X8 0
IDE X6
MODEM CODEC 0
AUDIO CODEC X4 0
USB 2.0 X2
USB 1.1 0 X2 0
SHAPE TRIM
LDT 0 X0 0
SMBUS2
LEGACY SLAVE
LPC
LOGICAL PCI BUS
PCI SLOT 1
PCI SLOT 2
PCI SLOT 3
PCI SLOT 4
PCI SLOT 5
PCI BUS# DEVICE# IDSEL PIN PCI SLOT PCI SLOT
PCI INTERRUPT/IDSEL MAP
P_INTZ*
DEVICE#
0X01-0X0F
22
P_INTW*
23
P_INTX* P_INTW*
24
FUNCTION
XA
X9
X4
X1
X1
?
X1
?
0
0
1
1
2
1
?
0
?
01
01PCI 2
0X06
0X08
PCI BUS#
MCP51 LOGICAL
PCI BUS 0
0
00
0
0
0
0
0
0
0
0
1
DEVICE ID
0X56/57
0X005C
0X0055
0X0054
0X0053
0X0058
0X0059
0X005B
0X005A
0X005F
0X005E
0X0052
0X00D3
0X0050/51
?
P_INTX*
P_INTY*
----
INTC*INTB*INTA*
P_INTY*
P_INTZ*
PCI SLOTPCI SLOT
INTD*
SOT23
1
SOT23-6
6
12
REQ/GNT
1/1
2/2P_INTZ*
3/301 0X09
SOT23-5/SC70
SOT89-5
3
2
45
3
21
SOT223
45
3
4
321
A A
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
PCI Device / VID Table
PCI Device / VID Table
PCI Device / VID Table
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
FOXCONN PCEG
MCP61M05
MCP61M05
MCP61M05
1
535Friday, June 27, 2008
535Friday, June 27, 2008
535Friday, June 27, 2008
AC
AC
AC
of
of
of
5
D D
HT_RC_CPU_CLK_H113
HT_RC_CPU_CLK_L113
+1.2V_HT
C C
HT_RC_CPU_CAD_H[15..0]13
HT_RC_CPU_CAD_L[15..0]13
B B
HT_RC_CPU_CLK_H013
HT_RC_CPU_CLK_L013
R150 49.9 +/-1%
R150 49.9 +/-1%
*
*
R149 49.9 +/-1%
R149 49.9 +/-1%
*
*
HT_RC_CPU_CTL_H013
HT_RC_CPU_CTL_L013
4
U9A
U9A
HYPERTRANSPORT
L0_CLKIN_H(1)
L0_CLKIN_L(1)
L0_CLKIN_H(0)
L0_CLKIN_L(0)
L0_CTLIN_H(1)
L0_CTLIN_L(1)
L0_CTLIN_H(0)
L0_CTLIN_L(0)
L0_CADIN_H(15)
L0_CADIN_L(15)
L0_CADIN_H(14)
L0_CADIN_L(14)
L0_CADIN_H(13)
L0_CADIN_L(13)
L0_CADIN_H(12)
L0_CADIN_L(12)
L0_CADIN_H(11)
L0_CADIN_L(11)
L0_CADIN_H(10)
L0_CADIN_L(10)
L0_CADIN_H(9)
L0_CADIN_L(9)
J6
L0_CADIN_H(8)
L0_CADIN_L(8)
L0_CADIN_H(7)
L0_CADIN_L(7)
L0_CADIN_H(6)
L0_CADIN_L(6)
L0_CADIN_H(5)
L0_CADIN_L(5)
L0_CADIN_H(4)
L0_CADIN_L(4)
L0_CADIN_H(3)
L0_CADIN_L(3)
L0_CADIN_H(2)
L0_CADIN_L(2)
J1
L0_CADIN_H(1)
L0_CADIN_L(1)
J3
L0_CADIN_H(0)
J2
L0_CADIN_L(0)
HYPERTRANSPORT
L0_CLKOUT_H(1)
L0_CLKOUT_L(1)
L0_CLKOUT_H(0)
L0_CLKOUT_L(0)
L0_CTLOUT_H(1)
L0_CTLOUT_L(1)
L0_CTLOUT_H(0)
L0_CTLOUT_L(0)
L0_CADOUT_H(15)
L0_CADOUT_L(15)
L0_CADOUT_H(14)
L0_CADOUT_L(14)
L0_CADOUT_H(13)
L0_CADOUT_L(13)
L0_CADOUT_H(12)
L0_CADOUT_L(12)
L0_CADOUT_H(11)
L0_CADOUT_L(11)
L0_CADOUT_H(10)
L0_CADOUT_L(10)
L0_CADOUT_H(9)
L0_CADOUT_L(9)
L0_CADOUT_H(8)
L0_CADOUT_L(8)
L0_CADOUT_H(7)
L0_CADOUT_L(7)
L0_CADOUT_H(6)
L0_CADOUT_L(6)
L0_CADOUT_H(5)
L0_CADOUT_L(5)
L0_CADOUT_H(4)
L0_CADOUT_L(4)
L0_CADOUT_H(3)
L0_CADOUT_L(3)
L0_CADOUT_H(2)
L0_CADOUT_L(2)
L0_CADOUT_H(1)
L0_CADOUT_L(1)
L0_CADOUT_H(0)
L0_CADOUT_L(0)
AD5
AD4
AD1
AC1
HT_CPU_CTLOUT_H1
Y6
HT_CPU_CTLOUT_L1
W6
W2
W3
Y5
Y4
AB6
AA6
AB5
AB4
AD6
AC6
AF6
AE6
AF5
AF4
AH6
AG6
AH5
AH4
Y1
W1
AA2
AA3
AB1
AA1
AC2
AC3
AE2
AE3
AF1
AE1
AG2
AG3
AH1
AG1
N6
P6
N3
HT_CPU_CTLIN_H1
HT_CPU_CTLIN_L1
HT_RC_CPU_CAD_H15
HT_RC_CPU_CAD_L15
HT_RC_CPU_CAD_H14
HT_RC_CPU_CAD_L14
HT_RC_CPU_CAD_H13
HT_RC_CPU_CAD_L13
HT_RC_CPU_CAD_H12
HT_RC_CPU_CAD_L12
HT_RC_CPU_CAD_H11
HT_RC_CPU_CAD_L11
HT_RC_CPU_CAD_H10
HT_RC_CPU_CAD_L10
HT_RC_CPU_CAD_H9
HT_RC_CPU_CAD_L9
HT_RC_CPU_CAD_H8
HT_RC_CPU_CAD_L8
HT_RC_CPU_CAD_H7
HT_RC_CPU_CAD_L7
HT_RC_CPU_CAD_H6
HT_RC_CPU_CAD_L6
HT_RC_CPU_CAD_H5
HT_RC_CPU_CAD_L5
HT_RC_CPU_CAD_H4
HT_RC_CPU_CAD_L4
HT_RC_CPU_CAD_H3
HT_RC_CPU_CAD_L3
HT_RC_CPU_CAD_H2
HT_RC_CPU_CAD_L2
HT_RC_CPU_CAD_H1
HT_RC_CPU_CAD_L1
HT_RC_CPU_CAD_H0 HT_CPU_RC_CAD_H0
HT_RC_CPU_CAD_L0
N2
V4
V5
U1
V1
U6
V6
T4
T5
R6
T6
P4
P5
M4
M5
L6
M6
K4
K5
K6
U3
U2
R1
T1
R3
R2
N1
P1
L1
M1
L3
L2
K1
3
HT_CPU_RC_CLK_H1 13
HT_CPU_RC_CLK_L1 13
HT_CPU_RC_CLK_H0 13
HT_CPU_RC_CLK_L0 13
1
1
HT_CPU_RC_CTL_H0 13
HT_CPU_RC_CTL_L0 13
HT_CPU_RC_CAD_H15
HT_CPU_RC_CAD_L15
HT_CPU_RC_CAD_H14
HT_CPU_RC_CAD_L14
HT_CPU_RC_CAD_H13
HT_CPU_RC_CAD_L13
HT_CPU_RC_CAD_H12
HT_CPU_RC_CAD_L12
HT_CPU_RC_CAD_H11
HT_CPU_RC_CAD_L11
HT_CPU_RC_CAD_H10
HT_CPU_RC_CAD_L10
HT_CPU_RC_CAD_H9
HT_CPU_RC_CAD_L9
HT_CPU_RC_CAD_H8
HT_CPU_RC_CAD_L8
HT_CPU_RC_CAD_H7
HT_CPU_RC_CAD_L7
HT_CPU_RC_CAD_H6
HT_CPU_RC_CAD_L6
HT_CPU_RC_CAD_H5
HT_CPU_RC_CAD_L5
HT_CPU_RC_CAD_H4
HT_CPU_RC_CAD_L4
HT_CPU_RC_CAD_H3
HT_CPU_RC_CAD_L3
HT_CPU_RC_CAD_H2
HT_CPU_RC_CAD_L2
HT_CPU_RC_CAD_H1
HT_CPU_RC_CAD_L1
HT_CPU_RC_CAD_L0
TP14TP14
TP12TP12
HT_CPU_RC_CAD_H[15..0] 13
HT_CPU_RC_CAD_L[15..0] 13
2
1
Layout: Add stitching caps if crossing plane split
A A
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
M2 HyperTransport
M2 HyperTransport
M2 HyperTransport
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
5
4
3
2
FOXCONN PCEG
MCP61M05
MCP61M05
MCP61M05
635Friday, June 27, 2008
635Friday, June 27, 2008
635Friday, June 27, 2008
1
AC
AC
AC
of
of
of
5
MEMORY INTERFACE A
MEMORY INTERFACE A
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0
AG21
AG20
AC25
AA24
AC28
AE20
AE19
AD27
AA25
AC27
AB25
AB27
AA26
AA27
AC26
AD15
AE15
AG18
AG19
AG24
AG25
AG27
AG28
AF15
AF19
AH29
G19
H19
U27
U26
G20
G21
V27
W27
N25
Y27
L27
M25
M27
N24
N26
P25
Y25
N27
R24
P27
R25
R26
R27
T25
U25
T27
W24
D29
C29
C25
D25
E19
F19
F15
G15
AJ25
B29
E24
E18
H15
MA0_CLK_H(2)
MA0_CLK_L(2)
MA0_CLK_H(1)
MA0_CLK_L(1)
MA0_CLK_H(0)
MA0_CLK_L(0)
MA0_CS_L(1)
MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)
MA1_CLK_L(2)
MA1_CLK_H(1)
MA1_CLK_L(1)
MA1_CLK_H(0)
MA1_CLK_L(0)
MA1_CS_L(1)
MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_L
MA_WE_L
MA_RAS_L
MA_BANK(2)
MA_BANK(1)
MA_BANK(0)
MA_CKE(1)
MA_CKE(0)
MA_ADD(15)
MA_ADD(14)
MA_ADD(13)
MA_ADD(12)
MA_ADD(11)
MA_ADD(10)
MA_ADD(9)
MA_ADD(8)
MA_ADD(7)
MA_ADD(6)
MA_ADD(5)
MA_ADD(4)
MA_ADD(3)
MA_ADD(2)
MA_ADD(1)
MA_ADD(0)
MA_DQS_H(7)
MA_DQS_L(7)
MA_DQS_H(6)
MA_DQS_L(6)
MA_DQS_H(5)
MA_DQS_L(5)
MA_DQS_H(4)
MA_DQS_L(4)
MA_DQS_H(3)
MA_DQS_L(3)
MA_DQS_H(2)
MA_DQS_L(2)
MA_DQS_H(1)
MA_DQS_L(1)
MA_DQS_H(0)
MA_DQS_L(0)
MA_DM(7)
MA_DM(6)
MA_DM(5)
MA_DM(4)
MA_DM(3)
MA_DM(2)
MA_DM(1)
MA_DM(0)
MEM_MA0_CLK_H211,12
MEM_MA0_CLK_L211,12
MEM_MA0_CLK_H111,12
MEM_MA0_CLK_L111,12
MEM_MA0_CLK_H011,12
MEM_MA0_CLK_L011,12
MEM_MA0_CS_L111,12
MEM_MA0_CS_L011,12
D D
MEM_MA_ADD[15..0]11,12
C C
MEM_MA_DQS_H[7..0]11
MEM_MA_DQS_L[7..0]11
MEM_MA0_ODT011,12
MEM_MA_CAS_L11,12
MEM_MA_WE_L11,12
MEM_MA_RAS_L11,12
MEM_MA_BANK211,12
MEM_MA_BANK111,12
MEM_MA_BANK011,12
MEM_MA_CKE011,12
MEM_MA_DM[7..0]11
4
U9B
U9B
MA_DATA(63)
MA_DATA(62)
MA_DATA(61)
MA_DATA(60)
MA_DATA(59)
MA_DATA(58)
MA_DATA(57)
MA_DATA(56)
MA_DATA(55)
MA_DATA(54)
MA_DATA(53)
MA_DATA(52)
MA_DATA(51)
MA_DATA(50)
MA_DATA(49)
MA_DATA(48)
MA_DATA(47)
MA_DATA(46)
MA_DATA(45)
MA_DATA(44)
MA_DATA(43)
MA_DATA(42)
MA_DATA(41)
MA_DATA(40)
MA_DATA(39)
MA_DATA(38)
MA_DATA(37)
MA_DATA(36)
MA_DATA(35)
MA_DATA(34)
MA_DATA(33)
MA_DATA(32)
MA_DATA(31)
MA_DATA(30)
MA_DATA(29)
MA_DATA(28)
MA_DATA(27)
MA_DATA(26)
MA_DATA(25)
MA_DATA(24)
MA_DATA(23)
MA_DATA(22)
MA_DATA(21)
MA_DATA(20)
MA_DATA(19)
MA_DATA(18)
MA_DATA(17)
MA_DATA(16)
MA_DATA(15)
MA_DATA(14)
MA_DATA(13)
MA_DATA(12)
MA_DATA(11)
MA_DATA(10)
MA_DATA(9)
MA_DATA(8)
MA_DATA(7)
MA_DATA(6)
MA_DATA(5)
MA_DATA(4)
MA_DATA(3)
MA_DATA(2)
MA_DATA(1)
MA_DATA(0)
MA_DQS_H(8)
MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)
MA_CHECK(6)
MA_CHECK(5)
MA_CHECK(4)
MA_CHECK(3)
MA_CHECK(2)
MA_CHECK(1)
MA_CHECK(0)
AE14
AG14
AG16
AD17
AD13
AE13
AG15
AE16
AG17
AE18
AD21
AG22
AE17
AF17
AF21
AE21
AF23
AE23
AJ26
AG26
AE22
AG23
AH25
AF25
AJ28
AJ29
AF29
AE26
AJ27
AH27
AG29
AF27
E29
E28
D27
C27
G26
F27
C28
E27
F25
E25
E23
D23
E26
C26
G23
F23
E22
E21
F17
G17
G22
F21
G18
E17
G16
E15
G13
H13
H17
E16
E14
G14
J28
J27
J25
K25
J26
G28
G27
L24
K27
H29
H27
MEM_MA_DATA63
MEM_MA_DATA62
MEM_MA_DATA61
MEM_MA_DATA60
MEM_MA_DATA59
MEM_MA_DATA58
MEM_MA_DATA57
MEM_MA_DATA56
MEM_MA_DATA55
MEM_MA_DATA54
MEM_MA_DATA53
MEM_MA_DATA52
MEM_MA_DATA51
MEM_MA_DATA50
MEM_MA_DATA49
MEM_MA_DATA48
MEM_MA_DATA47
MEM_MA_DATA46
MEM_MA_DATA45
MEM_MA_DATA44
MEM_MA_DATA43
MEM_MA_DATA42
MEM_MA_DATA41
MEM_MA_DATA40
MEM_MA_DATA39
MEM_MA_DATA38
MEM_MA_DATA37
MEM_MA_DATA36
MEM_MA_DATA35
MEM_MA_DATA34
MEM_MA_DATA33
MEM_MA_DATA32
MEM_MA_DATA31
MEM_MA_DATA30
MEM_MA_DATA29
MEM_MA_DATA28
MEM_MA_DATA27
MEM_MA_DATA26
MEM_MA_DATA25
MEM_MA_DATA24
MEM_MA_DATA23
MEM_MA_DATA22
MEM_MA_DATA21
MEM_MA_DATA20
MEM_MA_DATA19
MEM_MA_DATA18
MEM_MA_DATA17
MEM_MA_DATA16
MEM_MA_DATA15
MEM_MA_DATA14
MEM_MA_DATA13
MEM_MA_DATA12
MEM_MA_DATA11
MEM_MA_DATA10
MEM_MA_DATA9
MEM_MA_DATA8
MEM_MA_DATA7
MEM_MA_DATA6
MEM_MA_DATA5
MEM_MA_DATA4
MEM_MA_DATA3
MEM_MA_DATA2
MEM_MA_DATA1
MEM_MA_DATA0
MEM_MA_CHECK7
MEM_MA_CHECK6
MEM_MA_CHECK5
MEM_MA_CHECK4
MEM_MA_CHECK3
MEM_MA_CHECK2
MEM_MA_CHECK1
MEM_MA_CHECK0
MEM_MA_DQS_H8 11
MEM_MA_DQS_L8 11
MEM_MA_DM8 11
MEM_MA_DATA[63..0] 11
MEM_MA_CHECK[7..0] 11
3
2
1
B B
A A
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
M2- 2 DDR -1
M2- 2 DDR -1
M2- 2 DDR -1
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
5
4
3
2
FOXCONN PCEG
MCP61M05
MCP61M05
MCP61M05
735Friday, June 27, 2008
735Friday, June 27, 2008
735Friday, June 27, 2008
1
AC
AC
AC
of
of
of
5
D D
C C
MEM_MB_ADD[15..0]11,12
MEM_MB_DQS_H[7..0]11
MEM_MB_DQS_L[7..0]11
B B
MEM_MB_DM[7..0]11
4
U9C
U9C
MEMORY INTERFACE B
MEMORY INTERFACE B
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_DM7
MEM_MB_DM6
MEM_MB_DM5
MEM_MB_DM4
MEM_MB_DM3
MEM_MB_DM2
MEM_MB_DM1
MEM_MB_DM0
AK19
AE30
AC31
AD29
AE29
AB31
AD31
AC29
AC30
AB29
AA31
AA28
AE31
AA29
AA30
AK13
AK17
AK23
AH17
AK29
AJ19
AL19
AL18
W29
W28
AJ13
AJ17
AL23
AL28
AL29
AJ14
AJ23
A18
A19
U31
U30
C19
D19
N31
M31
M29
N28
N29
N30
P29
P31
R29
R28
R31
R30
T31
T29
U29
U28
D31
C31
C24
C23
D17
C17
C14
C13
C30
A23
B17
B13
MB0_CLK_H(2)
MB0_CLK_L(2)
MB0_CLK_H(1)
MB0_CLK_L(1)
MB0_CLK_H(0)
MB0_CLK_L(0)
MB0_CS_L(1)
MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)
MB1_CLK_L(2)
MB1_CLK_H(1)
MB1_CLK_L(1)
MB1_CLK_H(0)
MB1_CLK_L(0)
MB1_CS_L(1)
MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_L
MB_WE_L
MB_RAS_L
MB_BANK(2)
MB_BANK(1)
MB_BANK(0)
MB_CKE(1)
MB_CKE(0)
MB_ADD(15)
MB_ADD(14)
MB_ADD(13)
MB_ADD(12)
MB_ADD(11)
MB_ADD(10)
MB_ADD(9)
MB_ADD(8)
MB_ADD(7)
MB_ADD(6)
MB_ADD(5)
MB_ADD(4)
MB_ADD(3)
MB_ADD(2)
MB_ADD(1)
MB_ADD(0)
MB_DQS_H(7)
MB_DQS_L(7)
MB_DQS_H(6)
MB_DQS_L(6)
MB_DQS_H(5)
MB_DQS_L(5)
MB_DQS_H(4)
MB_DQS_L(4)
MB_DQS_H(3)
MB_DQS_L(3)
MB_DQS_H(2)
MB_DQS_L(2)
MB_DQS_H(1)
MB_DQS_L(1)
MB_DQS_H(0)
MB_DQS_L(0)
MB_DM(7)
MB_DM(6)
MB_DM(5)
MB_DM(4)
MB_DM(3)
MB_DM(2)
MB_DM(1)
MB_DM(0)
MB_DATA(63)
MB_DATA(62)
MB_DATA(61)
MB_DATA(60)
MB_DATA(59)
MB_DATA(58)
MB_DATA(57)
MB_DATA(56)
MB_DATA(55)
MB_DATA(54)
MB_DATA(53)
MB_DATA(52)
MB_DATA(51)
MB_DATA(50)
MB_DATA(49)
MB_DATA(48)
MB_DATA(47)
MB_DATA(46)
MB_DATA(45)
MB_DATA(44)
MB_DATA(43)
MB_DATA(42)
MB_DATA(41)
MB_DATA(40)
MB_DATA(39)
MB_DATA(38)
MB_DATA(37)
MB_DATA(36)
MB_DATA(35)
MB_DATA(34)
MB_DATA(33)
MB_DATA(32)
MB_DATA(31)
MB_DATA(30)
MB_DATA(29)
MB_DATA(28)
MB_DATA(27)
MB_DATA(26)
MB_DATA(25)
MB_DATA(24)
MB_DATA(23)
MB_DATA(22)
MB_DATA(21)
MB_DATA(20)
MB_DATA(19)
MB_DATA(18)
MB_DATA(17)
MB_DATA(16)
MB_DATA(15)
MB_DATA(14)
MB_DATA(13)
MB_DATA(12)
MB_DATA(11)
MB_DATA(10)
MB_DATA(9)
MB_DATA(8)
MB_DATA(7)
MB_DATA(6)
MB_DATA(5)
MB_DATA(4)
MB_DATA(3)
MB_DATA(2)
MB_DATA(1)
MB_DATA(0)
MB_DQS_H(8)
MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)
MB_CHECK(6)
MB_CHECK(5)
MB_CHECK(4)
MB_CHECK(3)
MB_CHECK(2)
MB_CHECK(1)
MB_CHECK(0)
MEM_MB0_CLK_H211,12
MEM_MB0_CLK_L211,12
MEM_MB0_CLK_H111,12
MEM_MB0_CLK_L111,12
MEM_MB0_CLK_H011,12
MEM_MB0_CLK_L011,12
MEM_MB0_CS_L111,12
MEM_MB0_CS_L011,12
MEM_MB0_ODT011,12
MEM_MB_CAS_L11,12
MEM_MB_WE_L11,12
MEM_MB_RAS_L11,12
MEM_MB_BANK211,12
MEM_MB_BANK111,12
MEM_MB_BANK011,12
MEM_MB_CKE011,12
AH13
AL13
AL15
AJ15
AF13
AG13
AL14
AK15
AL16
AL17
AK21
AL21
AH15
AJ16
AH19
AL20
AJ22
AL22
AL24
AK25
AJ21
AH21
AH23
AJ24
AL27
AK27
AH31
AG30
AL25
AL26
AJ30
AJ31
E31
E30
B27
A27
F29
F31
A29
A28
A25
A24
C22
D21
A26
B25
B23
A22
B21
A20
C16
D15
C21
A21
A17
A16
B15
A14
E13
F13
C15
A15
A13
D13
J31
J30
J29
K29
K31
G30
G29
L29
L28
H31
G31
3
MEM_MB_DATA63
MEM_MB_DATA62
MEM_MB_DATA61
MEM_MB_DATA60
MEM_MB_DATA59
MEM_MB_DATA58
MEM_MB_DATA57
MEM_MB_DATA56
MEM_MB_DATA55
MEM_MB_DATA54
MEM_MB_DATA53
MEM_MB_DATA52
MEM_MB_DATA51
MEM_MB_DATA50
MEM_MB_DATA49
MEM_MB_DATA48
MEM_MB_DATA47
MEM_MB_DATA46
MEM_MB_DATA45
MEM_MB_DATA44
MEM_MB_DATA43
MEM_MB_DATA42
MEM_MB_DATA41
MEM_MB_DATA40
MEM_MB_DATA39
MEM_MB_DATA38
MEM_MB_DATA37
MEM_MB_DATA36
MEM_MB_DATA35
MEM_MB_DATA34
MEM_MB_DATA33
MEM_MB_DATA32
MEM_MB_DATA31
MEM_MB_DATA30
MEM_MB_DATA29
MEM_MB_DATA28
MEM_MB_DATA27
MEM_MB_DATA26
MEM_MB_DATA25
MEM_MB_DATA24
MEM_MB_DATA23
MEM_MB_DATA22
MEM_MB_DATA21
MEM_MB_DATA20
MEM_MB_DATA19
MEM_MB_DATA18
MEM_MB_DATA17
MEM_MB_DATA16
MEM_MB_DATA15
MEM_MB_DATA14
MEM_MB_DATA13
MEM_MB_DATA12
MEM_MB_DATA11
MEM_MB_DATA10
MEM_MB_DATA9
MEM_MB_DATA8
MEM_MB_DATA7
MEM_MB_DATA6
MEM_MB_DATA5
MEM_MB_DATA4
MEM_MB_DATA3
MEM_MB_DATA2
MEM_MB_DATA1
MEM_MB_DATA0
MEM_MB_CHECK7
MEM_MB_CHECK6
MEM_MB_CHECK5
MEM_MB_CHECK4
MEM_MB_CHECK3
MEM_MB_CHECK2
MEM_MB_CHECK1
MEM_MB_CHECK0
MEM_MB_DQS_H8 11
MEM_MB_DQS_L8 11
MEM_MB_DM8 11
MEM_MB_DATA[63..0] 11
MEM_MB_CHECK[7..0] 11
2
1
A A
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
M2- 2 DDR -2
M2- 2 DDR -2
M2- 2 DDR -2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
FOXCONN PCEG
MCP61M05
MCP61M05
MCP61M05
1
835Friday, June 27, 2008
835Friday, June 27, 2008
835Friday, June 27, 2008
AC
AC
AC
of
of
of
5
Level translation buffers
Assuming system devices
Do not provide VDDIO
compatible voltage levels
D D
CPU_ALL_PWROK13
CPU_LDTSTOP_L13
CPU_HT_RESET_L13
near CPU
U9E
U9E
INTERNAL MISC
INTERNAL MISC
L25
RSVD1
L26
RSVD2
L31
RSVD3
L30
RSVD4
C C
B B
5
6
7
8
9
10
11
12
1
2
13
14
15
A A
16
17
18
19
20
W26
RSVD5
W25
RSVD6
AE27
RSVD7
U24
RSVD8
V24
RSVD9
AE28
RSVD10
Y31
RSVD11
Y30
RSVD12
AG31
RSVD13
V31
RSVD14
W31
RSVD15
AF31
RSVD16
U9JU9J
MTG1
MTG1
MTG1
MTG1
MTG1
MTG1
MTG1
MTG1
EMI
EMI
MTG2
MTG2
MTG2
MTG2
MTG2
MTG2
MTG2
MTG2
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
MTG3
MTG3
MTG3
MTG3
MTG3
MTG3
MTG3
MTG3
MTG4
MTG4
MTG4
MTG4
MTG4
MTG4
MTG4
MTG4
E20
B19
AL4
AK4
AK3
F2
F3
G4
G3
G5
AD25
AE24
AE25
AJ18
AJ20
C18
C20
G24
G25
H25
V29
W30
21
22
23
24
25
26
27
28
3
EMI
4
EMI
29
30
31
32
33
34
35
36
+1.8V_SUS
RN24
RN24
*
*
135
300
300
+/-5%
+/-5%
C190
C190
0.22uF
0.22uF
*
*
Dummy
Dummy
4
+2.5V
*
*
Keep trace to resistor
less than 600mils from CPU pin and
trace to AC caps less than 1250mils
78
642
CPU_CLKIN_H13
CPU_CLKIN_L13
CPU_SIC18
CPU_SID18
modify 8/20
C199
C199
22uF
22uF
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
+1.8V_SUS
R164
R164
300
300
*
*
*
*
+/-5%
+/-5%
*
*
Dummy
Dummy
+1.8V_SUS
R179 39.2 +/-1%
R179 39.2 +/-1%
*
*
R180 39.2 +/-1%
R180 39.2 +/-1%
*
*
CPU_THERMDC24
CPU_THERMDA24
CPU_M_VREF_SUS
+1.8V_SUS
R172
R172
*
*
16.9 Ohm
16.9 Ohm
+/-1%
+/-1%
R171
R171
*
*
16.9 Ohm
16.9 Ohm
*
*
+/-1%
+/-1%
*
*
C191
C191
3.9nF
3.9nF
+/-10%
+/-10%
*
*
R154
R154
*
*
C188
C188
169 Ohm
169 Ohm
3.9nF
3.9nF
+/-1%
+/-1%
+/-10%
+/-10%
*
*
CPU_SIC
R162
R162
CPU_SID
300
300
+/-5%
+/-5%
R161
R161
300
300
+/-5%
+/-5%
CPU_VDD_RUN_FB_H30
CPU_VDD_RUN_FB_L30
TP26TP26
CPU_M_VREF_SUS
R168 300 +/-5%
R168 300 +/-5%
R167 300 +/-5%
R167 300 +/-5%
TP16TP16
TP15TP15
TP20TP20
TP13TP13
TP18TP18
CPU_M_VREF_SUS
C197
C197
*
*
100nF
100nF
C211
C211
4.7uF
4.7uF
*
*
+80/-20%
+80/-20%
CPU_CLKIN_SC_H
CPU_CLKIN_SC_L
CPU_ALL_PWROK
CPU_LDTSTOP_L
CPU_HT_RESET_L
CPU_PRESENT_L
CPU_TDI
CPU_TRST_L
CPU_TCK
CPU_TMS
CPU_DBREQ_L
1
M_ZN
M_ZP
*
*
*
*
CPU_TEST17
1
CPU_TEST16
1
CPU_TEST15
1
CPU_TEST14
1
CPU_TEST12
1
CPU_THERMDC
CPU_THERMDA CPU_TEST26
C196
C196
1nF
1nF
Layout: Place near CPU socket
C200
C200
3.3nF
3.3nF
+/-10%
+/-10%
CPU_TEST25_H
CPU_TEST25_L
*
*
CPU_VDDA_RUN
C201
C201
0.22uF
0.22uF
10V, X7R, +/-10%
10V, X7R, +/-10%
AL10
AJ10
AH10
AH11
AJ11
3
C10
D10
A8
B8
C9
D8
C7
AL3
AL6
AK6
AL9
A5
G2
G1
E12
F12
A10
B10
F10
E9
AJ7
F6
D6
E7
F8
C5
AH9
E5
AJ5
AG9
AG8
AH7
AJ6
U9D
U9D
MISC
MISC
VDDA1
VDDA2
CLKIN_H
CLKIN_L
PWROK
LDTSTOP_L
RESET_L
CPU_PRESENT_L
SIC
SID
TDI
TRST_L
TCK
TMS
DBREQ_L
VDD_FB_H
VDD_FB_L
VTT_SENSE
M_VREF
M_ZN
M_ZP
TEST25_H
TEST25_L
TEST19
TEST18
TEST13
TEST9
TEST17
TEST16
TEST15
TEST14
TEST12
TEST7
TEST6
THERMDC
THERMDA
TEST3
TEST2
VID(5)
VID(4)
VID(3)
VID(2)
VID(1)
VID(0)
THERMTRIP_L
PROCHOT_L
DBRDY
VDDIO_FB_H
VDDIO_FB_L
PSI_L
HTREF1
HTREF0
TEST29_H
TEST29_L
TEST24
TEST23
TEST22
TEST21
TEST20
TEST28_H
TEST28_L
TEST27
TEST26
TEST10
TEST8
TDO
Required for compatibility
with future processors
CPU_VID5
D2
D1
C1
E3
E2
E1
AK7
AL7
AK10
B6
AK11
AL11
F1
V8
V7
C11
D11
AK8
AH8
AJ9
AL8
AJ8
J10
H9
AK9
AK5
G7
D4
CPU_VID4
CPU_VID3
CPU_VID2
CPU_VID1
CPU_VID0
CPU_THERMTRIP_L
CPU_PROCHOT_L_1.8
CPU_TDO
CPU_DBRDY
CPU_VDDIO_SUS_FB_H
CPU_VDDIO_SUS_FB_L
CPU_PSI_LCPU_VTT_SUS_SENSE
CPU_HTREF1
CPU_HTREF0
CPU_TEST29_H
CPU_TEST29_L
CPU_TEST23
CPU_TEST22
CPU_TEST21
1
2
+1.8V_SUS
R174
R174
R170
R170
300
300
+/-5%
+/-5%
TP7TP7
TP8TP8
1
R160 44.2Ohm +/-1%
R160 44.2Ohm +/-1%
R157 44.2Ohm +/-1%
R157 44.2Ohm +/-1%
TP17TP17
1
TP19TP19
1
CPU_DBREQ_L
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST_L
CPU_TDO
Erratum 133, Revision Guide for
AMD NPT 0Fh Processors
Erratum 133, Revision Guide for
AMD NPT 0Fh Processors
*
*
*
*
300
300
+/-5%
+/-5%
CPU_PROCHOT_L_1.8 13
R175
R175
*
*
300
300
+/-5%
+/-5%
*
*
*
*
R173
R173
*
*
80.6
80.6
+/-1%
+/-1%
CPU_DBREQ_L
CPU_TEST26
CPU_PRESENT_L
CPU_TEST25_H
CPU_TEST25_L
CPU_TEST21
CPU_TEST22
VREG_VID4 30
VREG_VID3 30
VREG_VID2 30
VREG_VID1 30
VREG_VID0 30
CPU_THERMTRIP* 13,21
+1.2V_HT
Keep trace to resistors
less than 1.5" from CPU pin
Route as 80-Ohm differential impedance
Keep trace to resistor less than 1" from CPU pin
+1.8V_SUS
HDT
HDT
HHS2X13JZO25H70
HHS2X13JZO25H70
112
2
3 4
5 6
7 8
9 10
111112
12
13 14
15 16
17 18
19 20
212122
22
23 24
26
0.050IN
0.050IN
DUMMY
DUMMY
Dummy
Dummy
R158 300 +/-5%
R158 300 +/-5%
R159 1K +/-5%
R159 1K +/-5%
R166 510 Ohm
R166 510 Ohm
R165 510 Ohm
R165 510 Ohm
R178 300 +/-5%
R178 300 +/-5%
Dummy
Dummy
CPU_HT_RESET_L
26
+1.8V_SUS
R177
R177
300
300
*
*
+/-5%
+/-5%
*
*
*
*
*
*
*
*
*
*
*
*
R176
R176
300
300
+/-5%
+/-5%
+/-5%
+/-5%
+/-5%
+/-5%
CPU_VDDA_RUN
CPU_CLKIN_H
CPU_CLKIN_L
CPU_VDD_RUN_FB_H
CPU_VDD_RUN_FB_L
CPU_TEST29_H
CPU_TEST29_L
CPU_VDDIO_SUS_FB_H
CPU_VDDIO_SUS_FB_L
CPU_ALL_PWROK
CPU_LDTSTOP_L
CPU_HT_RESET_L
CPU_THERMTRIP_L
1
TP21TP21
1
TP4TP4
1
TP3TP3
1
TP6TP6
1
TP5TP5
1
TP22TP22
1
TP25TP25
1
TP24TP24
1
TP23TP23
1
TP11TP11
1
TP10TP10
1
TP9TP9
1
TP27TP27
1
FOXCONN PCEG
FOXCONN PCEG
GND
5
4
3
2
Title
Title
Title
M2- 3 MISC
M2- 3 MISC
M2- 3 MISC
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
FOXCONN PCEG
MCP61M05
MCP61M05
MCP61M05
1
AC
AC
935Friday, June 27, 2008
935Friday, June 27, 2008
935Friday, June 27, 2008
AC
of
of
of
5
4
3
2
1
Processor Power & Ground
D D
VLDT_RUN_B is connected to the VLDT_RUN power
supply through the package or on the die. It is only connected
+V_CPU
C C
B B
AC10
AE10
AA10
AA12
AA14
AA16
AA18
AB11
U9F
U9F
VDD1
VDD1
A4
VDD1
A6
VDD2
AA8
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
AB7
VDD9
AB9
VDD10
VDD11
AC4
VDD12
AC5
VDD13
AC8
VDD14
VDD15
AD2
VDD16
AD3
VDD17
AD7
VDD18
AD9
VDD19
VDD20
AF7
VDD21
AF9
VDD22
AG4
VDD23
AG5
VDD24
AG7
VDD25
AH2
VDD26
AH3
VDD27
B3
VDD28
B5
VDD29
B7
VDD30
C2
VDD31
C4
VDD32
C6
VDD33
C8
VDD34
D3
VDD35
D5
VDD36
D7
VDD37
D9
VDD38
E4
VDD39
E6
VDD40
E8
VDD41
E10
VDD42
F5
VDD43
F7
VDD44
F9
VDD45
F11
VDD46
G6
VDD47
G8
VDD48
G10
VDD49
G12
VDD50
H7
VDD51
H11
VDD52
H23
VDD53
J8
VDD54
J12
VDD55
J14
VDD56
J16
VDD57
J18
VDD58
J20
VDD59
J22
VDD60
J24
VDD61
K7
VDD62
K9
VDD63
K11
VDD64
K13
VDD65
K15
VDD66
K17
VDD67
K19
VDD68
K21
VDD69
K23
VDD70
L4
VDD71
L5
VDD72
L8
VDD73
L10
VDD74
L12
VDD75
Y17
VDD150
Y19
VDD151
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS240
VSS241
A3
A7
A9
A11
AA4
AA5
AA7
AA9
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AB2
AB3
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC7
AC9
AC11
AC13
AC15
AC17
AC19
AC21
AC23
AD8
AD10
AD12
AD14
AD16
AD20
AD22
AD24
AE4
AE5
AE9
AE11
AF2
AF3
AF8
AF10
AF12
AF14
AF16
AF18
AF20
AF22
AF24
AF26
AF28
AG10
AG11
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH30
AK2
AK14
AK16
AK18
Y14
Y16
GND
+V_CPU
W10
W12
W14
W16
W18
W20
U9G
U9G
VDD2
VDD2
L14
VDD1
L16
VDD2
L18
VDD3
M2
VDD4
M3
VDD5
M7
VDD6
M9
VDD7
M11
VDD8
M13
VDD9
M15
VDD10
M17
VDD11
M19
VDD12
N8
VDD13
N10
VDD14
N12
VDD15
N14
VDD16
N16
VDD17
N18
VDD18
P7
VDD19
P9
VDD20
P11
VDD21
P13
VDD22
P15
VDD23
P17
VDD24
P19
VDD25
R4
VDD26
R5
VDD27
R8
VDD28
R10
VDD29
R12
VDD30
R14
VDD31
R16
VDD32
R18
VDD33
R20
VDD34
T2
VDD35
T3
VDD36
T7
VDD37
T9
VDD38
T11
VDD39
T13
VDD40
T15
VDD41
T17
VDD42
T19
VDD43
T21
VDD44
U8
VDD45
U10
VDD46
U12
VDD47
U14
VDD48
U16
VDD49
U18
VDD50
U20
VDD51
V9
VDD52
V11
VDD53
V13
VDD54
V15
VDD55
V17
VDD56
V19
VDD57
V21
VDD58
W4
VDD59
W5
VDD60
W8
VDD61
VDD62
VDD63
VDD64
VDD65
VDD66
VDD67
Y2
VDD68
Y3
VDD69
Y7
VDD70
Y9
VDD71
Y11
VDD72
Y13
VDD73
Y15
VDD74
Y21
VDD75
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
AK20
AK22
AK24
AK26
AK28
AK30
AL5
B4
B9
B11
B14
B16
B18
B20
B22
B24
B26
B28
B30
C3
D14
D16
D18
D20
D22
D24
D26
D28
D30
E11
F4
F14
F16
F18
F20
F22
F24
F26
F28
F30
G9
G11
H8
H10
H12
H14
H16
H18
H22
H24
H26
H28
H30
J4
J5
J7
J9
J11
J13
J15
J17
J19
J21
J23
K2
K3
K8
K10
K12
K14
K16
K18
K20
K22
Y18
GND
+V_CPU
AA20
AA22
AB13
AB15
AB17
AB19
AB21
AB23
AC12
AC14
AC16
AC18
AC20
AC22
AD11
AD23
AE12
AF11
U9H
U9H
VDD3
VDD3
N17
VSS1
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
L20
VDD19
L22
VDD20
M21
VDD21
M23
VDD22
N20
VDD23
N22
VDD24
P21
VDD25
P23
VDD26
R22
VDD27
T23
VDD28
U22
VDD29
V23
VDD30
W22
VDD31
Y23
VDD32
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
N19
N21
N23
P2
P3
P8
P10
P12
P14
P16
P18
P20
P22
R7
R9
R11
R13
R15
R17
R19
R21
R23
T8
T10
T12
T14
T16
T18
T20
T22
U4
U5
U7
U9
U11
U13
U15
U17
U19
U21
U23
V2
V3
V10
V12
V14
V16
V18
V20
V22
W9
W11
W13
W15
W17
W19
W21
W23
Y8
Y10
Y12
W7
Y20
Y22
GND
Place near processor on VLDT pour.
4
+1.2V_HT
*
*
C184
C184
4.7uF
4.7uF
C185
C185
100nF
100nF
*
*
+80%~-20%
+80%~-20%
+80/-20%
+80/-20%
GND
A A
5
on the board to decoupling near the CPU package.
U9I
+1.2V_HT
VTT_DDR_SUS VTT_DDR_SUS
+1.8V_SUS
AB24
AB26
AB28
AB30
AC24
AD26
AD28
AD30
AF30
U9I
VDDIO
VDDIO
AJ4
VLDT_A1
AJ3
VLDT_A2
AJ2
VLDT_A3
AJ1
VLDT_A4
D12
VTT1
C12
VTT2
B12
VTT3
A12
VTT4
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO29
M24
VDDIO9
M26
VDDIO10
M28
VDDIO11
M30
VDDIO12
P24
VDDIO13
P26
VDDIO14
P28
VDDIO15
P30
VDDIO16
T24
VDDIO17
T26
VDDIO18
T28
VDDIO19
T30
VDDIO20
V25
VDDIO21
V26
VDDIO22
V28
VDDIO23
V30
VDDIO24
Y24
VDDIO25
Y26
VDDIO26
Y28
VDDIO27
Y29
VDDIO28
VLDT_B1
VLDT_B2
VLDT_B3
VLDT_B4
VTT5
VTT6
VTT7
VTT8
VTT9
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
H6
H5
H2
H1
AK12
AJ12
AH12
AG12
AL12
K24
K26
K28
K30
L7
L9
L11
L13
L15
L17
L19
L21
L23
M8
M10
M12
M14
M16
M18
M20
M22
N4
N5
N7
N9
N11
N13
N15
GND
Decoupling Between Processor and DIMMs
Place as close to processor as possible.
+1.8V_SUS
C334
C334
C346
C346
C342
C342
C357
C357
4.7uF
*
*
VTT_DDR_SUS
*
*
VTT_DDR_SUS
*
*
3
4.7uF
4.7uF
C205
C205
4.7uF
4.7uF
C203
C203
4.7uF
4.7uF
4.7uF
*
*
+80/-20%
+80/-20%
C202
C202
4.7uF
4.7uF
*
*
+80/-20%
+80/-20%
C206
C206
4.7uF
4.7uF
*
*
+80/-20%
+80/-20%
0.22uF
0.22uF
0.22uF
0.22uF
*
*
*
*
+80/-20%
+80/-20%
GND
10V, X7R, +/-10%
10V, X7R, +/-10%
10V, X7R, +/-10%
10V, X7R, +/-10%
C222
C222
C218
C218
0.22uF
0.22uF
*
*
+80/-20%
+80/-20%
C217
C217
0.22uF
0.22uF
*
*
+80/-20%
+80/-20%
10V, X7R, +/-10%
10V, X7R, +/-10%
10V, X7R, +/-10%
10V, X7R, +/-10%
C208
C208
0.22uF
0.22uF
1nF
1nF
*
*
*
*
10V, X7R, +/-10%
10V, X7R, +/-10%
C220
C220
C207
C207
0.22uF
0.22uF
1nF
1nF
*
*
*
*
10V, X7R, +/-10%
10V, X7R, +/-10%
C404
C404
C416
C416
180pF
180pF
1nF
1nF
*
*
*
*
+/-5%
+/-5%
50V, X7R, +/-10%
50V, X7R, +/-10%
50V, X7R, +/-10%
50V, X7R, +/-10%
C400
C400
C209
C209
180pF
180pF
1nF
1nF
*
*
*
*
+/-5%
+/-5%
50V, X7R, +/-10%
50V, X7R, +/-10%
50V, X7R, +/-10%
50V, X7R, +/-10%
VLDT_RUN_B
*
*
GND
C401
C401
180pF
180pF
*
*
+/-5%
+/-5%
GND
C204
C204
180pF
180pF
*
*
+/-5%
+/-5%
GND
C173
C173
+80/-20%
+80/-20%
4.7uF
4.7uF
Bottomside Decoupling
+V_CPU
C490
C490
22uF
22uF
*
*
Dummy
Dummy
+V_CPU
C486
C486
0.22uF
0.22uF
*
*
Dummy
Dummy
+1.8V_SUS
C505
C505
10uF
10uF
*
*
+/-10%
+/-10%
C502
C502
10uF
10uF
*
*
+/-10%
+/-10%
6.3V, X5R, +/-10%
6.3V, X5R, +/-10%
Dummy
Dummy
C504
C504
0.22uF
0.22uF
*
*
10V, X7R, +/-10%
10V, X7R, +/-10%
10V, X7R, +/-10%
10V, X7R, +/-10%
modify 8/16
C506
C506
10uF
10uF
*
*
+/-10%
+/-10%
*
*
Dummy
Dummy
*
*
*
*
C492
C492
22uF
22uF
C493
C493
0.22uF
0.22uF
C509
C509
4.7uF
4.7uF
6.3V, X5R, +/-10%
6.3V, X5R, +/-10%
10V, X7R, +/-10%
10V, X7R, +/-10%
+80/-20%
+80/-20%
*
*
*
*
Dummy
Dummy
*
*
C491
C491
10uF
10uF
+/-10%
+/-10%
C133
C133
10nF
10nF
C508
C508
4.7uF
4.7uF
25V, X7R, +/-10%
25V, X7R, +/-10%
+80/-20%
+80/-20%
*
*
Dummy
Dummy
*
*
GND
*
*
C499
C499
22uF
22uF
*
*
6.3V, X5R, +/-10%
6.3V, X5R, +/-10%
Dummy
Dummy
C494
C494
180pF
180pF
50V, NPO, +/-5%
50V, NPO, +/-5%
C507
C507
0.22uF
0.22uF
*
*
10V, X7R, +/-10%
10V, X7R, +/-10%
modify 8/16
C498
C498
C497
C497
10uF
10uF
10uF
10uF
*
*
*
*
+/-10%
+/-10%
+/-10%
+/-10%
C511
C511
C510
C510
0.22uF
0.22uF
0.22uF
0.22uF
*
*
*
*
10V, X7R, +/-10%
10V, X7R, +/-10%
10V, X7R, +/-10%
10V, X7R, +/-10%
C496
C496
10uF
10uF
+/-10%
+/-10%
C513
C513
10nF
10nF
Decoupling Between Processor and DIMMs
2
C500
C500
C489
C489
C487
C487
10uF
10uF
*
*
+/-10%
+/-10%
C512
C512
180pF
180pF
*
*
50V, NPO, +/-5%
50V, NPO, +/-5%
GND
25V, Y5V, +80%/-20%
25V, Y5V, +80%/-20%
+1.8V_SUS
C347
C347
180pF
180pF
*
*
+/-5%
+/-5%
Title
Title
Title
M2- 4 Power
M2- 4 Power
M2- 4 Power
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
10uF
10uF
10uF
10uF
*
*
*
*
+/-10%
+/-10%
+/-10%
+/-10%
Dummy
Dummy
C317
C317
180pF
180pF
*
*
+/-5%
+/-5%
GND
C501
C501
C488
C488
22uF
22uF
22uF
22uF
*
*
*
*
6.3V, X5R, +/-10%
6.3V, X5R, +/-10%
Dummy
Dummy
Dummy
Dummy
FOXCONN PCEG
FOXCONN PCEG
FOXCONN PCEG
MCP61M05
MCP61M05
MCP61M05
1
6.3V, X5R, +/-10%
6.3V, X5R, +/-10%
*
*
Dummy
Dummy
C495
C495
10uF
10uF
+/-10%
+/-10%
*
*
GND
Dummy
Dummy
10 35Friday, June 27, 2008
10 35Friday, June 27, 2008
10 35Friday, June 27, 2008
C503
C503
10uF
10uF
+/-10%
+/-10%
of
of
of
AC
AC
AC
5
4
3
SMB_MEM BUS ADDRESS
DIMM 0
DIMM 1
DIMM 2
DIMM 3
1010 000
1010 001
1010 010
1010 011
2
1
DIMMA0
D D
MEM_MA_DM[7..0]7
MEM_MA_DQS_H87
MEM_MA_DQS_L87
MEM_MA_DQS_H[7..0]7
MEM_MA_DQS_L[7..0]7
C C
MEM_MA_ADD[15..0]7,12
B B
MEM_MA_CHECK[7..0]7
MEM_MA_DM87
GND
SMB_MEM_SDA18
MEM_MA_BANK27,12
MEM_MA_BANK17,12
MEM_MA_BANK07,12
MEM_MA0_CLK_H07,12
MEM_MA0_CLK_L07,12
MEM_MA0_CLK_H17,12
MEM_MA0_CLK_L17,12
MEM_MA0_CLK_H27,12
MEM_MA0_CLK_L27,12
MEM_MA_CKE07,12
MEM_MA_RAS_L7,12
MEM_MA_CAS_L7,12
MEM_MA0_CS_L07,12
MEM_MA0_CS_L17,12
MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_CHECK6
MEM_MA_CHECK5
MEM_MA_CHECK4
MEM_MA_CHECK3
MEM_MA_CHECK2
MEM_MA_CHECK1
MEM_MA_CHECK0
MEM_MA_CKE0
+1.8V_SUS
172
178
184
187
189
197
64
69
170
175
181
191
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD753VDD859VDD9
VDD1067VDD11
VDDQ1
VDDQ2
164
DQS17_H
165
DQS17_L
232
DQS16_H
233
DQS16_L
223
DQS15_H
224
DQS15_L
211
DQS14_H
212
DQS14_L
202
DQS13_H
203
DQS13_L
155
DQS12_H
156
DQS12_L
146
DQS11_H
147
DQS11_L
134
DQS10_H
135
DQS10_L
125
DQS9_H
126
DQS9_L
46
DQS8_H
45
DQS8_L
114
DQS7_H
113
DQS7_L
105
DQS6_H
104
DQS6_L
93
DQS5_H
92
DQS5_L
84
DQS4_H
83
DQS4_L
37
DQS3_H
36
DQS3_L
28
DQS2_H
27
DQS2_L
16
DQS1_H
15
DQS1_L
7
DQS0_H
6
DQS0_L
101
SA2
240
SA1
239
SA0
120
SCL
119
SDA
54
BA2
190
BA1
71
BA0
173
A15
174
A14
196
A13
176
A12
57
A11
70
A10
177
A9
179
A8
58
A7
180
A6
60
A5
61
A4
182
A3
63
A2
183
A1
188
A0
168
CB7
167
CB6
162
CB5
161
CB4
49
CB3
48
CB2
43
CB1
42
CB0
185
CK0_H
186
CK0_L
137
CK1_H
138
CK1_L
220
CK2_H
221
CK2_L
18
RESET_L
52
CKE0
171
CKE1
192
RAS_L
74
CAS_L
193
S0_L
76
S1_L
VDDQ3
VDDQ4
194
VDDQ5
72
VDDQ651VDDQ756VDDQ862VDDQ9
+3.3V
78
VDDQ1075VDDQ11
ERR_OUT_L
VDDQ4
194
VDDQ5
72
VDDQ651VDDQ756VDDQ862VDDQ9
+3.3V
78
VDDQ1075VDDQ11
ERR_OUT_L
R254
R254
*
*
0
0
+/-5%
+/-5%
DIMM2DIMM2
238
VDDSPD
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
WE_L
VREF
TEST
ODT0
ODT1
PAR_IN
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
NC1
MEM_MB_DATA63
236
MEM_MB_DATA62
235
MEM_MB_DATA61
230
MEM_MB_DATA60
229
MEM_MB_DATA59
117
MEM_MB_DATA58
116
MEM_MB_DATA57
111
MEM_MB_DATA56
110
MEM_MB_DATA55
227
MEM_MB_DATA54
226
MEM_MB_DATA53
218
MEM_MB_DATA52
217
MEM_MB_DATA51
108
MEM_MB_DATA50
107
MEM_MB_DATA49
99
MEM_MB_DATA48
98
MEM_MB_DATA47
215
MEM_MB_DATA46
214
MEM_MB_DATA45
209
MEM_MB_DATA44
208
MEM_MB_DATA43
96
MEM_MB_DATA42
95
MEM_MB_DATA41
90
MEM_MB_DATA40
89
MEM_MB_DATA39
206
MEM_MB_DATA38
205
MEM_MB_DATA37
200
MEM_MB_DATA36
199
MEM_MB_DATA35
87
MEM_MB_DATA34
86
MEM_MB_DATA33
81
MEM_MB_DATA32
80
MEM_MB_DATA31
159
MEM_MB_DATA30
158
MEM_MB_DATA29
153
MEM_MB_DATA28
152
MEM_MB_DATA27
40
MEM_MB_DATA26
39
MEM_MB_DATA25
34
MEM_MB_DATA24
33
MEM_MB_DATA23
150
MEM_MB_DATA22
149
MEM_MB_DATA21
144
MEM_MB_DATA20
143
MEM_MB_DATA19
31
MEM_MB_DATA18
30
MEM_MB_DATA17
25
MEM_MB_DATA16
24
MEM_MB_DATA15
141
MEM_MB_DATA14
140
MEM_MB_DATA13
132
MEM_MB_DATA12
131
MEM_MB_DATA11
22
MEM_MB_DATA10
21
MEM_MB_DATA9
13
MEM_MB_DATA8
12
MEM_MB_DATA7
129
MEM_MB_DATA6
128
MEM_MB_DATA5
123
MEM_MB_DATA4
122
MEM_MB_DATA3
10
MEM_MB_DATA2
9
MEM_MB_DATA1
4
MEM_MB_DATA0MEM_MB_CHECK7
3
73
MEM_MB_WE_L 8,12
1
102
195
77
55
68
19
MEM_MB_DATA[63..0] 8
MEM_M_VREF_SUS
MEM_MB0_ODT0 8,12
GND
First Logical DDR2 DIMM
R253
R253
*
*
0
0
+/-5%
+/-5%
DIMM1DIMM1
238
VDDSPD
MEM_MA_DATA63
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
WE_L
VREF
TEST
ODT0
ODT1
PAR_IN
236
MEM_MA_DATA62
235
MEM_MA_DATA61
230
MEM_MA_DATA60
229
MEM_MA_DATA59
117
MEM_MA_DATA58
116
MEM_MA_DATA57
111
MEM_MA_DATA56
110
MEM_MA_DATA55
227
MEM_MA_DATA54
226
MEM_MA_DATA53
218
MEM_MA_DATA52
217
MEM_MA_DATA51
108
MEM_MA_DATA50
107
MEM_MA_DATA49
99
MEM_MA_DATA48
98
MEM_MA_DATA47
215
MEM_MA_DATA46
214
MEM_MA_DATA45
209
MEM_MA_DATA44
208
MEM_MA_DATA43
96
MEM_MA_DATA42
95
MEM_MA_DATA41
90
MEM_MA_DATA40
89
MEM_MA_DATA39
206
MEM_MA_DATA38
205
MEM_MA_DATA37
200
MEM_MA_DATA36
199
MEM_MA_DATA35
87
MEM_MA_DATA34
86
MEM_MA_DATA33
81
MEM_MA_DATA32
80
MEM_MA_DATA31
159
MEM_MA_DATA30
158
MEM_MA_DATA29
153
MEM_MA_DATA28
152
MEM_MA_DATA27
40
MEM_MA_DATA26
39
MEM_MA_DATA25
34
MEM_MA_DATA24
33
MEM_MA_DATA23
150
MEM_MA_DATA22
149
MEM_MA_DATA21
144
MEM_MA_DATA20
143
MEM_MA_DATA19
31
MEM_MA_DATA18
30
MEM_MA_DATA17
25
MEM_MA_DATA16
24
MEM_MA_DATA15
141
MEM_MA_DATA14
140
MEM_MA_DATA13
132
MEM_MA_DATA12
131
MEM_MA_DATA11
22
MEM_MA_DATA10
21
MEM_MA_DATA9
13
DQ9
MEM_MA_DATA8
12
DQ8
MEM_MA_DATA7
129
DQ7
MEM_MA_DATA6
128
DQ6
MEM_MA_DATA5
123
DQ5
MEM_MA_DATA4
122
DQ4
MEM_MA_DATA3
10
DQ3
MEM_MA_DATA2
9
DQ2
MEM_MA_DATA1
4
DQ1
MEM_MA_DATA0MEM_MA_CHECK7
3
DQ0
73
MEM_MA_WE_L 7,12
1
102
195
77
55
68
19
NC1
MEM_MA0_ODT0 7,12
GND
MEM_MA_DATA[63..0] 7
MEM_M_VREF_SUS
MEM_M_VREF_SUS
MEM_MB_DM[7..0]8
MEM_MB_DQS_H88
MEM_MB_DQS_L88
MEM_MB_DQS_H[7..0]8
MEM_MB_DQS_L[7..0]8
MEM_MB_DM88
+3.3V
SMB_MEM_SCL18SMB_MEM_SCL18
SMB_MEM_SDA18
GND
MEM_MB_BANK28,12
MEM_MB_BANK18,12
MEM_MB_ADD[15..0]8,12
MEM_MB_BANK08,12
MEM_MB_CHECK[7..0]8
MEM_MB0_CLK_H08,12
MEM_MB0_CLK_L08,12
MEM_MB0_CLK_H18,12
MEM_MB0_CLK_L18,12
MEM_MB0_CLK_H28,12
MEM_MB0_CLK_L28,12
MEM_MB_CKE08,12
MEM_MB_RAS_L8,12
MEM_MB_CAS_L8,12
MEM_MB0_CS_L08,12
MEM_MB0_CS_L18,12
MEM_MB_DM7
MEM_MB_DM6
MEM_MB_DM5
MEM_MB_DM4
MEM_MB_DM3
MEM_MB_DM2
MEM_MB_DM1
MEM_MB_DM0
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_CHECK6
MEM_MB_CHECK5
MEM_MB_CHECK4
MEM_MB_CHECK3
MEM_MB_CHECK2
MEM_MB_CHECK1
MEM_MB_CHECK0
164
DQS17_H
165
DQS17_L
232
DQS16_H
233
DQS16_L
223
DQS15_H
224
DQS15_L
211
DQS14_H
212
DQS14_L
202
DQS13_H
203
DQS13_L
155
DQS12_H
156
DQS12_L
146
DQS11_H
147
DQS11_L
134
DQS10_H
135
DQS10_L
125
DQS9_H
126
DQS9_L
46
DQS8_H
45
DQS8_L
114
DQS7_H
113
DQS7_L
105
DQS6_H
104
DQS6_L
93
DQS5_H
92
DQS5_L
84
DQS4_H
83
DQS4_L
37
DQS3_H
36
DQS3_L
28
DQS2_H
27
DQS2_L
16
DQS1_H
15
DQS1_L
7
DQS0_H
6
DQS0_L
101
SA2
240
SA1
239
SA0
120
SCL
119
SDA
54
BA2
190
BA1
71
BA0
173
A15
174
A14
196
A13
176
A12
57
A11
70
A10
177
A9
179
A8
58
A7
180
A6
60
A5
61
A4
182
A3
63
A2
183
A1
188
A0
168
CB7
167
CB6
162
CB5
161
CB4
49
CB3
48
CB2
43
CB1
42
CB0
185
CK0_H
186
CK0_L
137
CK1_H
138
CK1_L
220
CK2_H
221
CK2_L
18
RESET_L
52
CKE0
171
CKE1
192
RAS_L
74
CAS_L
193
S0_L
76
S1_L
DIMMB0
+1.8V_SUS
172
178
184
187
189
197
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
64
VDD753VDD859VDD9
69
VDD1067VDD11
170
VDDQ1
175
181
191
VDDQ2
VDDQ3
+1.8V_SUS
R222
R222
C356
C356
*
*
59 Ohm
59 Ohm
*
*
+/-1%
*
*
+/-1%
R220
R220
59 Ohm
59 Ohm
+/-1%
+/-1%
*
*
A A
Layout: Place near DIMM sockets
5
4
3
100nF
100nF
100nF
100nF
C335
C335
MEM_M_VREF_SUS
C337
C337
1nF
1nF
*
*
GND
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
DDR SDRAM DIMM 1 - 2
DDR SDRAM DIMM 1 - 2
DDR SDRAM DIMM 1 - 2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
FOXCONN PCEG
MCP61M05
MCP61M05
MCP61M05
1
11 35Friday, June 27, 2008
11 35Friday, June 27, 2008
11 35Friday, June 27, 2008
AC
AC
AC
of
of
of
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