Foxconn CK804A07 Schematics

5

4

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CK804A07

D D

nVIDIA CK804 Chipset forAM2 CPU

10/25/2006)

PAGE PAGECONTENT CONTENT

1 2 3 4

C C

5 6 7 8

9 10 11 12 13 14

B B

15 16 17 18 19 20 21

Index Topology RESET MAP CLOCK DISTRIBUTION Power Delivery M2-1 Hyper Transport M2-2 DDR-1 M2-2 DDR-2 M2-4 MISC M2-5 Power

DDRII SDRAM DIMM1-2

DDRII SDRAM DIMM3-4 DDRTerminator

CK804 HT

CK804 PCI EXPRESS CK804 PCI CK804 SATA / IDE CK804 G/MII / AC97 / USB CK804 DECOUPLING PCI EXPRESS X16 CONNECTOR PCI EXPRESS X1 CONNECTORS

22 23 24

25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

42

PCI CONNECTOR 1-2 PCI CONNECTOR 3-4

PCI TERMINATION

VT6307/6308 LAN RTL8211BL FWH & SPI USB CONNECTORS IDE CONNECTORS AUDIO 653/850 AUDIO CONNECTORS 653/850

SIO ITE8716

FDD / PS2 FAN / HARDWARE MONITOR

PRT COM PORT

PWM ST L6711 AM2 DDR POWER CK804 CORE Power sequence PWR CON / FNT PNL / VBAT VID CONTROLLER CHANGELIST

42

A A

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Index

CK804A07

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A

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1

D D

POWER

SUPPLY

CONNECTOR

PEX X1

PEX X16

PEX X1 (2)

C C

PRIMARY IDE

SECONDARY IDE

X4 - SATA CONN

FLOPPY CONN

PS2/KBRD CONN

PARALLEL CONN

SERIAL CONN

B B

SIO

ITE IT8712F

VREG

PCI EXPRESS/NEW CARD

PCI EXPRESS

ATA 133

INTEGRATED SATA

LPC BUS 33MHZ

4MB FLASH

BLOCK DIAGRAM

SOCKET 940

AM2

HT 16X16 1GHZ

NFORCE

CRUSH K804

RGMII

PCI 33MHZ

AC97

X10 USB2

MII/RGMII

AC97

BACK PANEL CONN

USB2 PORTS 4-5

QUAD STACK

USB2 PORTS 8-9

FRONT PANEL HDR

USB2 PORTS 1-0

USB2 PORTS 7-6

DDR SDRAM CONN A1

DDR SDRAM CONN B1

DDR SDRAM CONN A2

DDR SDRAM CONNB2

PCI SLOT 1

PCI SLOT 2

PCI SLOT 3

PCI SLOT 4

X2/GBIT LAN

A A

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Index

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RESET MAP

D D

AM2

CPU RST*

CPU PWRGD

C C

CPU_RST*

CPU_PWRGD

PWR SWTCH

CK804

PWR CONN

PS ON

PWR GOOD

PWRGD SB

B B

CIRCUIT

SLP_S3*

POWER_GOOD

PEX X16

PWRBTN*

PWRGD_SB

PWR BUTTON

SLP S3*

PWRGD

PWRGD_SB

PE_RESET*

CPU PWRGD CPU RST*

PCI RST0* PCI RST1* PCI RST2* PCI RST3*

LPC_RST*

GPIO_AUX*

CPU_PWRGD CPU_RST*

PCIRST_SLOT1* PCIRST_SLOT2* PCIRST_SLOT3-4*

PCIRST_IDE* LPCRST_FLASH* LPCRST_SIO*

SIO

FLASH

PRI IDE

PCI SLOT 3

PCI SLOT 4SEC IDE

PCI SLOT 2

PCI SLOT 1394

1394

PEX X1(2)

PEX X1NC

A A

5

4

LAN_PHY

RESET*

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Reset Map

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K8 AM2 CPU

L0_CLKIN_H(1)

L0_CLKIN_L(1)

D D

L0_CLKIN_H(0)

L0_CLKIN_L(0) L0_CLKOUT_H(1)

L0_CLKOUT_L(1) L0_CLKOUT_H(0)

L0_CLKOUT_L(0)

CPU_CLK_IN* CPU_CLK_IN

MEMORY_A0_CLK[2:0] MEMORY_A0_CLK[2:0]*

MEMORY_B0_CLK[2:0] MEMORY_B0_CLK[2:0]*

MEMORY_A1_CLK[2:0] MEMORY_A1_CLK[2:0]*

MEMORY_B1_CLK[2:0] MEMORY_B1_CLK[2:0]*

CHANNEL A1 0-63

CHANNEL B1 0-63

CHANNEL A2 0-63

CHANNEL B2 0-63

DIMM A1

DIMM B1

DIMM A2

DIMM B2

CK804

CPU_CLK_IN CPU_CLK_IN*

HT_RXCLK0* HT_RXCLK0

HT_RXCLK1* HT_RXCLK1

C C

32.0 KHZ

25 MHZ

B B

HT_TXCLK1*

HT_TXCLK1

HT_TXCLK0*

HT_TXCLK0 XTAL_IN

XTAL_OUT

XTAL_IN

XTAL_OUT

PE0_REFCLK PE0_REFCLK*

PE1_REFCLK PE1_REFCLK*

PE2_REFCLK PE2_REFCLK*

PE3_REFCLK PE3_REFCLK*

BUF_SIO

LPC_CLK0

PCI_CLK0 PCI_CLK1 PCI_CLK2 PCI_CLK3 PCI_CLK4 PCI_CLK5

PCI_CLK_FB

AC_97CLK

AC_BITCLK

BUF_25MHZ

SUSCLK

LPC_CLK1

14MHZ OR 24MHZ

AC '97 LINK

SIO

AC97 CODEC

PEX X16

PEX X1

PCI SLOT 2

PCI SLOT 1

PCI SLOT 3

PCI SLOT 4

PCI_CLKLPC

1394

A A

TECHNOLOGY COPR.

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Clock Distribution

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Clock Distribution

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A

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2

1

D D

+5V

AOD4600

+5V_DUAL

POWER CONN

+5V_STBY

12V_SYS 5V_SYS 3.3V_SYS 5V_STBY -12V_SYS

3D3V__DUAL

C C

3D3V_SYS/5V_SYS

3D3V_SYS

AP15N03H

AME8800 +2.5V

RT9166A-15PXL +1.5V_SP_PLLPWR

AZ1084D-ADJTRE1

5V_DUAL

VTT_DDR

1D2V_HT

RT9214PS 1D8V_STR

RT9173

AP15N03H

MEM-POWER

B B

12V_SYS

12V_VRM

A A

5

LM78L05 5V_AUDIO

L6711TR +V_CPU

4

CPU-POWER

3

3.3V_DUAL

5V_SYS

RT9166A-15PXL

RT9214PS

2

+1.5V_DUAL

1D5V_CORE

TECHNOLOGY COPR.

Title

Document Number Rev

Date: Sheet

Reset Map

CK804A07

TECHNOLOGY COPR.

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A

5

HT_UPCLK114

D D

HT_UP[15..0]14

HT_UP*[15..0]14

C C

HT_UP[15..0]

HT_UP*[15..0]

1D2V_HT

GND

R100 49.9 r0603h6 +/-1%R100 49.9 r0603h6 +/-1% R101 49.9 r0603h6 +/-1%R101 49.9 r0603h6 +/-1%

HT_UPCLK1*14 HT_UPCLK014 HT_UPCLK0*14

HT_UPCNTL14 HT_UPCNTL*14

HT_UP*15

HT_UP*14

HT_UP*13

HT_UP*12

HT_UP*11

HT_UP*10

HT_UP*9

HT_UP*8

HT_UP*7

HT_UP*6

HT_UP*5

HT_UP*4

HT_UP*3

HT_UP*2

HT_UP*1

HT_UP*0

4

HT_UPCLK1 HT_UPCLK1* HT_UPCLK0 HT_UPCLK0*

HT_CPU_CTLIN_H1 HT_CPU_CTLIN_L1

HT_UPCNTL HT_UPCNTL*

HT_UP15

HT_UP14

HT_UP13

HT_UP12

HT_UP11

HT_UP10

HT_UP9

HT_UP8

HT_UP7

HT_UP6

HT_UP5

HT_UP4

HT_UP3

HT_UP2

HT_UP1

HT_UP0

N6

L0_CLKIN_H(1)

P6

L0_CLKIN_L(1)

N3

L0_CLKIN_H(0)

N2

L0_CLKIN_L(0)

V4

L0_CTLIN_H(1)

V5

L0_CTLIN_L(1)

U1

L0_CTLIN_H(0)

V1

L0_CTLIN_L(0)

U6

L0_CADIN_H(15)

V6

L0_CADIN_L(15)

T4

L0_CADIN_H(14)

T5

L0_CADIN_L(14)

R6

L0_CADIN_H(13)

T6

L0_CADIN_L(13)

P4

L0_CADIN_H(12)

P5

L0_CADIN_L(12)

M4

L0_CADIN_H(11)

M5

L0_CADIN_L(11)

L6

L0_CADIN_H(10)

M6

L0_CADIN_L(10)

K4

L0_CADIN_H(9)

K5

L0_CADIN_L(9)

J6

L0_CADIN_H(8)

K6

L0_CADIN_L(8)

U3

L0_CADIN_H(7)

U2

L0_CADIN_L(7)

R1

L0_CADIN_H(6)

T1

L0_CADIN_L(6)

R3

L0_CADIN_H(5)

R2

L0_CADIN_L(5)

N1

L0_CADIN_H(4)

P1

L0_CADIN_L(4)

L1

L0_CADIN_H(3)

M1

L0_CADIN_L(3)

L3

L0_CADIN_H(2)

L2

L0_CADIN_L(2)

J1

L0_CADIN_H(1)

K1

L0_CADIN_L(1)

J3

L0_CADIN_H(0)

J2

L0_CADIN_L(0)

U1A

HYPERTRANSPORT

L0_CLKOUT_H(1)

L0_CLKOUT_L(1)

L0_CLKOUT_H(0)

L0_CLKOUT_L(0)

L0_CTLOUT_H(1)

L0_CTLOUT_L(1)

L0_CTLOUT_H(0)

L0_CTLOUT_L(0)

L0_CADOUT_H(15) L0_CADOUT_L(15) L0_CADOUT_H(14) L0_CADOUT_L(14) L0_CADOUT_H(13) L0_CADOUT_L(13) L0_CADOUT_H(12) L0_CADOUT_L(12) L0_CADOUT_H(11) L0_CADOUT_L(11) L0_CADOUT_H(10) L0_CADOUT_L(10)

L0_CADOUT_H(9)

L0_CADOUT_L(9)

L0_CADOUT_H(8)

L0_CADOUT_L(8)

L0_CADOUT_H(7)

L0_CADOUT_L(7)

L0_CADOUT_H(6)

L0_CADOUT_L(6)

L0_CADOUT_H(5)

L0_CADOUT_L(5)

L0_CADOUT_H(4)

L0_CADOUT_L(4)

L0_CADOUT_H(3)

L0_CADOUT_L(3)

L0_CADOUT_H(2)

L0_CADOUT_L(2)

L0_CADOUT_H(1)

L0_CADOUT_L(1)

L0_CADOUT_H(0)

L0_CADOUT_L(0)

3

AD5 AD4 AD1 AC1

HT_CPU_CTLOUT_H1

Y6

HT_CPU_CTLOUT_L1

W6 W2 W3

Y5 Y4 AB6 AA6 AB5 AB4 AD6 AC6 AF6 AE6 AF5 AF4 AH6 AG6 AH5 AH4

Y1 W1 AA2 AA3 AB1 AA1 AC2 AC3 AE2 AE3 AF1 AE1 AG2 AG3 AH1 AG1

HT_DWN15

HT_DWN14

HT_DWN13

HT_DWN12

HT_DWN11

HT_DWN10

HT_DWN9

HT_DWN8

HT_DWN7

HT_DWN6

HT_DWN5

HT_DWN4

HT_DWN3

HT_DWN2

HT_DWN1

HT_DWN0

HT_DWNCLK1 HT_DWNCLK1* HT_DWNCLK0 HT_DWNCLK0*

1 1

HT_DWNCNTL HT_DWNCNTL*

HT_DWN*15

HT_DWN*14

HT_DWN*13

HT_DWN*12

HT_DWN*11

HT_DWN*10

HT_DWN*9

HT_DWN*8

HT_DWN*7

HT_DWN*6

HT_DWN*5

HT_DWN*4

HT_DWN*3

HT_DWN*2

HT_DWN*1

HT_DWN*0

TP1TP1 TP2TP2

2

HT_DWNCLK1 14 HT_DWNCLK1* 14 HT_DWNCLK0 14 HT_DWNCLK0* 14

HT_DWNCNTL 14 HT_DWNCNTL* 14

HT_DWN[15..0]

HT_DWN*[15..0]

1

HT_DWN[15..0] 14

HT_DWN*[15..0] 14

A1

B B

M2

Top View

A31

Layout: Add stitching caps if crossing plane split

HyperTransport Net Naming Convention

HT_"link driver"_"link receiver"_"function"_"polarity"_"number"

AL1

A A

TECHNOLOGY COPR.

Title

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M2-1 Hyper Transport

CK804A07

TECHNOLOGY COPR.

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641Tuesday, October 31, 2006

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641Tuesday, October 31, 2006

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641Tuesday, October 31, 2006

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A

5

D D

MEM_MA0_CLK_H211,13 MEM_MA0_CLK_L211,13 MEM_MA0_CLK_H111,13 MEM_MA0_CLK_L111,13 MEM_MA0_CLK_H011,13 MEM_MA0_CLK_L011,13

MEM_MA0_CS_L111,13 MEM_MA0_CS_L011,13

MEM_MA0_ODT011,13 MEM_MA1_CLK_H212,13

MEM_MA1_CLK_L212,13 MEM_MA1_CLK_H112,13 MEM_MA1_CLK_L112,13 MEM_MA1_CLK_H012,13 MEM_MA1_CLK_L012,13

MEM_MA1_CS_L112,13 MEM_MA1_CS_L012,13

MEM_MA1_ODT012,13

MEM_MA_CAS_L11,12,13 MEM_MA_WE_L11,12,13

C C

MEM_MA_RAS_L11,12,13 MEM_MA_BANK211,12,13

MEM_MA_BANK111,12,13 MEM_MA_BANK011,12,13

MEM_MA_CKE112,13 MEM_MA_CKE011,13

MEM_MA_ADD[15..0]11,12,13

MEM_MA_DQS_H[7..0]11,12

B B

MEM_MA_DQS_L[7..0]11,12

MEM_MA_DM[7..0]11,12

4

MEM_MA_ADD15 MEM_MA_ADD14 MEM_MA_ADD13 MEM_MA_ADD12 MEM_MA_ADD11 MEM_MA_ADD10 MEM_MA_ADD9 MEM_MA_ADD8 MEM_MA_ADD7 MEM_MA_ADD6 MEM_MA_ADD5 MEM_MA_ADD4 MEM_MA_ADD3 MEM_MA_ADD2 MEM_MA_ADD1 MEM_MA_ADD0

MEM_MA_DQS_H7 MEM_MA_DQS_L7 MEM_MA_DQS_H6 MEM_MA_DQS_L6 MEM_MA_DQS_H5 MEM_MA_DQS_L5 MEM_MA_DQS_H4 MEM_MA_DQS_L4 MEM_MA_DQS_H3 MEM_MA_DQS_L3 MEM_MA_DQS_H2 MEM_MA_DQS_L2 MEM_MA_DQS_H1 MEM_MA_DQS_L1 MEM_MA_DQS_H0 MEM_MA_DQS_L0

MEM_MA_DM7 MEM_MA_DM6 MEM_MA_DM5 MEM_MA_DM4 MEM_MA_DM3 MEM_MA_DM2 MEM_MA_DM1 MEM_MA_DM0

AG21 AG20

G19

H19 U27 U26

AC25 AA24

AC28 AE20

AE19

G20 G21

V27

W27

AD27 AA25

AC27

AB25 AB27 AA26

N25 Y27

AA27

M25 M27

N24

AC26

N26 P25 Y25 N27 R24 P27 R25 R26 R27 T25 U25 T27

W24

AD15 AE15 AG18 AG19 AG24 AG25 AG27 AG28

D29 C29 C25 D25 E19 F19 F15

G15

AF15 AF19 AJ25

AH29

B29 E24 E18 H15

L27

MEMORY INTERFACE A

MA0_CLK_H(2) MA0_CLK_L(2) MA0_CLK_H(1) MA0_CLK_L(1) MA0_CLK_H(0) MA0_CLK_L(0)

MA0_CS_L(1) MA0_CS_L(0)

MA0_ODT(0) MA1_CLK_H(2)

MA1_CLK_L(2) MA1_CLK_H(1) MA1_CLK_L(1) MA1_CLK_H(0) MA1_CLK_L(0)

MA1_CS_L(1) MA1_CS_L(0)

MA1_ODT(0)

MA_CAS_L MA_WE_L MA_RAS_L

MA_BANK(2) MA_BANK(1) MA_BANK(0)

MA_CKE(1) MA_CKE(0)

MA_ADD(15) MA_ADD(14) MA_ADD(13) MA_ADD(12) MA_ADD(11) MA_ADD(10) MA_ADD(9) MA_ADD(8) MA_ADD(7) MA_ADD(6) MA_ADD(5) MA_ADD(4) MA_ADD(3) MA_ADD(2) MA_ADD(1) MA_ADD(0)

MA_DQS_H(7) MA_DQS_L(7) MA_DQS_H(6) MA_DQS_L(6) MA_DQS_H(5) MA_DQS_L(5) MA_DQS_H(4) MA_DQS_L(4) MA_DQS_H(3) MA_DQS_L(3) MA_DQS_H(2) MA_DQS_L(2) MA_DQS_H(1) MA_DQS_L(1) MA_DQS_H(0) MA_DQS_L(0)

MA_DM(7) MA_DM(6) MA_DM(5) MA_DM(4) MA_DM(3) MA_DM(2) MA_DM(1) MA_DM(0)

U1B

MA_DATA(63) MA_DATA(62) MA_DATA(61) MA_DATA(60) MA_DATA(59) MA_DATA(58) MA_DATA(57) MA_DATA(56) MA_DATA(55) MA_DATA(54) MA_DATA(53) MA_DATA(52) MA_DATA(51) MA_DATA(50) MA_DATA(49) MA_DATA(48) MA_DATA(47) MA_DATA(46) MA_DATA(45) MA_DATA(44) MA_DATA(43) MA_DATA(42) MA_DATA(41) MA_DATA(40) MA_DATA(39) MA_DATA(38) MA_DATA(37) MA_DATA(36) MA_DATA(35) MA_DATA(34) MA_DATA(33) MA_DATA(32) MA_DATA(31) MA_DATA(30) MA_DATA(29) MA_DATA(28) MA_DATA(27) MA_DATA(26) MA_DATA(25) MA_DATA(24) MA_DATA(23) MA_DATA(22) MA_DATA(21) MA_DATA(20) MA_DATA(19) MA_DATA(18) MA_DATA(17) MA_DATA(16) MA_DATA(15) MA_DATA(14) MA_DATA(13) MA_DATA(12) MA_DATA(11) MA_DATA(10)

MA_DATA(9) MA_DATA(8) MA_DATA(7) MA_DATA(6) MA_DATA(5) MA_DATA(4) MA_DATA(3) MA_DATA(2) MA_DATA(1) MA_DATA(0)

MA_DQS_H(8)

MA_DQS_L(8)

MA_DM(8)

MA_CHECK(7) MA_CHECK(6) MA_CHECK(5) MA_CHECK(4) MA_CHECK(3) MA_CHECK(2) MA_CHECK(1) MA_CHECK(0)

AE14 AG14 AG16 AD17 AD13 AE13 AG15 AE16 AG17 AE18 AD21 AG22 AE17 AF17 AF21 AE21 AF23 AE23 AJ26 AG26 AE22 AG23 AH25 AF25 AJ28 AJ29 AF29 AE26 AJ27 AH27 AG29 AF27 E29 E28 D27 C27 G26 F27 C28 E27 F25 E25 E23 D23 E26 C26 G23 F23 E22 E21 F17 G17 G22 F21 G18 E17 G16 E15 G13 H13 H17 E16 E14 G14

J28 J27

J25 K25

J26 G28 G27 L24 K27 H29 H27

3

MEM_MA_DATA63 MEM_MA_DATA62 MEM_MA_DATA61 MEM_MA_DATA60 MEM_MA_DATA59 MEM_MA_DATA58 MEM_MA_DATA57 MEM_MA_DATA56 MEM_MA_DATA55 MEM_MA_DATA54 MEM_MA_DATA53 MEM_MA_DATA52 MEM_MA_DATA51 MEM_MA_DATA50 MEM_MA_DATA49 MEM_MA_DATA48 MEM_MA_DATA47 MEM_MA_DATA46 MEM_MA_DATA45 MEM_MA_DATA44 MEM_MA_DATA43 MEM_MA_DATA42 MEM_MA_DATA41 MEM_MA_DATA40 MEM_MA_DATA39 MEM_MA_DATA38 MEM_MA_DATA37 MEM_MA_DATA36 MEM_MA_DATA35 MEM_MA_DATA34 MEM_MA_DATA33 MEM_MA_DATA32 MEM_MA_DATA31 MEM_MA_DATA30 MEM_MA_DATA29 MEM_MA_DATA28 MEM_MA_DATA27 MEM_MA_DATA26 MEM_MA_DATA25 MEM_MA_DATA24 MEM_MA_DATA23 MEM_MA_DATA22 MEM_MA_DATA21 MEM_MA_DATA20 MEM_MA_DATA19 MEM_MA_DATA18 MEM_MA_DATA17 MEM_MA_DATA16 MEM_MA_DATA15 MEM_MA_DATA14 MEM_MA_DATA13 MEM_MA_DATA12 MEM_MA_DATA11 MEM_MA_DATA10 MEM_MA_DATA9 MEM_MA_DATA8 MEM_MA_DATA7 MEM_MA_DATA6 MEM_MA_DATA5 MEM_MA_DATA4 MEM_MA_DATA3 MEM_MA_DATA2 MEM_MA_DATA1 MEM_MA_DATA0

MEM_MA_CHECK7 MEM_MA_CHECK6 MEM_MA_CHECK5 MEM_MA_CHECK4 MEM_MA_CHECK3 MEM_MA_CHECK2 MEM_MA_CHECK1 MEM_MA_CHECK0

MEM_MA_DATA[63..0] 11,12

MEM_MA_DQS_H8 11,12 MEM_MA_DQS_L8 11,12

MEM_MA_DM8 11,12

MEM_MA_CHECK[7..0] 11,12

2

1

A A

TECHNOLOGY COPR.

Title

Document Number Rev

Date: Sheet

5

4

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2

Date: Sheet

M2-2 DDR-1

CK804A07

TECHNOLOGY COPR.

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741Tuesday, October 31, 2006

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741Tuesday, October 31, 2006

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741Tuesday, October 31, 2006

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A

5

D D

MEM_MB0_CLK_H211,13 MEM_MB0_CLK_L211,13 MEM_MB0_CLK_H111,13 MEM_MB0_CLK_L111,13 MEM_MB0_CLK_H011,13 MEM_MB0_CLK_L011,13

MEM_MB0_CS_L111,13 MEM_MB0_CS_L011,13

MEM_MB0_ODT011,13 MEM_MB1_CLK_H212,13

MEM_MB1_CLK_L212,13 MEM_MB1_CLK_H112,13 MEM_MB1_CLK_L112,13 MEM_MB1_CLK_H012,13 MEM_MB1_CLK_L012,13

MEM_MB1_CS_L112,13 MEM_MB1_CS_L012,13

MEM_MB1_ODT012,13

MEM_MB_CAS_L11,12,13 MEM_MB_WE_L11,12,13

C C

MEM_MB_RAS_L11,12,13 MEM_MB_BANK211,12,13

MEM_MB_BANK111,12,13 MEM_MB_BANK011,12,13

MEM_MB_CKE112,13 MEM_MB_CKE011,13

MEM_MB_ADD[15..0]11,12,13

MEM_MB_DQS_H[7..0]11,12

B B

MEM_MB_DQS_L[7..0]11,12

MEM_MB_DM[7..0]11,12

4

MEM_MB_ADD15 MEM_MB_ADD14 MEM_MB_ADD13 MEM_MB_ADD12 MEM_MB_ADD11 MEM_MB_ADD10 MEM_MB_ADD9 MEM_MB_ADD8 MEM_MB_ADD7 MEM_MB_ADD6 MEM_MB_ADD5 MEM_MB_ADD4 MEM_MB_ADD3 MEM_MB_ADD2 MEM_MB_ADD1 MEM_MB_ADD0

MEM_MB_DQS_H7 MEM_MB_DQS_L7 MEM_MB_DQS_H6 MEM_MB_DQS_L6 MEM_MB_DQS_H5 MEM_MB_DQS_L5 MEM_MB_DQS_H4 MEM_MB_DQS_L4 MEM_MB_DQS_H3 MEM_MB_DQS_L3 MEM_MB_DQS_H2 MEM_MB_DQS_L2 MEM_MB_DQS_H1 MEM_MB_DQS_L1 MEM_MB_DQS_H0 MEM_MB_DQS_L0

MEM_MB_DM7 MEM_MB_DM6 MEM_MB_DM5 MEM_MB_DM4 MEM_MB_DM3 MEM_MB_DM2 MEM_MB_DM1 MEM_MB_DM0

AJ19

AK19

A18 A19 U31 U30

AE30 AC31

AD29

AL19 AL18

C19

D19 W29 W28

AE29 AB31

AD31

AC29 AC30 AB29

N31

AA31 AA28

M31 M29

N28

N29

AE31

N30

P29

AA29

P31

R29

R28

R31

R30

T31

T29

U29

U28

AA30 AK13

AJ13

AK17

AJ17

AK23

AL23 AL28 AL29

D31

C31

C24

C23

D17

C17

C14

C13

AJ14

AH17

AJ23

AK29

C30

A23

B17

B13

MEMORY INTERFACE B

MB0_CLK_H(2) MB0_CLK_L(2) MB0_CLK_H(1) MB0_CLK_L(1) MB0_CLK_H(0) MB0_CLK_L(0)

MB0_CS_L(1) MB0_CS_L(0)

MB0_ODT(0) MB1_CLK_H(2)

MB1_CLK_L(2) MB1_CLK_H(1) MB1_CLK_L(1) MB1_CLK_H(0) MB1_CLK_L(0)

MB1_CS_L(1) MB1_CS_L(0)

MB1_ODT(0)

MB_CAS_L MB_WE_L MB_RAS_L

MB_BANK(2) MB_BANK(1) MB_BANK(0)

MB_CKE(1) MB_CKE(0)

MB_ADD(15) MB_ADD(14) MB_ADD(13) MB_ADD(12) MB_ADD(11) MB_ADD(10) MB_ADD(9) MB_ADD(8) MB_ADD(7) MB_ADD(6) MB_ADD(5) MB_ADD(4) MB_ADD(3) MB_ADD(2) MB_ADD(1) MB_ADD(0)

MB_DQS_H(7) MB_DQS_L(7) MB_DQS_H(6) MB_DQS_L(6) MB_DQS_H(5) MB_DQS_L(5) MB_DQS_H(4) MB_DQS_L(4) MB_DQS_H(3) MB_DQS_L(3) MB_DQS_H(2) MB_DQS_L(2) MB_DQS_H(1) MB_DQS_L(1) MB_DQS_H(0) MB_DQS_L(0)

MB_DM(7) MB_DM(6) MB_DM(5) MB_DM(4) MB_DM(3) MB_DM(2) MB_DM(1) MB_DM(0)

U1C

MB_DATA(63) MB_DATA(62) MB_DATA(61) MB_DATA(60) MB_DATA(59) MB_DATA(58) MB_DATA(57) MB_DATA(56) MB_DATA(55) MB_DATA(54) MB_DATA(53) MB_DATA(52) MB_DATA(51) MB_DATA(50) MB_DATA(49) MB_DATA(48) MB_DATA(47) MB_DATA(46) MB_DATA(45) MB_DATA(44) MB_DATA(43) MB_DATA(42) MB_DATA(41) MB_DATA(40) MB_DATA(39) MB_DATA(38) MB_DATA(37) MB_DATA(36) MB_DATA(35) MB_DATA(34) MB_DATA(33) MB_DATA(32) MB_DATA(31) MB_DATA(30) MB_DATA(29) MB_DATA(28) MB_DATA(27) MB_DATA(26) MB_DATA(25) MB_DATA(24) MB_DATA(23) MB_DATA(22) MB_DATA(21) MB_DATA(20) MB_DATA(19) MB_DATA(18) MB_DATA(17) MB_DATA(16) MB_DATA(15) MB_DATA(14) MB_DATA(13) MB_DATA(12) MB_DATA(11) MB_DATA(10)

MB_DATA(9) MB_DATA(8) MB_DATA(7) MB_DATA(6) MB_DATA(5) MB_DATA(4) MB_DATA(3) MB_DATA(2) MB_DATA(1) MB_DATA(0)

MB_DQS_H(8)

MB_DQS_L(8)

MB_DM(8)

MB_CHECK(7) MB_CHECK(6) MB_CHECK(5) MB_CHECK(4) MB_CHECK(3) MB_CHECK(2) MB_CHECK(1) MB_CHECK(0)

AH13 AL13 AL15 AJ15 AF13 AG13 AL14 AK15 AL16 AL17 AK21 AL21 AH15 AJ16 AH19 AL20 AJ22 AL22 AL24 AK25 AJ21 AH21 AH23 AJ24 AL27 AK27 AH31 AG30 AL25 AL26 AJ30 AJ31 E31 E30 B27 A27 F29 F31 A29 A28 A25 A24 C22 D21 A26 B25 B23 A22 B21 A20 C16 D15 C21 A21 A17 A16 B15 A14 E13 F13 C15 A15 A13 D13

J31 J30

J29 K29

K31 G30 G29 L29 L28 H31 G31

3

MEM_MB_DATA63 MEM_MB_DATA62 MEM_MB_DATA61 MEM_MB_DATA60 MEM_MB_DATA59 MEM_MB_DATA58 MEM_MB_DATA57 MEM_MB_DATA56 MEM_MB_DATA55 MEM_MB_DATA54 MEM_MB_DATA53 MEM_MB_DATA52 MEM_MB_DATA51 MEM_MB_DATA50 MEM_MB_DATA49 MEM_MB_DATA48 MEM_MB_DATA47 MEM_MB_DATA46 MEM_MB_DATA45 MEM_MB_DATA44 MEM_MB_DATA43 MEM_MB_DATA42 MEM_MB_DATA41 MEM_MB_DATA40 MEM_MB_DATA39 MEM_MB_DATA38 MEM_MB_DATA37 MEM_MB_DATA36 MEM_MB_DATA35 MEM_MB_DATA34 MEM_MB_DATA33 MEM_MB_DATA32 MEM_MB_DATA31 MEM_MB_DATA30 MEM_MB_DATA29 MEM_MB_DATA28 MEM_MB_DATA27 MEM_MB_DATA26 MEM_MB_DATA25 MEM_MB_DATA24 MEM_MB_DATA23 MEM_MB_DATA22 MEM_MB_DATA21 MEM_MB_DATA20 MEM_MB_DATA19 MEM_MB_DATA18 MEM_MB_DATA17 MEM_MB_DATA16 MEM_MB_DATA15 MEM_MB_DATA14 MEM_MB_DATA13 MEM_MB_DATA12 MEM_MB_DATA11 MEM_MB_DATA10 MEM_MB_DATA9 MEM_MB_DATA8 MEM_MB_DATA7 MEM_MB_DATA6 MEM_MB_DATA5 MEM_MB_DATA4 MEM_MB_DATA3 MEM_MB_DATA2 MEM_MB_DATA1 MEM_MB_DATA0

MEM_MB_CHECK7 MEM_MB_CHECK6 MEM_MB_CHECK5 MEM_MB_CHECK4 MEM_MB_CHECK3 MEM_MB_CHECK2 MEM_MB_CHECK1 MEM_MB_CHECK0

MEM_MB_DATA[63..0] 11,12

MEM_MB_DQS_H8 11,12 MEM_MB_DQS_L8 11,12

MEM_MB_DM8 11,12

MEM_MB_CHECK[7..0] 11,12

2

1

A A

TECHNOLOGY COPR.

Title

Document Number Rev

Date: Sheet

5

4

3

2

Date: Sheet

M2-3 DDR-2

CK804A07

TECHNOLOGY COPR.

of

841Tuesday, October 31, 2006

of

841Tuesday, October 31, 2006

of

841Tuesday, October 31, 2006

1

A

5

Level translation buffers Assuming system devices Do not provide VDDIO compatible voltage levels

HT_STOP*14

D D

DS

Q3

CK8_PWRGD18,39

These signals must be driven low during S3 and S5 states, including

C C

state transitions, to meet HT I/O Link Specification

B B

A A

G

2N7002-7-FQ32N7002-7-F

CPU_RST*14

CPU_PWRGD14

Note 1

5-bit VID Implementation: VID4:0 connects to VID4:0 of regulator* VID5 should be left unconnected. VID1 should be pulled up to VDDIO for compatibility with future processors * Translation may be needed to meet the input requirements of the regulator inputs (See datasheet for processor Voh specs & regulator datasheet for Vih min requirements)

6-bit VID Implementation: VID5:0 directly connects to VID5:0 of regulator. VID1 should be pulled up to VDDIO for compatibility with future processors NOTE: There is an incompatibility between the 5-bit VID code & 6-bit VID code x11111b. VID code 11111b is FF for 5-bit VID controllers & a valid VID code for 6-bit VID controllers (011111b is 775mv & 111111b is 375mv). These are not planned to be operating VID for non-mobile抯 processors so no adverse system implications will occur using a 5-bit VID or 6-bit controller in non-mobile implementations. Please see AMD Socket M2 Motherboard Design Guide, PID #33165 for more details.

5

M2_DE_Glitching

R102

1K

+-5%

r0603h6

R112

1K

+-5%

r0603h6

M2_DE_Glitching

R125

1K

+-5%

r0603h6

M2_DE_Glitching

DS

Q1

G

2N7002-7-FQ12N7002-7-F

DS

Q4

G

2N7002-7-FQ42N7002-7-F

DS

Q7

G

2N7002-7-FQ72N7002-7-F

1D8V_STR3D3V_SYS 3D3V_DUAL

R104

R103

300

680

+/-5%

R0603

r0603h6

DS

Q2

G

2N7002-7-FQ22N7002-7-F

3D3V_DUAL 1D8V_STR3D3V_SYS

R107

R106

300

680

+/-5%

R0603

r0603h6

DS

Q5

G

2N7002-7-FQ52N7002-7-F

3D3V_DUAL 1D8V_STR3D3V_SYS

R127

R126

300

680

+/-5%

R0603

r0603h6

DS

Q8

G

2N7002-7-FQ82N7002-7-F

慜

4

CPU_LDTSTOP_L

5V_SYS

C100

1uF

*

Dummy

C0603

Keep trace to resistor less than 600mils from CPU pin and trace to AC caps less than 1250mils

CPU_HT_RESET_L

CPU_ALL_PWROK

U1J

<PART_NAME>

<PART_NAME> bga940j_socket-m2h64

bga940j_socket-m2h64

5

MTG1

6

MTG1

7

MTG1

8

MTG1

9

MTG1

10

MTG1

11

MTG1

12

MTG1

1

EMI

2

EMI

13

MTG2

14

MTG2

15

MTG2

16

MTG2

17

MTG2

18

MTG2

19

MTG2

20

MTG2

<PATH>

4

C101

0.1uF

C0603

U3 AME8800

Dummy

3

V_IN

V_OUT

GND

1

MTG3 MTG3 MTG3 MTG3 MTG3 MTG3 MTG3 MTG3

MTG4 MTG4 MTG4 MTG4 MTG4 MTG4 MTG4 MTG4

EMI EMI

2

21 22 23 24 25 26 27 28

3 4

29 30 31 32 33 34 35 36

GND

+2.5V

C102

22uF

*

10V, Y5V, +80%/-20%

Dummy

C1206

CPU_CLKIN_H14

CPU_CLKIN_L14

CPU_SIC32 CPU_SID32

1D8V_STR

GND

3

CPU_VDDA_RUN

CP1

Dummy

12

X_COPPER

FB1

Dummy

*

FB L0805 200 Ohm

C106

1D8V_STR

R108

R108 300

300

+/-5%

R0603

Dummy

R118 39.2 +/-1% r0402h4

*

R120 39.2 +/-1% r0402h4

*

CPU_THERMDC34 CPU_THERMDA34

L25 L26 L31 L30

W26 W25

AE27

U24 V24

AE28

Y31 Y30

AG31

V31

W31

AF31

C103

4.7uF

*

C0805

3.9nF C0603 50V, X7R, +/-10%

*

R109

R109 169 Ohm

169 Ohm

+/-1%

r0603h6

C107

3.9nF C0603 50V, X7R, +/-10%

*

CPU_PRESENT36

R113

R113 300

300

+/-5%

R0603

Dummy

R116

R116 300

300

+/-5%

R0603

CPU_VDD_RUN_FB_H36 CPU_VDD_RUN_FB_L36

GND

TP4TP4

CPU_M_VREF_SUS

R123 300 +/-5% R0603R123 300 +/-5% R0603 R122 300 +/-5% R0603R122 300 +/-5% R0603

GND

TP6TP6 TP7TP7 TP9TP9 TP13TP13 TP12TP12

U1E

INTERNAL MISC

RSVD1 RSVD2 RSVD3 RSVD4

RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10

RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16

C104

0.22uF

*

C0603

CPU_CLKIN_SC_H CPU_CLKIN_SC_L

CPU_ALL_PWROK

CPU_LDTSTOP_L

CPU_HT_RESET_L

CPU_PRESENT_L

CPU_SIC CPU_SID

CPU_TDI CPU_TRST_L CPU_TCK CPU_TMS

CPU_DBREQ_L

1

M_ZN M_ZP

1

CPU_TEST16

1

CPU_TEST15

1

CPU_TEST14

1

CPU_TEST12

1

CPU_THERMDC CPU_THERMDA CPU_TEST26

RSVD17 RSVD18

RSVD19 RSVD20 RSVD21

RSVD22 RSVD23

RSVD24 RSVD25 RSVD26

RSVD27 RSVD28 RSVD29 RSVD30 RSVD31 RSVD32 RSVD33 RSVD34 RSVD35 RSVD36 RSVD37 RSVD38

CPU Control & Debug Interfaces

VREG_VID4----RN1.6VREG_VID2---RN1.4VREG_VID3---RN1.2

C105

3.3nF

C0603

C10

VDDA1

D10

VDDA2

A8

CLKIN_H

B8

CLKIN_L

C9

PWROK

D8

LDTSTOP_L

C7

RESET_L

AL3

CPU_PRESENT_L

AL6

SIC

AK6

SID

AL10

TDI

AJ10

TRST_L

AH10

TCK

AL9

TMS

A5

DBREQ_L

G2

VDD_FB_H

G1

VDD_FB_L

E12

VTT_SENSE

F12

M_VREF

AH11

M_ZN

AJ11

GND

A10 B10 F10

E9

AJ7

F6 D6

E7 F8 C5

AH9

E5

AJ5 AG9 AG8 AH7

AJ6

CPU_DBREQ_L CPU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST_L CPU_TDO

M_ZP TEST25_H

TEST25_L TEST19 TEST18 TEST13 TEST9

TEST17 TEST16 TEST15 TEST14 TEST12

TEST7 TEST6 THERMDC THERMDA TEST3 TEST2

CPU_TEST25_H CPU_TEST25_L

E20 B19

AL4 AK4 AK3

F2 F3

G4 G3 G5

AD25 AE24 AE25 AJ18 AJ20 C18 C20 G24 G25 H25 V29 W30

CPU_M_VREF_SUS

*

0.1uF

C0603

C108

CPU_M_VREF_SUS

C109

1nF

*

Layout: Place near CPU socket

C0603

GND

1D8V_STR

3

R133

16.9

r0603h6

+/-1%

R134

16.9

+/-1%

r0603h6

2

Required for compatibility

with future processors

See Note 1

U1D

MISC

CPU_VID5

D2

CPU_VID4

D1

CPU_VID3

C1

CPU_VID2

E3

CPU_VID1

E2

CPU_VID0

E1 AK7

CPU_PROCHOT_L_1.8

AL7

CPU_TDO

AK10

CPU_DBRDY

B6 AK11

CPU_VDDIO_SUS_FB_L

AL11

CPU_PSI_LCPU_VTT_SUS_SENSE

F1

CPU_HTREF1

V8

CPU_HTREF0

V7

C11 D11

AK8 AH8 AJ9 AL8 AJ8

J10 H9 AK9 AK5 G7 D4

1 1 1 1 1 1 1

2

1

CPU_TEST29_H CPU_TEST29_L

CPU_TEST24CPU_TEST17 CPU_TEST23 CPU_TEST22 CPU_TEST21 CPU_TEST20

TP15TP15 TP16TP16 TP18TP18 TP17TP17 TP20TP20 TP19TP19 TP21TP21

VID(5) VID(4) VID(3) VID(2) VID(1) VID(0)

THERMTRIP_L

PROCHOT_L

TDO

DBRDY

VDDIO_FB_H VDDIO_FB_L

PSI_L

HTREF1 HTREF0

TEST29_H

TEST29_L

TEST24 TEST23 TEST22 TEST21 TEST20

TEST28_H

TEST28_L

TEST27 TEST26 TEST10

TEST8

Erratum 133, Revision Guide for AMD NPT 0Fh Processors

1

1D8V_STR

R105

R110

300

+/-5%

R0603

TP3TP3

CPU_THERMTRIP_L

1

1 1 1

1

FAB B change

CPU_THERMTRIP_L

R646

Dummy

CPU_TEST26

CPU_PRESENT_L CPU_VDD_RUN_FB_L CPU_TEST25_H

CPU_TEST25_L

CPU_TEST21

1D8V_STR

R111

R111 300

300

*

135

+/-5%

R0603

CPU_VDDIO_SUS_FB_H

TP5TP5

R119 44.2R119 44.2 R121 44.2R121 44.2

TP8TP8 TP10TP10 TP11TP11

TP14TP14

1D8V_STR

Dummy

R647

r0603h6R647

r0603h6

1K +-5%

0

R128 300 R0603 +/-5%R128 300 R0603 +/-5%

R129 1K +-5%

R129 1K +-5% R130 510

R131 510 r0603h6 +/-1%R131 510 r0603h6 +/-1%

R132 300 R0603 +/-5%R132 300 R0603 +/-5%

1D8V_STR

+/-5%

78

8P4R0603

330

642

RN1

R114 4.7K

r0603h6 +/-5%

RN21

*

1 3 5 7 8

4.7K

8p4r0603h7

+/-5%

1D2V_HT

GND

R124

80.6

Route as 80-Ohm differential impedance

+/-1%

r0603h6

Keep trace to resistor less than 1" from CPU pin

5V_SB_SYS

R644

680

+/-5%

r0603h6

R649 0

Dummy

r0603h6

+-5%

1K

R648

Dummy

Q70

B

PMBT3904

E C

R6500R650 0

GND

1D8V_STR

FAB B change

r0603h6

r0603h6 r0603h6

r0603h6

+/-1%R130 510

+/-1%

GND

Title

Document Number Rev

Date: Sheet

Date: Sheet of

B

Q38

Q38 PMBT3904

PMBT3904

B

Q39

Q39 PMBT3904

PMBT3904

B

2

Q42

4

PMBT3904

6

B

Q43

Q43 PMBT3904

PMBT3904

B

Q63

Q63 PMBT3904

PMBT3904

Keep trace to resistors less than 1.5" from CPU pin

3D3V_DUAL

R645

1K

+-5%

r0603h6

DS

Q71

G

2N7002-7-F

GND

CPU_VDD_RUN_FB_H

CPU_TEST29_H CPU_TEST29_L

CPU_VDDIO_SUS_FB_H CPU_VDDIO_SUS_FB_L

CPU_ALL_PWROK

CPU_LDTSTOP_L

CPU_HT_RESET_L

CPU_THERMTRIP_L

M2-4 MISC

CK804A07

1

3V_CPU_VID4 32,41

CPU_VID4

E C

3V_CPU_VID3 32,41

CPU_VID3

E C

3V_CPU_VID2 32,41

CPU_VID2

E C

3V_CPU_VID1 32,41

CPU_VID1

E C

3V_CPU_VID0 32,41

CPU_VID0

E C

CPU_VDDA_RUN

CPU_THERMTRIP* 14

TP22TP22

1

TP25TP25

1

TP26TP26

1

TP28TP28

1

TP27TP27

1

TP30TP30

1

TP29TP29

1

TP31TP31

1

TP32TP32

1

TP33TP33

1

TP34TP34

1

TECHNOLOGY COPR.

of

941Tuesday, October 31, 2006

A

5

4

3

2

1

Processor Power & Ground

D D

+V_CPU

C C

B B

A A

AA10 AA12 AA14 AA16 AA18

AB11

AC10

AE10

U1F

VDD1

A4

VDD1

A6

VDD2

AA8

VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

AB7

VDD9

AB9

VDD10 VDD11

AC4

VDD12

AC5

VDD13

AC8

VDD14 VDD15

AD2

VDD16

AD3

VDD17

AD7

VDD18

AD9

VDD19 VDD20

AF7

VDD21

AF9

VDD22

AG4

VDD23

AG5

VDD24

AG7

VDD25

AH2

VDD26

AH3

VDD27

B3

VDD28

B5

VDD29

B7

VDD30

C2

VDD31

C4

VDD32

C6

VDD33

C8

VDD34

D3

VDD35

D5

VDD36

D7

VDD37

D9

VDD38

E4

VDD39

E6

VDD40

E8

VDD41

E10

VDD42

F5

VDD43

F7

VDD44

F9

VDD45

F11

VDD46

G6

VDD47

G8

VDD48

G10

VDD49

G12

VDD50

H7

VDD51

H11

VDD52

H23

VDD53

J8

VDD54

J12

VDD55

J14

VDD56

J16

VDD57

J18

VDD58

J20

VDD59

J22

VDD60

J24

VDD61

K7

VDD62

K9

VDD63

K11

VDD64

K13

VDD65

K15

VDD66

K17

VDD67

K19

VDD68

K21

VDD69

K23

VDD70

L4

VDD71

L5

VDD72

L8

VDD73

L10

VDD74

L12

VDD75

Y17

VDD150

Y19

VDD151

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8

VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75

VSS240 VSS241

A3 A7 A9 A11 AA4 AA5 AA7 AA9 AA11 AA13 AA15 AA17 AA19 AA21 AA23 AB2 AB3 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC7 AC9 AC11 AC13 AC15 AC17 AC19 AC21 AC23 AD8 AD10 AD12 AD14 AD16 AD20 AD22 AD24 AE4 AE5 AE9 AE11 AF2 AF3 AF8 AF10 AF12 AF14 AF16 AF18 AF20 AF22 AF24 AF26 AF28 AG10 AG11 AH14 AH16 AH18 AH20 AH22 AH24 AH26 AH28 AH30 AK2 AK14 AK16 AK18 Y14 Y16

GND

5

CPU_AH14 41

+V_CPU

U1G

VDD2

L14

VDD1

L16

VDD2

L18

VDD3

M2

VDD4

M3

VDD5

M7

VDD6

M9

VDD7

M11

VDD8

M13

VDD9

M15

VDD10

M17

VDD11

M19

VDD12

N8

VDD13

N10

VDD14

N12

VDD15

N14

VDD16

N16

VDD17

N18

VDD18

P7

VDD19

P9

VDD20

P11

VDD21

P13

VDD22

P15

VDD23

P17

VDD24

P19

VDD25

R4

VDD26

R5

VDD27

R8

VDD28

R10

VDD29

R12

VDD30

R14

VDD31

R16

VDD32

R18

VDD33

R20

VDD34

T2

VDD35

T3

VDD36

T7

VDD37

T9

VDD38

T11

VDD39

T13

VDD40

T15

VDD41

T17

VDD42

T19

VDD43

T21

VDD44

U8

VDD45

U10

VDD46

U12

VDD47

U14

VDD48

U16

VDD49

U18

VDD50

U20

VDD51

V9

VDD52

V11

VDD53

V13

VDD54

V15

VDD55

V17

VDD56

V19

VDD57

V21

VDD58

W4

VDD59

W5

VDD60

W8

VDD61

W10

VDD62

W12

VDD63

W14

VDD64

W16

VDD65

W18

VDD66

W20

VDD67

Y2

VDD68

Y3

VDD69

Y7

VDD70

Y9

VDD71

Y11

VDD72

Y13

VDD73

Y15

VDD74

Y21

VDD75

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8

VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75

AK20 AK22 AK24 AK26 AK28 AK30 AL5 B4 B9 B11 B14 B16 B18 B20 B22 B24 B26 B28 B30 C3 D14 D16 D18 D20 D22 D24 D26 D28 D30 E11 F4 F14 F16 F18 F20 F22 F24 F26 F28 F30 G9 G11 H8 H10 H12 H14 H16 H18 H22 H24 H26 H28 H30 J4 J5 J7 J9 J11 J13 J15 J17 J19 J21 J23 K2 K3 K8 K10 K12 K14 K16 K18 K20 K22 Y18

GND

Place near processor on VLDT pour.

1D2V_HT

C155

C154

4.7uF

*

C0805

*

C0805

10V, Y5V, +80%/-20%

4

C156

0.22uF

C0603

+V_CPU

AA20 AA22 AB13 AB15 AB17 AB19 AB21 AB23 AC12 AC14 AC16 AC18 AC20 AC22 AD11 AD23 AE12 AF11

C157

0.22uF

*

C0603

10V, X7R, +/-10%

U1H

VDD3

N17

VSS1

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

L20

VDD19

L22

VDD20

M21

VDD21

M23

VDD22

N20

VDD23

N22

VDD24

P21

VDD25

P23

VDD26

R22

VDD27

T23

VDD28

U22

VDD29

V23

VDD30

W22

VDD31

Y23

VDD32

C158

C159

180pF

*

C0603

GND

50V, NPO, +/-5%

N19

VSS2

N21

VSS3

N23

VSS4

P2

VSS5

P3

VSS6

P8

VSS7

P10

VSS8

P12

VSS9

P14

VSS10

P16

VSS11

P18

VSS12

P20

VSS13

P22

VSS14

R7

VSS15

R9

VSS16

R11

VSS17

R13

VSS18

R15

VSS19

R17

VSS20

R19

VSS21

R21

VSS22

R23

VSS23

T8

VSS24

T10

VSS25

T12

VSS26

T14

VSS27

T16

VSS28

T18

VSS29

T20

VSS30

T22

VSS31

U4

VSS32

U5

VSS33

U7

VSS34

U9

VSS35

U11

VSS36

U13

VSS37

U15

VSS38

U17

VSS39

U19

VSS40

U21

VSS41

U23

VSS42

V2

VSS43

V3

VSS44

V10

VSS45

V12

VSS46

V14

VSS47

V16

VSS48

V18

VSS49

V20

VSS50

V22

VSS51

W9

VSS52

W11

VSS53

W13

VSS54

W15

VSS55

W17

VSS56

W19

VSS57

W21

VSS58

W23

VSS59

Y8

VSS60

Y10

VSS61

Y12

VSS62

W7

VSS63

Y20

VSS64

Y22

VSS65

GND

50V, NPO, +/-5%

VLDT_RUN_B is connected to the VLDT_RUN power supply through the package or on the die. It is only connected on the board to decoupling near the CPU package.

U1I

1D2V_HT

VTT_DDR VTT_DDR

1D8V_STR

AB24 AB26 AB28 AB30 AC24 AD26 AD28 AD30 AF30

U1I

VDDIO

AJ4

VLDT_A1

AJ3

VLDT_A2

AJ2

VLDT_A3

AJ1

VLDT_A4

D12

VTT1

C12

VTT2

B12

VTT3

A12

VTT4 VDDIO1

VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO29

M24

VDDIO9

M26

VDDIO10

M28

VDDIO11

M30

VDDIO12

P24

VDDIO13

P26

VDDIO14

P28

VDDIO15

P30

VDDIO16

T24

VDDIO17

T26

VDDIO18

T28

VDDIO19

T30

VDDIO20

V25

VDDIO21

V26

VDDIO22

V28

VDDIO23

V30

VDDIO24

Y24

VDDIO25

Y26

VDDIO26

Y28

VDDIO27

Y29

VDDIO28

VLDT_B1 VLDT_B2 VLDT_B3 VLDT_B4

VTT5 VTT6 VTT7 VTT8 VTT9

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8

VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28

H6 H5 H2 H1

AK12 AJ12 AH12 AG12 AL12

K24 K26 K28 K30 L7 L9 L11 L13 L15 L17 L19 L21 L23 M8 M10 M12 M14 M16 M18 M20 M22 N4 N5 N7 N9 N11 N13 N15

GND

VLDT_RUN_B

*

GND

Decoupling Between Processor and DIMMs Place as close to processor as possible.

1D8V_STR

C140

VTT_DDR

3

C140

C141

4.7uF

*

C0805

10V, Y5V, +80%/-20%

C146

C147

4.7uF

*

C0805

10V, Y5V, +80%/-20%

C161

C160

4.7uF

*

C0805

10V, Y5V, +80%/-20%

C143

C142

0.22uF

*

C0603

GND

10V, X7R, +/-10%

C148

C149

0.22uF

*

C0603

10V, X7R, +/-10%

C163

C162

0.22uF

*

C0603

10V, X7R, +/-10%

C151

C150

1nF

*

C0603

50V, X7R, +/-10%

C164

C165

1nF

*

C0603

50V, X7R, +/-10%

C153

C152

180pF

*

C0603

GND

50V, NPO, +/-5%

C166

C167

180pF

*

C0603

GND

50V, NPO, +/-5%

C110

4.7uF

C0805

Bottomside Decoupling

10V, Y5V, +80%/-20%

+V_CPU

C111

*

+V_CPU

*

1D8V_STR

*

C111

22uF

*

C1206

6.3V, X5R, +/-20%

@BOTTOM

C126

0.22uF

*

C0603

10V, X7R, +/-10%

@BOTTOM

C131

22uF

C1206

6.3V, X5R, +/-20%

@BOTTOM

C112

22uF

C1206

@BOTTOM

C127

0.22uF

C0603

@BOTTOM

*

6.3V, X5R, +/-20%

*

10V, X7R, +/-10%

C132

22uF

*

C1206

6.3V, X5R, +/-20%

@BOTTOM

2

C116

*

6.3V, X5R, +/-20%

*

GND

50V, X7R, +/-10%

C134

4.7uF

*

C0805

10V, Y5V, +80%/-20%

@BOTTOM

C115

22uF

*

C1206

6.3V, X5R, +/-20%

@BOTTOM

C130

180pF

C0603

50V, NPO, +/-5%

@BOTTOM

C135

0.22uF

C0603

10V, X7R, +/-10%

@BOTTOM

C116

22uF

C1206

@BOTTOM

*

C113

22uF

*

C1206

6.3V, X5R, +/-20%

@BOTTOM

C128

0.22uF

*

C0603

10V, X7R, +/-10%

@BOTTOM

C133

4.7uF

C0805

10V, Y5V, +80%/-20%

@BOTTOM

C114

22uF

C1206

@BOTTOM

C129

10nF

C0603

@BOTTOM

*

Decoupling Between Processor and DIMMs

*

6.3V, X5R, +/-20%

C136

0.22uF

*

C0603

10V, X7R, +/-10%

@BOTTOM

C117

22uF

*

C1206

6.3V, X5R, +/-20%

@BOTTOM

C137

0.22uF

C0603

10V, X7R, +/-10%

@BOTTOM

C118

22uF

C1206

@BOTTOM

*

C125

M2

C125

C124

22uF

*

C1206

GND

6.3V, X5R, +/-20%

@BOTTOM

6.3V, X5R, +/-20%

@BOTTOM

6.3V, X5R, +/-20%

A31

*

6.3V, X5R, +/-20%

C138

10nF

*

C0603

GND

50V, X7R, +/-10%

@BOTTOM

1D8V_STR

C144

180pF

*

C0603

C119

22uF

*

C1206

6.3V, X5R, +/-20%

@BOTTOM

C139

180pF

C0603

50V, NPO, +/-5%

@BOTTOM

*

GND

50V, NPO, +/-5%

C120

22uF

*

C1206

6.3V, X5R, +/-20%

@BOTTOM

A1

C145

180pF

C0603

50V, NPO, +/-5%

C121

22uF

*

C1206

6.3V, X5R, +/-20%

@BOTTOM

C122

22uF

*

C1206

6.3V, X5R, +/-20%

@BOTTOM

Top View

C123

22uF

C1206

@BOTTOM

AL1

TECHNOLOGY COPR.

Title

Document Number Rev

Date: Sheet of

Date: Sheet

M2-5 Power

CK804A07

1

TECHNOLOGY COPR.

of

10 41Tuesday, October 31, 2006

A

5

4

3

SMB_MEM BUS ADDRESS

DIMM 0 DIMM 1 DIMM 2 DIMM 3

1010 000 1010 001 1010 010 1010 011

2

1

DIMMA0

D D

MEM_MA_DM[7..0]7,12

MEM_MA_DQS_H87,12

MEM_MA_DQS_L87,12 MEM_MA_DQS_H[7..0]7,12 MEM_MA_DQS_L[7..0]7,12

C C

MEM_MA_ADD[15..0]7,12,13

B B

MEM_MA_CHECK[7..0]7,12

A A

MEM_MA_DM87,12

GND

SMB_MEM_SDA12,18 MEM_MA_BANK27,12,13 MEM_MA_BANK17,12,13 MEM_MA_BANK07,12,13

MEM_MA0_CLK_H07,13 MEM_MA0_CLK_L07,13 MEM_MA0_CLK_H17,13 MEM_MA0_CLK_L17,13 MEM_MA0_CLK_H27,13 MEM_MA0_CLK_L27,13

MEM_MA_CKE07,13 MEM_MA_RAS_L7,12,13

MEM_MA_CAS_L7,12,13 MEM_MA0_CS_L07,13

MEM_MA0_CS_L17,13

MEM_MA_DM7

MEM_MA_DM6

MEM_MA_DM5

MEM_MA_DM4

MEM_MA_DM3

MEM_MA_DM2

MEM_MA_DM1

MEM_MA_DM0

MEM_MA_DQS_H7 MEM_MA_DQS_L7 MEM_MA_DQS_H6 MEM_MA_DQS_L6 MEM_MA_DQS_H5 MEM_MA_DQS_L5 MEM_MA_DQS_H4 MEM_MA_DQS_L4 MEM_MA_DQS_H3 MEM_MA_DQS_L3 MEM_MA_DQS_H2 MEM_MA_DQS_L2 MEM_MA_DQS_H1 MEM_MA_DQS_L1 MEM_MA_DQS_H0 MEM_MA_DQS_L0

MEM_MA_ADD15 MEM_MA_ADD14 MEM_MA_ADD13 MEM_MA_ADD12 MEM_MA_ADD11 MEM_MA_ADD10 MEM_MA_ADD9 MEM_MA_ADD8 MEM_MA_ADD7 MEM_MA_ADD6 MEM_MA_ADD5 MEM_MA_ADD4 MEM_MA_ADD3 MEM_MA_ADD2 MEM_MA_ADD1 MEM_MA_ADD0

MEM_MA_CHECK6 MEM_MA_CHECK5 MEM_MA_CHECK4 MEM_MA_CHECK3 MEM_MA_CHECK2 MEM_MA_CHECK1 MEM_MA_CHECK0

MEM_MA_CKE0

5

1D8V_STR

172

178

184

187

189

197

64

69

170

175

181

191

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD753VDD859VDD9

VDD1067VDD11

VDDQ1

VDDQ2

164

DQS17_H

165

DQS17_L

232

DQS16_H

233

DQS16_L

223

DQS15_H

224

DQS15_L

211

DQS14_H

212

DQS14_L

202

DQS13_H

203

DQS13_L

155

DQS12_H

156

DQS12_L

146

DQS11_H

147

DQS11_L

134

DQS10_H

135

DQS10_L

125

DQS9_H

126

DQS9_L

46

DQS8_H

45

DQS8_L

114

DQS7_H

113

DQS7_L

105

DQS6_H

104

DQS6_L

93

DQS5_H

92

DQS5_L

84

DQS4_H

83

DQS4_L

37

DQS3_H

36

DQS3_L

28

DQS2_H

27

DQS2_L

16

DQS1_H

15

DQS1_L

7

DQS0_H

6

DQS0_L

101

SA2

240

SA1

239

SA0

120

SCL

119

SDA

54

BA2

190

BA1

71

BA0

173

A15

174

A14

196

A13

176

A12

57

A11

70

A10

177

A9

179

A8

58

A7

180

A6

60

A5

61

A4

182

A3

63

A2

183

A1

188

A0

168

CB7

167

CB6

162

CB5

161

CB4

49

CB3

48

CB2

43

CB1

42

CB0

185

CK0_H

186

CK0_L

137

CK1_H

138

CK1_L

220

CK2_H

221

CK2_L

18

RESET_L

52

CKE0

171

CKE1

192

RAS_L

74

CAS_L

193

S0_L

76

S1_L

VDDQ3

3D3V_SYS 3D3V_SYS

238

78

194

72

VDDQ4

VDDQ5

VDDQ651VDDQ756VDDQ862VDDQ9

VDDQ1075VDDQ11

VDDSPD

ERR_OUT_L

4

First Logical DDR2 DIMM

DIMM1DIMM1

MEM_MA_DATA63

236

DQ63

MEM_MA_DATA62

235

DQ62

MEM_MA_DATA61

230

DQ61

MEM_MA_DATA60

229

DQ60

MEM_MA_DATA59

117

DQ59

MEM_MA_DATA58

116

DQ58

MEM_MA_DATA57

111

DQ57

MEM_MA_DATA56

110

DQ56

MEM_MA_DATA55

227

DQ55

MEM_MA_DATA54

226

DQ54

MEM_MA_DATA53

218

DQ53

MEM_MA_DATA52

217

DQ52

MEM_MA_DATA51

108

DQ51

MEM_MA_DATA50

107

DQ50

MEM_MA_DATA49

99

DQ49

MEM_MA_DATA48

98

DQ48

MEM_MA_DATA47

215

DQ47

MEM_MA_DATA46

214

DQ46

MEM_MA_DATA45

209

DQ45

MEM_MA_DATA44

208

DQ44

MEM_MA_DATA43

96

DQ43

MEM_MA_DATA42

95

DQ42

MEM_MA_DATA41

90

DQ41

MEM_MA_DATA40

89

DQ40

MEM_MA_DATA39

206

DQ39

MEM_MA_DATA38

205

DQ38

MEM_MA_DATA37

200

DQ37

MEM_MA_DATA36

199

DQ36

MEM_MA_DATA35

87

DQ35

MEM_MA_DATA34

86

DQ34

MEM_MA_DATA33

81

DQ33

MEM_MA_DATA32

80

DQ32

MEM_MA_DATA31

159

DQ31

MEM_MA_DATA30

158

DQ30

MEM_MA_DATA29

153

DQ29

MEM_MA_DATA28

152

DQ28

MEM_MA_DATA27

40

DQ27

MEM_MA_DATA26

39

DQ26

MEM_MA_DATA25

34

DQ25

MEM_MA_DATA24

33

DQ24

MEM_MA_DATA23

150

DQ23

MEM_MA_DATA22

149

DQ22

MEM_MA_DATA21

144

DQ21

MEM_MA_DATA20

143

DQ20

MEM_MA_DATA19

31

DQ19

MEM_MA_DATA18

30

DQ18

MEM_MA_DATA17

25

DQ17

MEM_MA_DATA16

24

DQ16

MEM_MA_DATA15

141

DQ15

MEM_MA_DATA14

140

DQ14

MEM_MA_DATA13

132

DQ13

MEM_MA_DATA12

131

DQ12

MEM_MA_DATA11

22

DQ11

MEM_MA_DATA10

21

DQ10

MEM_MA_DATA9

13

DQ9

MEM_MA_DATA8

12

DQ8

MEM_MA_DATA7

129

DQ7

MEM_MA_DATA6

128

DQ6

MEM_MA_DATA5

123

DQ5

MEM_MA_DATA4

122

DQ4

MEM_MA_DATA3

10

DQ3

MEM_MA_DATA2

9

DQ2

MEM_MA_DATA1

4

DQ1

MEM_MA_DATA0MEM_MA_CHECK7

3

DQ0

73 1 102 195

77 55

68 19

MEM_MA_WE_L 7,12,13

MEM_MA0_ODT0 7,13

GND

WE_L VREF

TEST

ODT0 ODT1

PAR_IN

NC1

MEM_M_VREF_SUS

MEM_MA_DATA[63..0] 7,12

MEM_M_VREF_SUS

1D8V_STR

MEM_MB_DM[7..0]8,12

MEM_MB_DQS_H88,12

MEM_MB_DQS_L88,12 MEM_MB_DQS_H[7..0]8,12 MEM_MB_DQS_L[7..0]8,12

MEM_MB_DM88,12

3D3V_SYS

GND

MEM_MB_BANK28,12,13 MEM_MB_BANK18,12,13

MEM_MB_ADD[15..0]8,12,13

MEM_MB_BANK08,12,13

MEM_MB_CHECK[7..0]8,12

MEM_MB0_CLK_H08,13 MEM_MB0_CLK_L08,13 MEM_MB0_CLK_H18,13 MEM_MB0_CLK_L18,13 MEM_MB0_CLK_H28,13 MEM_MB0_CLK_L28,13

MEM_MB_CKE08,13 MEM_MB_RAS_L8,12,13

MEM_MB_CAS_L8,12,13 MEM_MB0_CS_L08,13

MEM_MB0_CS_L18,13

121 240

R135

C168

59

*

MEM_M_VREF_SUS

0.1uF

+/-1%

C0603

R0603

R136

R136 59

59

*

0.1uF

+/-1%

C0603

R0603

Layout: Place near DIMM sockets

3

C169

C170

1nF

*

C0603

GND

SMB_MEM_SCL12,18SMB_MEM_SCL12,18 SMB_MEM_SDA12,18

MEM_MB_DM7

MEM_MB_DM6

MEM_MB_DM5

MEM_MB_DM4

MEM_MB_DM3

MEM_MB_DM2

MEM_MB_DM1

MEM_MB_DM0

MEM_MB_DQS_H7 MEM_MB_DQS_L7 MEM_MB_DQS_H6 MEM_MB_DQS_L6 MEM_MB_DQS_H5 MEM_MB_DQS_L5 MEM_MB_DQS_H4 MEM_MB_DQS_L4 MEM_MB_DQS_H3 MEM_MB_DQS_L3 MEM_MB_DQS_H2 MEM_MB_DQS_L2 MEM_MB_DQS_H1 MEM_MB_DQS_L1 MEM_MB_DQS_H0 MEM_MB_DQS_L0

MEM_MB_ADD15 MEM_MB_ADD14 MEM_MB_ADD13 MEM_MB_ADD12 MEM_MB_ADD11 MEM_MB_ADD10 MEM_MB_ADD9 MEM_MB_ADD8 MEM_MB_ADD7 MEM_MB_ADD6 MEM_MB_ADD5 MEM_MB_ADD4 MEM_MB_ADD3 MEM_MB_ADD2 MEM_MB_ADD1 MEM_MB_ADD0

MEM_MB_CHECK6 MEM_MB_CHECK5 MEM_MB_CHECK4 MEM_MB_CHECK3 MEM_MB_CHECK2 MEM_MB_CHECK1 MEM_MB_CHECK0

1

1D8V_STR

172

178

184

187

VDD1

VDD2

VDD3

164

DQS17_H

165

DQS17_L

232

DQS16_H

233

DQS16_L

223

DQS15_H

224

DQS15_L

211

DQS14_H

212

DQS14_L

202

DQS13_H

203

DQS13_L

155

DQS12_H

156

DQS12_L

146

DQS11_H

147

DQS11_L

134

DQS10_H

135

DQS10_L

125

DQS9_H

126

DQS9_L

46

DQS8_H

45

DQS8_L

114

DQS7_H

113

DQS7_L

105

DQS6_H

104

DQS6_L

93

DQS5_H

92

DQS5_L

84

DQS4_H

83

DQS4_L

37

DQS3_H

36

DQS3_L

28

DQS2_H

27

DQS2_L

16

DQS1_H

15

DQS1_L

7

DQS0_H

6

DQS0_L

101

SA2

240

SA1

239

SA0

120

SCL

119

SDA

54

BA2

190

BA1

71

BA0

173

A15

174

A14

196

A13

176

A12

57

A11

70

A10

177

A9

179

A8

58

A7

180

A6

60

A5

61

A4

182

A3

63

A2

183

A1

188

A0

168

CB7

167

CB6

162

CB5

161

CB4

49

CB3

48

CB2

43

CB1

42

CB0

185

CK0_H

186

CK0_L

137

CK1_H

138

CK1_L

220

CK2_H

221

CK2_L

18

RESET_L

52

CKE0

171

CKE1

192

RAS_L

74

CAS_L

193

S0_L

76

S1_L

VDD4

CON_DDR2_240_STD

2

DIMMB0

189

197

64

69

170

175

181

191

194

VDD5

VDD6

VDD753VDD859VDD9

VDD1067VDD11

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ651VDDQ756VDDQ862VDDQ9

DIMM2DIMM2

238

78

72

VDDQ1075VDDQ11

VDDSPD

ERR_OUT_L

DQ63 DQ62 DQ61 DQ60 DQ59 DQ58 DQ57 DQ56 DQ55 DQ54 DQ53 DQ52 DQ51 DQ50 DQ49 DQ48 DQ47 DQ46 DQ45 DQ44 DQ43 DQ42 DQ41 DQ40 DQ39 DQ38 DQ37 DQ36 DQ35 DQ34 DQ33 DQ32 DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10

WE_L VREF

TEST

ODT0 ODT1

PAR_IN

DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

NC1

MEM_MB_DATA63

236

MEM_MB_DATA62

235

MEM_MB_DATA61

230

MEM_MB_DATA60

229

MEM_MB_DATA59

117

MEM_MB_DATA58

116

MEM_MB_DATA57

111

MEM_MB_DATA56

110

MEM_MB_DATA55

227

MEM_MB_DATA54

226

MEM_MB_DATA53

218

MEM_MB_DATA52

217

MEM_MB_DATA51

108

MEM_MB_DATA50

107

MEM_MB_DATA49

99

MEM_MB_DATA48

98

MEM_MB_DATA47

215

MEM_MB_DATA46

214

MEM_MB_DATA45

209

MEM_MB_DATA44

208

MEM_MB_DATA43

96

MEM_MB_DATA42

95

MEM_MB_DATA41

90

MEM_MB_DATA40

89

MEM_MB_DATA39

206

MEM_MB_DATA38

205

MEM_MB_DATA37

200

MEM_MB_DATA36

199

MEM_MB_DATA35

87

MEM_MB_DATA34

86

MEM_MB_DATA33

81

MEM_MB_DATA32

80

MEM_MB_DATA31

159

MEM_MB_DATA30

158

MEM_MB_DATA29

153

MEM_MB_DATA28

152

MEM_MB_DATA27

40

MEM_MB_DATA26

39

MEM_MB_DATA25

34

MEM_MB_DATA24

33

MEM_MB_DATA23

150

MEM_MB_DATA22

149

MEM_MB_DATA21

144

MEM_MB_DATA20

143

MEM_MB_DATA19

31

MEM_MB_DATA18

30

MEM_MB_DATA17

25

MEM_MB_DATA16

24

MEM_MB_DATA15

141

MEM_MB_DATA14

140

MEM_MB_DATA13

132

MEM_MB_DATA12

131

MEM_MB_DATA11

22

MEM_MB_DATA10

21

MEM_MB_DATA9

13

MEM_MB_DATA8

12

MEM_MB_DATA7

129

MEM_MB_DATA6

128

MEM_MB_DATA5

123

MEM_MB_DATA4

122

MEM_MB_DATA3

10

MEM_MB_DATA2

9

MEM_MB_DATA1

4

MEM_MB_DATA0MEM_MB_CHECK7

3 73

MEM_MB_WE_L 8,12,13

1 102 195

77 55

68 19

MEM_M_VREF_SUS

MEM_MB0_ODT0 8,13

GND

240

Title

Document Number Rev

Date: Sheet

Date: Sheet of

DDRII SDRAM DIMM1-2

CK804A07

1

MEM_MB_DATA[63..0] 8,12

120

TECHNOLOGY COPR.

of

11 41Tuesday, October 31, 2006

A

5

4

3

2

SMB_MEM BUS ADDRESS

DIMM 0 DIMM 1 DIMM 2 DIMM 3

1010 000 1010 001 1010 010 1010 011

1

Second Logical DDR2 DIMM

DIMMA1

D D

MEM_MA_DM[7..0]7,11

MEM_MA_DQS_H87,11

MEM_MA_DQS_L87,11 MEM_MA_DQS_H[7..0]7,11 MEM_MA_DQS_L[7..0]7,11

C C

MEM_MA_ADD[15..0]7,11,13

B B

MEM_MA_CHECK[7..0]7,11

MEM_MA_DM87,11

SMB_MEM_SCL11,18 SMB_MEM_SDA11,18

GND

MEM_MA_BANK27,11,13 MEM_MA_BANK17,11,13 MEM_MA_BANK07,11,13

MEM_MA1_CLK_H07,13 MEM_MA1_CLK_L07,13 MEM_MA1_CLK_H17,13 MEM_MA1_CLK_L17,13 MEM_MA1_CLK_H27,13 MEM_MA1_CLK_L27,13

MEM_MA_CKE17,13 MEM_MA_RAS_L7,11,13

MEM_MA_CAS_L7,11,13 MEM_MA1_CS_L07,13

MEM_MA1_CS_L17,13

MEM_MA_DM7

MEM_MA_DM6

MEM_MA_DM5

MEM_MA_DM4

MEM_MA_DM3

MEM_MA_DM2

MEM_MA_DM1

MEM_MA_DM0

MEM_MA_DQS_H7 MEM_MA_DQS_L7 MEM_MA_DQS_H6 MEM_MA_DQS_L6 MEM_MA_DQS_H5 MEM_MA_DQS_L5 MEM_MA_DQS_H4 MEM_MA_DQS_L4 MEM_MA_DQS_H3 MEM_MA_DQS_L3 MEM_MA_DQS_H2 MEM_MA_DQS_L2 MEM_MA_DQS_H1 MEM_MA_DQS_L1 MEM_MA_DQS_H0 MEM_MA_DQS_L0

MEM_MA_ADD15 MEM_MA_ADD14 MEM_MA_ADD13 MEM_MA_ADD12 MEM_MA_ADD11 MEM_MA_ADD10 MEM_MA_ADD9 MEM_MA_ADD8 MEM_MA_ADD7 MEM_MA_ADD6 MEM_MA_ADD5 MEM_MA_ADD4 MEM_MA_ADD3 MEM_MA_ADD2 MEM_MA_ADD1 MEM_MA_ADD0

MEM_MA_CHECK7 MEM_MA_DATA0 MEM_MA_CHECK6 MEM_MA_CHECK5 MEM_MA_CHECK4 MEM_MA_CHECK3 MEM_MA_CHECK2 MEM_MA_CHECK1 MEM_MA_CHECK0

MEM_MA_CKE1 MEM_MB_CKE1

1D8V_STR 1D8V_STR

172

178

184

187

189

197

64

69

170

175

181

191

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD753VDD859VDD9

VDD1067VDD11

VDDQ1

VDDQ2

164

DQS17_H

165

DQS17_L

232

DQS16_H

233

DQS16_L

223

DQS15_H

224

DQS15_L

211

DQS14_H

212

DQS14_L

202

DQS13_H

203

DQS13_L

155

DQS12_H

156

DQS12_L

146

DQS11_H

147

DQS11_L

134

DQS10_H

135

DQS10_L

125

DQS9_H

126

DQS9_L

46

DQS8_H

45

DQS8_L

114

DQS7_H

113

DQS7_L

105

DQS6_H

104

DQS6_L

93

DQS5_H

92

DQS5_L

84

DQS4_H

83

DQS4_L

37

DQS3_H

36

DQS3_L

28

DQS2_H

27

DQS2_L

16

DQS1_H

15

DQS1_L

7

DQS0_H

6

DQS0_L

101

SA2

240

SA1

239

SA0

120

SCL

119

SDA

54

BA2

190

BA1

71

BA0

173

A15

174

A14

196

A13

176

A12

57

A11

70

A10

177

A9

179

A8

58

A7

180

A6

60

A5

61

A4

182

A3

63

A2

183

A1

188

A0

168

CB7

167

CB6

162

CB5

161

CB4

49

CB3

48

CB2

43

CB1

42

CB0

185

CK0_H

186

CK0_L

137

CK1_H

138

CK1_L

220

CK2_H

221

CK2_L

18

RESET_L

52

CKE0

171

CKE1

192

RAS_L

74

CAS_L

193

S0_L

76

S1_L

VDDQ3

3D3V_SYS 3D3V_SYS

DIMM3DIMM3

238

78

194

72

VDDQ4

VDDQ5

VDDQ651VDDQ756VDDQ862VDDQ9

VDDQ1075VDDQ11

VDDSPD

DQ63 DQ62 DQ61 DQ60 DQ59 DQ58 DQ57 DQ56 DQ55 DQ54 DQ53 DQ52 DQ51 DQ50 DQ49 DQ48 DQ47 DQ46 DQ45 DQ44 DQ43 DQ42 DQ41 DQ40 DQ39 DQ38 DQ37 DQ36 DQ35 DQ34 DQ33 DQ32 DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10

WE_L VREF

TEST

ODT0 ODT1

ERR_OUT_L

PAR_IN

MEM_MA_DATA63

236

MEM_MA_DATA62

235

MEM_MA_DATA61

230

MEM_MA_DATA60

229

MEM_MA_DATA59

117

MEM_MA_DATA58

116

MEM_MA_DATA57

111

MEM_MA_DATA56

110

MEM_MA_DATA55

227

MEM_MA_DATA54

226

MEM_MA_DATA53

218

MEM_MA_DATA52

217

MEM_MA_DATA51

108

MEM_MA_DATA50

107

MEM_MA_DATA49

99

MEM_MA_DATA48

98

MEM_MA_DATA47

215

MEM_MA_DATA46

214

MEM_MA_DATA45

209

MEM_MA_DATA44

208

MEM_MA_DATA43

96

MEM_MA_DATA42

95

MEM_MA_DATA41

90

MEM_MA_DATA40

89

MEM_MA_DATA39

206

MEM_MA_DATA38

205

MEM_MA_DATA37

200

MEM_MA_DATA36

199

MEM_MA_DATA35

87

MEM_MA_DATA34

86

MEM_MA_DATA33

81

MEM_MA_DATA32

80

MEM_MA_DATA31

159

MEM_MA_DATA30

158

MEM_MA_DATA29

153

MEM_MA_DATA28

152

MEM_MA_DATA27

40

MEM_MA_DATA26

39

MEM_MA_DATA25

34

MEM_MA_DATA24

33

MEM_MA_DATA23

150

MEM_MA_DATA22

149

MEM_MA_DATA21

144

MEM_MA_DATA20

143

MEM_MA_DATA19

31

MEM_MA_DATA18

30

MEM_MA_DATA17

25

MEM_MA_DATA16

24

MEM_MA_DATA15

141

MEM_MA_DATA14

140

MEM_MA_DATA13

132

MEM_MA_DATA12

131

MEM_MA_DATA11

22

MEM_MA_DATA10

21

MEM_MA_DATA9

13

DQ9

MEM_MA_DATA8

12

DQ8

MEM_MA_DATA7

129

DQ7

MEM_MA_DATA6

128

DQ6

MEM_MA_DATA5

123

DQ5

MEM_MA_DATA4

122

DQ4

MEM_MA_DATA3

10

DQ3

MEM_MA_DATA2

9

DQ2

MEM_MA_DATA1

4

DQ1

3

DQ0

73 1 102 195

77 55

68 19

NC1

MEM_MA_WE_L 7,11,13

MEM_MA1_ODT0 7,13

GND

MEM_MA_DATA[63..0] 7,11

MEM_MB_DM[7..0]8,11

MEM_MB_DQS_H88,11

MEM_MB_DQS_L88,11 MEM_MB_DQS_H[7..0]8,11 MEM_MB_DQS_L[7..0]8,11

MEM_MB_DM88,11

3D3V_SYS3D3V_SYS

SMB_MEM_SCL11,18

GND

SMB_MEM_SDA11,18 MEM_MB_BANK28,11,13 MEM_MB_BANK18,11,13

MEM_MB_ADD[15..0]8,11,13

MEM_MB_BANK08,11,13

MEM_MB_CHECK[7..0]8,11

MEM_M_VREF_SUS MEM_M_VREF_SUS

MEM_MB1_CLK_H08,13 MEM_MB1_CLK_L08,13 MEM_MB1_CLK_H18,13 MEM_MB1_CLK_L18,13 MEM_MB1_CLK_H28,13 MEM_MB1_CLK_L28,13

MEM_MB_CKE18,13 MEM_MB_RAS_L8,11,13

MEM_MB_CAS_L8,11,13 MEM_MB1_CS_L08,13

MEM_MB1_CS_L18,13

MEM_MB_DM7

MEM_MB_DM6

MEM_MB_DM5

MEM_MB_DM4

MEM_MB_DM3

MEM_MB_DM2

MEM_MB_DM1

MEM_MB_DM0

MEM_MB_DQS_H7 MEM_MB_DQS_L7 MEM_MB_DQS_H6 MEM_MB_DQS_L6 MEM_MB_DQS_H5 MEM_MB_DQS_L5 MEM_MB_DQS_H4 MEM_MB_DQS_L4 MEM_MB_DQS_H3 MEM_MB_DQS_L3 MEM_MB_DQS_H2 MEM_MB_DQS_L2 MEM_MB_DQS_H1 MEM_MB_DQS_L1 MEM_MB_DQS_H0 MEM_MB_DQS_L0

MEM_MB_ADD15 MEM_MB_ADD14 MEM_MB_ADD13 MEM_MB_ADD12 MEM_MB_ADD11 MEM_MB_ADD10 MEM_MB_ADD9 MEM_MB_ADD8 MEM_MB_ADD7 MEM_MB_ADD6 MEM_MB_ADD5 MEM_MB_ADD4 MEM_MB_ADD3 MEM_MB_ADD2 MEM_MB_ADD1 MEM_MB_ADD0

MEM_MB_CHECK7 MEM_MB_CHECK6 MEM_MB_CHECK5 MEM_MB_CHECK4 MEM_MB_CHECK3 MEM_MB_CHECK2 MEM_MB_CHECK1 MEM_MB_CHECK0

164

DQS17_H

165

DQS17_L

232

DQS16_H

233

DQS16_L

223

DQS15_H

224

DQS15_L

211

DQS14_H

212

DQS14_L

202

DQS13_H

203

DQS13_L

155

DQS12_H

156

DQS12_L

146

DQS11_H

147

DQS11_L

134

DQS10_H

135

DQS10_L

125

DQS9_H

126

DQS9_L

46

DQS8_H

45

DQS8_L

114

DQS7_H

113

DQS7_L

105

DQS6_H

104

DQS6_L

93

DQS5_H

92

DQS5_L

84

DQS4_H

83

DQS4_L

37

DQS3_H

36

DQS3_L

28

DQS2_H

27

DQS2_L

16

DQS1_H

15

DQS1_L

7

DQS0_H

6

DQS0_L

101

SA2

240

SA1

239

SA0

120

SCL

119

SDA

54

BA2

190

BA1

71

BA0

173

A15

174

A14

196

A13

176

A12

57

A11

70

A10

177

A9

179

A8

58

A7

180

A6

60

A5

61

A4

182

A3

63

A2

183

A1

188

A0

168

CB7

167

CB6

162

CB5

161

CB4

49

CB3

48

CB2

43

CB1

42

CB0

185

CK0_H

186

CK0_L

137

CK1_H

138

CK1_L

220

CK2_H

221

CK2_L

18

RESET_L

52

CKE0

171

CKE1

192

RAS_L

74

CAS_L

193

S0_L

76

S1_L

121

DIMMB1

172

178

184

187

189

197

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD753VDD859VDD9

64

69

170

175

181

191

194

VDD1067VDD11

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ651VDDQ756VDDQ862VDDQ9

CON_DDR2_240_STD

72

78

VDDQ1075VDDQ11

ERR_OUT_L

DIMM4DIMM4

238

VDDSPD

DQ63 DQ62 DQ61 DQ60 DQ59 DQ58 DQ57 DQ56 DQ55 DQ54 DQ53 DQ52 DQ51 DQ50 DQ49 DQ48 DQ47 DQ46 DQ45 DQ44 DQ43 DQ42 DQ41 DQ40 DQ39 DQ38 DQ37 DQ36 DQ35 DQ34 DQ33 DQ32 DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10

WE_L VREF

TEST

ODT0 ODT1

PAR_IN

MEM_MB_DATA63

236

MEM_MB_DATA62

235

MEM_MB_DATA61

230

MEM_MB_DATA60

229

MEM_MB_DATA59

117

MEM_MB_DATA58

116

MEM_MB_DATA57

111

MEM_MB_DATA56

110

MEM_MB_DATA55

227

MEM_MB_DATA54

226

MEM_MB_DATA53

218

MEM_MB_DATA52

217

MEM_MB_DATA51

108

MEM_MB_DATA50

107

MEM_MB_DATA49

99

MEM_MB_DATA48

98

MEM_MB_DATA47

215

MEM_MB_DATA46

214

MEM_MB_DATA45

209

MEM_MB_DATA44

208

MEM_MB_DATA43

96

MEM_MB_DATA42

95

MEM_MB_DATA41

90

MEM_MB_DATA40

89

MEM_MB_DATA39

206

MEM_MB_DATA38

205

MEM_MB_DATA37

200

MEM_MB_DATA36

199

MEM_MB_DATA35

87

MEM_MB_DATA34

86

MEM_MB_DATA33

81

MEM_MB_DATA32

80

MEM_MB_DATA31

159

MEM_MB_DATA30

158

MEM_MB_DATA29

153

MEM_MB_DATA28

152

MEM_MB_DATA27

40

MEM_MB_DATA26

39

MEM_MB_DATA25

34

MEM_MB_DATA24

33

MEM_MB_DATA23

150

MEM_MB_DATA22

149

MEM_MB_DATA21

144

MEM_MB_DATA20

143

MEM_MB_DATA19

31

MEM_MB_DATA18

30

MEM_MB_DATA17

25

MEM_MB_DATA16

24

MEM_MB_DATA15

141

MEM_MB_DATA14

140

MEM_MB_DATA13

132

MEM_MB_DATA12

131

MEM_MB_DATA11

22

MEM_MB_DATA10

21

MEM_MB_DATA9

13

DQ9

MEM_MB_DATA8

12

DQ8

MEM_MB_DATA7

129

DQ7

MEM_MB_DATA6

128

DQ6

MEM_MB_DATA5

123

DQ5

MEM_MB_DATA4

122

DQ4

MEM_MB_DATA3

10

DQ3

MEM_MB_DATA2

9

DQ2

MEM_MB_DATA1

4

DQ1

MEM_MB_DATA0

3

DQ0

73 1 102 195

77 55

68 19

NC1

MEM_MB_WE_L 8,11,13

MEM_MB1_ODT0 8,13

GND

MEM_MB_DATA[63..0] 8,11

240

1

A A

Title

Document Number Rev

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

DDRII SDRAM DIMM3-4

CK804A07

120

TECHNOLOGY COPR.

A

of

12 41Tuesday, October 31, 2006

1

12 41Tuesday, October 31, 2006

5

MEM_MA_ADD[15..0]7,11,12

D D

MEM_MA_ADD[15..0]

MEM_MA_CAS_L7,11,12 MEM_MA_WE_L7,11,12 MEM_MA_RAS_L7,11,12

MEM_MA_BANK27,11,12 MEM_MA_BANK17,11,12 MEM_MA_BANK07,11,12

MEM_MA_CKE17,12 MEM_MA_CKE07,11

MEM_MA0_CS_L17,11 MEM_MA0_CS_L07,11 MEM_MA0_ODT07,11

MEM_MA1_CS_L17,12 MEM_MA1_CS_L07,12 MEM_MA1_ODT07,12

MEM_MA_ADD15 MEM_MA_ADD14 MEM_MA_ADD13 MEM_MA_ADD12 MEM_MA_ADD11 MEM_MA_ADD10 MEM_MA_ADD9 MEM_MA_ADD8 MEM_MA_ADD7 MEM_MA_ADD6 MEM_MA_ADD5 MEM_MA_ADD4 MEM_MA_ADD3 MEM_MA_ADD2 MEM_MA_ADD1 MEM_MA_ADD0

4

MEM_MB_CAS_L MEM_MA_CAS_L MEM_MB0_ODT0 MEM_MA0_ODT0

MEM_MB_CKE0 MEM_MA_CKE1 MEM_MA_ADD14 MEM_MA_CKE0

MEM_MB_BANK0 MEM_MA1_CS_L0 MEM_MA0_CS_L0 MEM_MB_RAS_L

MEM_MB1_CS_L1 MEM_MA1_CS_L1 MEM_MA0_CS_L1 MEM_MB0_CS_L1

RN2

*

1 3 5 7 8

47 Ohm

+/-5%

8p4r0402h5

RN4

*

1 3 5 7 8

47 Ohm

+/-5%

8p4r0402h5

RN6

*

1 3 5 7 8

47 Ohm

+/-5%

8p4r0402h5

RN46

*

1 3 5 7 8

47 Ohm

+/-5%

8p4r0402h5

3

VTT_DDR VTT_DDR

RN3

2 4 6

MEM_MB1_ODT0 MEM_MA1_ODT0 MEM_MB_ADD13 MEM_MA_ADD13

MEM_MB_BANK1 MEM_MA_BANK0 MEM_MB_ADD10 MEM_MA_RAS_L

MEM_MB1_CS_L0 MEM_MA_WE_L MEM_MB_WE_L MEM_MB0_CS_L0

RN3

*

47 Ohm

+/-5%

8p4r0402h5

RN5

*

47 Ohm

+/-5%

8p4r0402h5

RN7

*

47 Ohm

+/-5%

8p4r0402h5

1 3 5 7 8

2

MEM_MA0_CLK_H27,11

MEM_MA0_CLK_L27,11

2 4 6

MEM_MA0_CLK_H17,11

MEM_MA0_CLK_L17,11

MEM_MA0_CLK_H07,11

MEM_MA0_CLK_L07,11

MEM_MB0_CLK_H28,11

MEM_MB0_CLK_L28,11

MEM_MB0_CLK_H18,11

MEM_MB0_CLK_L18,11

MEM_MB0_CLK_H08,11

MEM_MB0_CLK_L08,11

C171

1.5pF

*

50V, NPO, +/-0.25pF

C0603

C172

1.5pF

*

50V, NPO, +/-0.25pF

C0603

C173

1.5pF

*

50V, NPO, +/-0.25pF

C0603

C174

1.5pF

*

50V, NPO, +/-0.25pF

C0603

C175

1.5pF

*

50V, NPO, +/-0.25pF

C0603

C176

1.5pF

*

50V, NPO, +/-0.25pF

C0603

1

DDR2 Termination

C C

B B

A A

MEM_MB_ADD[15..0]8,11,12

MEM_MB_CAS_L8,11,12 MEM_MB_WE_L8,11,12 MEM_MB_RAS_L8,11,12

MEM_MB_BANK28,11,12 MEM_MB_BANK18,11,12 MEM_MB_BANK08,11,12

MEM_MB_CKE18,12 MEM_MB_CKE08,11

MEM_MB0_CS_L18,11 MEM_MB0_CS_L08,11 MEM_MB0_ODT08,11

MEM_MB1_CS_L18,12 MEM_MB1_CS_L08,12 MEM_MB1_ODT08,12

VTT_DDR

MEM_MB_ADD15 MEM_MB_ADD14 MEM_MB_ADD13 MEM_MB_ADD12 MEM_MB_ADD11 MEM_MB_ADD10 MEM_MB_ADD9 MEM_MB_ADD8 MEM_MB_ADD7 MEM_MB_ADD6 MEM_MB_ADD5 MEM_MB_ADD4 MEM_MB_ADD3 MEM_MB_ADD2 MEM_MB_ADD1 MEM_MB_ADD0

MEM_MB_ADD1 MEM_MA_ADD1 MEM_MB_ADD2 MEM_MA_ADD2

MEM_MB_ADD5 MEM_MB_ADD7 MEM_MB_ADD8 MEM_MA_ADD4

MEM_MA_ADD9 MEM_MB_ADD14 MEM_MA_ADD11 MEM_MB_BANK2

MEM_MA_BANK2 MEM_MA_ADD15 MEM_MB_CKE1 MEM_MB_ADD15

*

Layout: Spread out on VTT pour

C193

*

C191

0.1uF

C0603

C239

0.1uF

C0603

*

C192

*

0.1uF

C0603

50V, Y5V, +80%/-20%

C240

*

0.1uF

C0603

C194

C195

*

0.1uF

C0603

0.1uF

C0603

50V, Y5V, +80%/-20%

C243

C242

C241

*

0.1uF

C0603

0.1uF

C0603

0.1uF

C0603

C190

C189

C184

C183

*

0.1uF

C0603

50V, Y5V, +80%/-20%

C231

C232

*

0.1uF

C0603

C186

C185

*

0.1uF

C0603

50V, Y5V, +80%/-20%

C233

*

0.1uF

C0603

C187

*

0.1uF

C0603

50V, Y5V, +80%/-20%

C234

C235

*

0.1uF

C0603

C189

C188

*

0.1uF

C0603

50V, Y5V, +80%/-20%

C236

*

0.1uF

C0603

0.1uF

C0603

C237

0.1uF

C0603

*

0.1uF

C0603

50V, Y5V, +80%/-20%

C238

*

0.1uF

C0603

VTT_DDR VTT_DDR

RN8

1 3 5 7 8

47 Ohm

+/-5%

8p4r0402h5

RN10

1 3 5 7 8

47 Ohm

+/-5%

8p4r0402h5

RN12

1 3 5 7 8

47 Ohm

+/-5%

8p4r0402h5

RN14

1 3 5 7 8

47 Ohm

+/-5%

8p4r0402h5

C196

*

0.1uF

C0603

C244

*

0.1uF

C0603

2 4 6

C197

*

0.1uF

C0603

50V, Y5V, +80%/-20%

C245

*

0.1uF

C0603

*

GND

*

C198

0.1uF

C0603

50V, Y5V, +80%/-20%

1D8V_STR

C246

0.1uF

C0603

MEM_MB_ADD6 MEM_MA_ADD3 MEM_MB_ADD4 MEM_MB_ADD3

MEM_MA_ADD6 MEM_MB_ADD9 MEM_MA_ADD5 MEM_MB_ADD11

MEM_MA_ADD10 MEM_MB_ADD0 MEM_MA_ADD0 MEM_MA_BANK1

MEM_MA_ADD7 MEM_MA_ADD12 MEM_MA_ADD8 MEM_MB_ADD12

MEM_MA_ADD15 MEM_MA_ADD14 MEM_MA_ADD13 MEM_MA_ADD12 MEM_MA_ADD11 MEM_MA_ADD10 MEM_MA_ADD9 MEM_MA_ADD8 MEM_MA_ADD7 MEM_MA_ADD6 MEM_MA_ADD5 MEM_MA_ADD4 MEM_MA_ADD3 MEM_MA_ADD2 MEM_MA_ADD1 MEM_MA_ADD0

MEM_MA_CAS_L MEM_MA_WE_L MEM_MA_RAS_L

MEM_MA_BANK2 MEM_MA_BANK1 MEM_MA_BANK0

RN9

*

1

2

3

4

5

6

7 8

47 Ohm

+/-5%

8p4r0402h5

RN11

*

1

2

3

4

5

6

7 8

47 Ohm

+/-5%

8p4r0402h5

RN13

*

1

2

3

4

5

6

7 8

47 Ohm

+/-5%

8p4r0402h5

RN15

*

1

2

3

4

5

6

7 8

47 Ohm

+/-5%

8p4r0402h5

*

C200 22pF C0603

*

C199 22pF C0603

*

C202 22pF C0603

*

C201 22pF C0603

*

C204 22pF C0603

*

C206 22pF C0603

*

C208 22pF C0603

*

C210 22pF C0603

*

C209 22pF C0603

*

C211 22pF C0603

*

C219 22pF C0603

*

C223 22pF C0603

*

C218 22pF C0603

*

C224 22pF C0603

*

C222 22pF C0603

*

C226 22pF C0603

*

C227 22pF C0603

*

C247 22pF C0603

*

C249 22pF C0603

*

C248 22pF C0603

*

C253 22pF C0603

*

C254 22pF C0603

MEM_MA1_CLK_H27,12

MEM_MA1_CLK_L27,12

MEM_MA1_CLK_H17,12

MEM_MA1_CLK_L17,12

MEM_MA1_CLK_H07,12

MEM_MA1_CLK_L07,12

MEM_MB1_CLK_H28,12

MEM_MB1_CLK_L28,12

MEM_MB1_CLK_H18,12

MEM_MB1_CLK_L18,12

MEM_MB1_CLK_H08,12

MEM_MB1_CLK_L08,12

1D8V_STR 1D8V_STR

MEM_MB_ADD15 MEM_MB_ADD14 MEM_MB_ADD13 MEM_MB_ADD12 MEM_MB_ADD11 MEM_MB_ADD10 MEM_MB_ADD9 MEM_MB_ADD8 MEM_MB_ADD7 MEM_MB_ADD6 MEM_MB_ADD5 MEM_MB_ADD4 MEM_MB_ADD3 MEM_MB_ADD2 MEM_MB_ADD1 MEM_MB_ADD0

MEM_MB_CAS_L MEM_MB_WE_L MEM_MB_RAS_L

MEM_MB_BANK2 MEM_MB_BANK1 MEM_MB_BANK0

*

C203 22pF C0603

*

C205 22pF C0603

*

C207 22pF C0603

*

C213 22pF C0603

*

C214 22pF C0603

*

C215 22pF C0603

*

C212 22pF C0603

*

C216 22pF C0603

*

C217 22pF C0603

*

C220 22pF C0603

*

C221 22pF C0603

*

C225 22pF C0603

*

C230 22pF C0603

*

C229 22pF C0603

*

C228 22pF C0603

*

C251 22pF C0603

*

C252 22pF C0603

*

C250 22pF C0603

*

C257 22pF C0603

*

C255 22pF C0603

*

C256 22pF C0603

*

C258 22pF C0603

C177

1.5pF

*

50V, NPO, +/-0.25pF

C0603

C178

1.5pF

*

50V, NPO, +/-0.25pF

C0603

C179

1.5pF

*

50V, NPO, +/-0.25pF

C0603

C180

1.5pF

*

50V, NPO, +/-0.25pF

C0603

C181

1.5pF

*

50V, NPO, +/-0.25pF

C0603

C182

1.5pF

*

50V, NPO, +/-0.25pF

C0603

TECHNOLOGY COPR.

Title

50V, Y5V, +80%/-20%

5

50V, Y5V, +80%/-20%

4

50V, Y5V, +80%/-20%

3

2

Title

Document Number Rev

Date: Sheet

Date: Sheet of

DDR Terminator

CK804A07

1

TECHNOLOGY COPR.

of

13 41Tuesday, October 31, 2006

A

5

HT_DWN[15..0]6

D D

HT_DWN*[15..0]6

C C

HT_DWNCLK06 HT_DWNCLK0*6

R141

10K

+/-5%

r0603h6

HT_DWNCLK16 HT_DWNCLK1*6

HT_DWNCNTL6 HT_DWNCNTL*6

U6_1

3D3V_SYS

HT_STOP*9

FAB B change

Heatsink

SLP_S5*

*

37

3.3V_PLL_HT

C261

0.1uF

+/-10%

c0603h10

*

B B

3D3V_SYS

C259

0.1uF

*

+/-10%

c0603h10

FB2

*

FB L0805 70 Ohm

C260

10uF

*

6.3V, X5R, +/-10%

C1206

Dummy

HT_VLD39 CPU_VLD36

r0603h6 +/-5%

HTVDD_EN38 CPUVDD_EN36

C262

10nF

50V, X7R, +/-10%

C0603

4

R721 100

Dummy

HT_DWN[15..0]

HT_DWN*[15..0]

HT_DWNCLK0 HT_DWNCLK0* HT_DWNCLK1 HT_DWNCLK1*

HT_DWNCNTL HT_DWNCNTL*

HT_REQ* HT_STOP*

HT_VLD CPU_VLD

MEM_VLD HTVDD_EN

CPUVDD_EN

R142

49.9

+/-1%

r0603h6

HT_DWN0

0

HT_DWN1

1

HT_DWN2

2

HT_DWN3

3

HT_DWN4

4

HT_DWN5

5

HT_DWN6

HT_DWN7

7

HT_DWN8

8

HT_DWN9

9

HT_DWN10

10

HT_DWN11

11

HT_DWN12

12

HT_DWN13

13

HT_DWN14

14

HT_DWN15

15

HT_DWN*0

0

HT_DWN*1

1

HT_DWN*2

2

HT_DWN*3

3

HT_DWN*4

4

HT_DWN*5

5

HT_DWN*6

6

HT_DWN*7

7

HT_DWN*8

8

HT_DWN*9

9

HT_DWN*10

10

HT_DWN*11

11

HT_DWN*12

12

HT_DWN*13

13

HT_DWN*14

14 15

HT_COMP1

R143 150R143 150

AG30 AF30 AE29 AD27 AC29 AB30 AA30 AA28 AE26 AD26 AC24 AC26 AB26

Y22 Y24 Y26

AG29 AF29 AE28 AD28 AB28 AB29 AA29 AA27 AF26 AD25 AD24 AC25 AB25 AA22

Y23 Y25

AC27 AC28 AB24 AB23

Y28

W27

M22 N22

AF27 AF28

AK5

AJ4 AK4 AE3 AD3

AG28

AG27

U6A

HT_RXD0 HT_RXD1 HT_RXD2 HT_RXD3 HT_RXD4 HT_RXD5 HT_RXD6 HT_RXD7 HT_RXD8 HT_RXD9 HT_RXD10 HT_RXD11 HT_RXD12 HT_RXD13 HT_RXD14 HT_RXD15

HT_RXD0* HT_RXD1* HT_RXD2* HT_RXD3* HT_RXD4* HT_RXD5* HT_RXD6* HT_RXD7* HT_RXD8* HT_RXD9* HT_RXD10* HT_RXD11* HT_RXD12* HT_RXD13* HT_RXD14* HT_RXD15*

HT_RX_CLK0 HT_RX_CLK0* HT_RX_CLK1 HT_RX_CLK1*

HT_RXCTL HT_RXCTL*

HT_REQ*/GPIO HT_STOP*

HT_CAL_GND1 HT_CAL_GND2

HT_VLD CPU_VLD MEM_VLD HTVDD_EN CPUVDD_EN

+3.3V_PLL_HT

+3.3V_PLL_CPU

NF4-4X-B1

3

HT_UP0

0

N27

HT_TXD0 HT_TXD1 HT_TXD2 HT_TXD3 HT_TXD4 HT_TXD5 HT_TXD6 HT_TXD7 HT_TXD8

HT_TXD9 HT_TXD10 HT_TXD11 HT_TXD12 HT_TXD13 HT_TXD14 HT_TXD15

HT_TXD0* HT_TXD1* HT_TXD2* HT_TXD3* HT_TXD4* HT_TXD5* HT_TXD6* HT_TXD7* HT_TXD8*

HT_TXD9* HT_TXD10* HT_TXD11* HT_TXD12* HT_TXD13* HT_TXD14* HT_TXD15*

HT_TX_CLK0

HT_TX_CLK0*

HT_TX_CLK1

HT_TX_CLK1*

HT_TXCTL

HT_TXCTL*

CPU_CLK

CPU_CLK*

CPU_CLK_66

CPU_PWROK

CPU_RST*

THERMTRIP*/GPIO

CPU_COMP

TCK

TDO TMS

TRST*

N29 P29 P28 T28 U28 U30 V29 P25 P26 P22 T25 U22 V26 V24 V22

N28 N30 P30 R29 U27 U29 V30 V28 P24 N26 P23 T26 T22 U26 V25 V23

R28 R27 T23 T24

W29 W28

L28 L29

L27 M26 M28 AF25 M25

AD5 AC6

TDI

AB6 AC3 AC5

HT_UP1

1

HT_UP2

2

HT_UP3

3

HT_UP4

4

HT_UP5

5

HT_UP6

66

HT_UP7

7

HT_UP8

8

HT_UP9

9

HT_UP10

10

HT_UP11

11

HT_UP12

12

HT_UP13

13

HT_UP14

14

HT_UP15

15

HT_UP*0

0

HT_UP*1

1

HT_UP*2

2

HT_UP*3

3

HT_UP*4

4

HT_UP*5

5

HT_UP*6

6

HT_UP*7

7

HT_UP*8

8

HT_UP*9

9

HT_UP*10

10

HT_UP*11

11

HT_UP*12

12

HT_UP*13

13

HT_UP*14

14

HT_UP*15HT_DWN*15

15

HT_UPCLK0 HT_UPCLK0* HT_UPCLK1 HT_UPCLK1*

HT_UPCNTL HT_UPCNTL*

CPU_CLK CPU_CLK*

TP_CPU_CLK_66

CPU_PWRGD CPU_RST* CPU_THERMTRIP*

CPU_COMP

CK8_TCK CK8_TDI

CK8_TDO CK8_TMS

CK8_TRST*

2

HT_UP[15..0]

HT_UP*[15..0]

1

R144 549R144 549

R145 10K +/-5%R145 10K +/-5%

1

R147 10K

TP35TP35

TP36TP36

R148 10K +/-5%R148 10K +/-5%

+/-5%

HT_UP[15..0] 6

HT_UP*[15..0] 6

HT_UPCLK0 6 HT_UPCLK0* 6 HT_UPCLK1 6 HT_UPCLK1* 6

HT_UPCNTL 6 HT_UPCNTL* 6

CPU_CLKIN_H 9 CPU_CLKIN_L 9

CPU_PWRGD 9 CPU_RST* 9 CPU_THERMTRIP* 9

R146 10K +/-5%R146 10K +/-5%

1

3D3V_SYS

*

A A

C263

0.1uF

+/-10%

c0603h10

FB3

*

FB L0805 70 Ohm

5

C264

10uF

*

6.3V, X5R, +/-10%

C1206

Dummy

*

3.3V_PLL_CPU

C265

0.1uF

+/-10%

c0603h10

C266

10nF

*

50V, X7R, +/-10%

C0603

1D8V_STR

5V_SB_SYS 3D3V_DUAL

R722

10K

+/-5%

FAB B change

R724

C760

0.1uF

1K

r0603h6

+-5%

4

0.1uF

*

50V, Y5V, +80%/-20%

C0603

Dummy

+/-5%

r0603h6

Q81

B

PMBT3904

E C

3

R723

10K

+/-5%

r0603h6

DS

Q82

G

2N7002-7-F

MEM_VLD

C761

0.1uF

*

50V, Y5V, +80%/-20%

C0603

Dummy

TECHNOLOGY COPR.

Title

Document Number Rev

Date: Sheet

2

Date: Sheet

CK804 HT

CK804A07

TECHNOLOGY COPR.

of

14 41Tuesday, October 31, 2006

of

14 41Tuesday, October 31, 2006

of

14 41Tuesday, October 31, 2006

1

A

5

D D

PE0_IN[15..0]20

PE0_IN*[15..0]20

C C

PE0_PRSNT*20

PE1_IN21 PE1_IN*21

3D3V_DUAL

*

C310

0.1uF

*

+/-10%

c0603h10

R163

10K

+/-5%

r0603h6

C305

0.1uF

+/-10%

c0603h10

PE1_PRSNT*21

PE2_IN21 PE2_IN*21

PE2_PRSNT*21

PE_RESET*20,21

*

3D3V_SYS

R159

10K

+/-5%

r0603h6

R162

10K

+/-5%

r0603h6

Dummy

C303

0.1uF

+/-10%

c0603h10

FB4

*

PE_WAKE*

FB L0805 70 Ohm

C304

10uF

*

6.3V, X5R, +/-10%

C1206

1D5V_CORE

C309

10uF

*

6.3V, X5R, +/-10%

C1206

Dummy

B B

PE_WAKE*20,21

1D5V_CORE

*

TP38TP38 TP37TP37

C306

10nF

*

50V, X7R, +/-10%

C0603

C311

10nF

50V, X7R, +/-10%

C0603

@BOTTOM

4

PE0_IN[15..0]

PE0_IN*[15..0]

PE0_PRSNT*

PE1_IN PE1_IN*

PE1_PRSNT*

PE2_IN PE2_IN*

PE2_PRSNT*

PE_RESET*

1.5V_PLL_PE

3

U6B

PE0_IN0

0

H18

PE0_IN1

1 1

PE0_IN2

2

PE0_IN3

3

PE0_IN4

4

PE0_IN5

5

PE0_IN6

6

PE0_IN7

7

PE0_IN8

PE0_IN9

9

PE0_IN10

10

PE0_IN11

11

PE0_IN12

12

PE0_IN13

13

PE0_IN14

14

PE0_IN15

15

PE0_IN*0

0

PE0_IN*1

1

PE0_IN*2

2

PE0_IN*3

3

PE0_IN*4

4

PE0_IN*5

5

PE0_IN*6

6 6

PE0_IN*7

7

PE0_IN*8

8

PE0_IN*9

9

PE0_IN*10 PE_TX10*

10

PE0_IN*11

11

PE0_IN*12

12

PE0_IN*13

13

PE0_IN*14

14

PE0_IN*15

15

PE3_PRSNT*

TP_PE4_IN

1

TP_PE4_IN*

1

PE0_RX0

F18

PE0_RX1

J18

PE0_RX2

H16

PE0_RX3

E16

PE0_RX4

D14

PE0_RX5

J16

PE0_RX6

H14

PE0_RX7

E13

PE0_RX8

H12

PE0_RX9

E12

PE0_RX10

J11

PE0_RX11

D10

PE0_RX12

H10

PE0_RX13

F10

PE0_RX14

E8

PE0_RX15

G18

PE0_RX0*

E17

PE0_RX1*

J17

PE0_RX2*

G16

PE0_RX3*

F16

PE0_RX4*

E14

PE0_RX5*

J15

PE0_RX6*

G14

PE0_RX7*

F14

PE0_RX8*

G12

PE0_RX9*

F12

PE0_RX10*

J10

PE0_RX11*

E10

PE0_RX12*

G10

PE0_RX13*

E9

PE0_RX14*

F8

PE0_RX15*

D22

PE0_PRSNT*

D18

PE1_RX

E18

PE1_RX*

G22

PE1_PRSNT*

F20

PE2_RX

E20

PE2_RX*

F22

PE2_PRSNT*

H20

PE3_RX

G20

PE3_RX*

E21

PE3_PRSNT*

K19

PE4_RX

J19

PE4_RX*

E22

PE_RST*

E23

PE_WAKE*

A27

+1.5V_PLL_PE_AVDD

A28

+1.5V_PLL_PE_DVDD

B28

+1.5V_PLL_PE_CORE

A26

GND_PLL_PE

NF4-4X-B1

PE_REFCLKIN*

PE_CLK_TEST*

PECLK_COMP_GND

+3.3V_PLL_PE_CORE

PE0_TX0 PE0_TX1 PE0_TX2 PE0_TX3 PE0_TX4 PE0_TX5 PE0_TX6 PE0_TX7 PE0_TX8

PE0_TX9 PE0_TX10 PE0_TX11 PE0_TX12 PE0_TX13 PE0_TX14 PE0_TX15

PE0_TX0* PE0_TX1* PE0_TX2* PE0_TX3* PE0_TX4* PE0_TX5* PE0_TX6* PE0_TX7* PE0_TX8* PE0_TX9*

PE0_TX10* PE0_TX11* PE0_TX12* PE0_TX13* PE0_TX14* PE0_TX15*

PE0_REFCLK

PE0_REFCLK*

PE1_TX

PE1_TX*

PE1_REFCLK

PE1_REFCLK*

PE2_TX

PE2_TX*

PE2_REFCLK

PE2_REFCLK*

PE3_TX

PE3_TX*

PE3_REFCLK

PE3_REFCLK*

PE4_TX

PE4_TX*

PE_REFCLKIN

PE_CLK_TEST

A18 A17 C17 C16 C15 C14 A14 B13 D13 D11 B11 B10 B9 C9 C8 C7

B18 B17 D17 D15 B15 B14 A13 C13 C12 C11 C10 A10 A9 D9 D8 B7

PE0CLK

B19

PE0CLK*

C18

PE1_TX

D19

PE1_TXJ

C19

PE1CLK

D21

PE1CLKJ

C20

PE2_TX

B21

PE2_TXJ

C21

PE2CLK

C24

PE2CLK*

D23 C22

B22 C23

B23

A22 A21

A25 B25

C25 D24

E24

+3.3V_PLL_PE_CORE

B26

PLACE AT CONNECTOR

C267

0.1uF C0402

R149 33R149 33

R153 33R153 33

R157 33R157 33

@BOTTOM

C307

0.1uF

*

+/-10%

c0603h10

C267

C268

0.1uF C0402

*

C269

C271

0.1uF C0402

*

C272

C274

0.1uF C0402

*

C275

C277

0.1uF C0402

*

C278

C280

0.1uF C0402

*

C281

*

C283

C284

0.1uF C0402

*

C285

C287

0.1uF C0402

*

C288

C290

0.1uF C0402

*

C291

PE0_OUT*9 PE0_OUT*9

C293

0.1uF C0402

*

C294

C296

0.1uF C0402

*

C297

*

R151 33R151 33

R155 33R155 33

R160 33R160 33

TP41TP41

1

TP42TP42

1

TP44TP44

1

TP43TP43

1

R164

499

+/-1%

r0603h6

C308

4.7uF

*

6.3V, X5R, +/-10%

C0805

Dummy

PE_TX0 PE_TX1 PE_TX2 PE0_OUT2 PE_TX3 PE_TX4 PE_TX5 PE_TX6 PE_TX7 PE_TX8 PE_TX9 PE_TX10 PE_TX11 PE_TX12 PE_TX13 PE_TX14 PE_TX15

PE_TX0* PE_TX1* PE_TX2* PE_TX3* PE_TX4* PE_TX5* PE_TX6* PE_TX7* PE_TX8* PE_TX9*

PE_TX11* PE_TX12* PE_TX13* PE_TX14* PE_TX15*

TP_PE4_TX TP_PE4_TX*

TP_PE_REFCLK_C TP_PE_REFCLK_C*

TP_PECLK_TEST TP_PECLK_TEST*

PE_COMP

C270

0.1uF C0402

*

C273

0.1uF C0402

*

C276

0.1uF C0402

*

C279

0.1uF C0402

*

C282

0.1uF C0402

*

C286

0.1uF C0402

*

C289

0.1uF C0402

*

C292

0.1uF C0402

*

C295

0.1uF C0402

*

C298

0.1uF C0402

*

R150 40.2R150 40.2

R152 40.2R152 40.2

R154 40.2R154 40.2

R156 40.2R156 40.2

R158 40.2R158 40.2

R161 40.2R161 40.2

TP40TP40

1

TP39TP39

1

A01:137ohm A02:499ohm

FB5

FB L0805 70 Ohm

*

PE0_OUT*0

PE0_OUT*3

PE0_OUT*6

PE0_OUT*12

PE0_OUT*15

3D3V_SYS

PE0_OUT[15..0]

PE0_OUT0

0

PE0_OUT1

2

PE0_OUT3

3

PE0_OUT4

4

PE0_OUT5

5

PE0_OUT6

6

PE0_OUT7

7

PE0_OUT8

88

PE0_OUT9

9

PE0_OUT10

10

PE0_OUT11

11

PE0_OUT12

12

PE0_OUT13

13

PE0_OUT14

14

PE0_OUT15

15

PE0_OUT*[15..0]

0

PE0_OUT*1

1

PE0_OUT*2

2 3

PE0_OUT*4

4

PE0_OUT*5

5

PE0_OUT*7

7

PE0_OUT*8

8 9

PE0_OUT*10

10

PE0_OUT*11

11 12

PE0_OUT*13

13

PE0_OUT*14

14 15

0.1uF C0402

A01:49.9ohm A02:40.2ohm

C299

C301

*

2

PE0_OUT[15..0] 20

PE0_OUT*[15..0] 20

C300

0.1uF C0402

*

C302

0.1uF C0402

*

PLACE 0 OHM RES AT CONNECTOR SHARE PAD WITH CLOCK GEN 0 OHM

PE0_REFCLK 20 PE0_REFCLK* 20

PE1_OUT 21 PE1_OUT* 21

PE1_REFCLK 21 PE1_REFCLK* 21

PE2_OUT 21 PE2_OUT* 21

PE2_REFCLK 21 PE2_REFCLK* 21

1

A A

TECHNOLOGY COPR.

Title

Document Number Rev

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

CK804 PCI EXPRESS

CK804A07

1

TECHNOLOGY COPR.

of

15 41Tuesday, October 31, 2006

A

5

D D

C C

PCI_C/BE*[3..0]22,23,25

PCI_AD[31..0]22,23,25

PCI_FRAME*22,23,24,25 PCI_IRDY*22,23,24,25 PCI_TRDY*22,23,24,25 PCI_STOP*22,23,24,25 PCI_DEVSEL*22,23,24,25 PCI_PAR22,23,25 PCI_PERR*22,23,24,25 PCI_SERR*22,23,24 PCI_PME*22,23,24,25 PCI_CLKRUN*24

B B

PCIRST_139425 PCIRST_SLOT1*22 PCIRST_SLOT2*22

PCIRST_SLOT4-3*23

LPCRST_FLASH*27

LPCRST_SIO*32

PCI_AD[31..0]

PCI_C/BE*[3..0]

PCI_FRAME* PCI_IRDY* PCI_TRDY* PCI_STOP* PCI_DEVSEL* PCI_PAR PCI_PERR* PCI_SERR* PCI_PME* PCI_CLKRUN*

PCIRST_SLOT1* PCIRST_SLOT2*

PCIRST_SLOT4-3*

PCIRST_IDE*

LPCRST_FLASH*

LPCRST_SIO*

R717 33R717 33 R176 33R176 33 R177 33R177 33 R179 33R179 33 R181 33R181 33 R183 33R183 33 R184 33R184 33

PCI_AD0

0

PCI_AD1

1

PCI_AD2

2

PCI_AD3

3

PCI_AD4

4

PCI_AD5

5

PCI_AD6

6

PCI_AD7

7

PCI_AD8

8

PCI_AD9

9

PCI_AD10

10

PCI_AD11

11

PCI_AD12

12

PCI_AD13

13

PCI_AD14

14

PCI_AD15

15

PCI_AD16

16

PCI_AD17

17

PCI_AD18

18

PCI_AD19

19

PCI_AD20

20

PCI_AD21

21

PCI_AD22

22

PCI_AD23

23

PCI_AD24

24

PCI_AD25

25

PCI_AD26

26

PCI_AD27

27

PCI_AD28

28

PCI_AD29

29

PCI_AD30

30

PCI_AD31

31

PCI_C/BE*0

0

PCI_C/BE*1

1

PCI_C/BE*2

2

PCI_C/BE*3

3

UNNAMED_23_CK804_I99_PCIRESET4

UNNAMED_23_CK804_I99_PCIRESET0

UNNAMED_23_CK804_I99_PCIRESET1

UNNAMED_23_CK804_I99_PCIRESET2

UNNAMED_23_CK804_I99_PCIRESET3

4

U6C

H7

PCI_AD0

K7

PCI_AD1

J2

PCI_AD2

L9

PCI_AD3

J3

PCI_AD4

J5

PCI_AD5

H8

PCI_AD6

H6

PCI_AD7

K8

PCI_AD8

J4

PCI_AD9

H3

PCI_AD10

G5

PCI_AD11

G6

PCI_AD12

G7

PCI_AD13

H4

PCI_AD14

G3

PCI_AD15

C2

PCI_AD16

C1

PCI_AD17

D2

PCI_AD18

C3

PCI_AD19

B2

PCI_AD20

D3

PCI_AD21

E3

PCI_AD22

E4

PCI_AD23

B4

PCI_AD24

A3

PCI_AD25

A4

PCI_AD26

B3

PCI_AD27

C4

PCI_AD28

C5

PCI_AD29

A5

PCI_AD30

D5

PCI_AD31

J1

PCI_CBE0*

G2

PCI_CBE1*

F3

PCI_CBE2*

D4

PCI_CBE3*

F4

PCI_FRAME*

D1

PCI_IRDY*

E2

PCI_TRDY*

F2

PCI_STOP*

E1

PCI_DEVSEL*

G4

PCI_PAR

F5

PCI_PERR*/GPIO

F6

PCI_SERR*

P6

PCI_PME*/GPIO

N4

PCI_CLKRUN*/GPIO

N2

PCI_RESET0*

N1

PCI_RESET1*

N3

PCI_RESET2*

AF16

PCI_RESET3*

AE7

PCI_RESET*

NF4-4X-B1

PCI_REQ0*

PCI_REQ1* PCI_REQ2*/GPIO PCI_REQ3*/GPIO PCI_REQ4*/GPIO

PCI_GNT0*

PCI_GNT1* PCI_GNT2*/GPIO PCI_GNT3*/GPIO PCI_GNT4*/GPIO

PCI_INTW*

PCI_INTX* PCI_INTY*

PCI_INTZ*

PCI_CLK0 PCI_CLK1 PCI_CLK2 PCI_CLK3 PCI_CLK4 PCI_CLK5

PCI_CLKFB

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

LPC_FRAME*

LPC_DRQ0*

LPC_CS*/DRQ1*

SERIRQ

LPC_PWRDWN*/GPIO

LPC_CLK0

LPC_CLK1

3

N5 N9 M9 M8 P5

M7 M6 M5 K4 P7

B5 E6 E5 D6

K3 L2 K2 K5 L3 L4 M3

AF9 AE10 AD10 AC10

AC8 AF7 AH8 AD8

AE8

AB10

AB11

PCI_REQJ0 PCI_REQJ1 PCI_REQJ2 PCI_REQJ3 PCI_REQJ4

PCI_GNTJ0 PCI_GNTJ1 PCI_GNTJ2 PCI_GNTJ3 PCI_GNTJ4

PCLK_0 PCLK_1 PCLK_2 PCLK_3 PCLK_4 PCI_CLK5 PCI_CLKFB

*

LPC_AD0

0

LPC_AD1

1

LPC_AD2

2

LPC_AD3

3

UNNAMED_23_CK804_I99_LPCCS

TP_LPC_PWRDWN*

LPC_CLK0

C318

10pF

*

50V, NPO, +/-5%

C0603

0 1 2 3 4

PCI_INTW* PCI_INTX* PCI_INTY* PCI_INTZ*

C312

10pF

*

50V, NPO, +/-5%

C0603

LPC_AD[3..0]

C319

10pF

*

50V, NPO, +/-5%

C0603

PCI_REQJ[4..0]

PCI_GNTJ[4..0]

R167

22

+/-5%

r0603h6

C313

10pF

*

50V, NPO, +/-5%

C0603

TP45TP45

1

R180

+/-5% r0603h6

R182 33R182 33

R165

8.2K

r0603h6

+/-5%

PCI_INTW* 22,23,24 PCI_INTX* 22,23,24 PCI_INTY* 22,23,24 PCI_INTZ* 22,23,24,25

R168

22

+/-5%

r0603h6

C315

C314

10pF

*

50V, NPO, +/-5%

C0603

LPC_AD[3..0] 27,32

R173

+/-5%

r0603h6

PCI_CLKSIO

22

PCI_CLKLPC

2

PCI_REQJ[4..0] 22,23,24,25

3D3V_SYS

R166 8.2K

Dummy

PCI_GNTJ[4..0] 22,23,25

R169

22

+/-5%

r0603h6

C316

10pF

*

50V, NPO, +/-5%

C0603

8.2K

PCI_CLKSIO 32

PCI_CLKLPC 27

R170

22

+/-5%

r0603h6

C317

10pF

50V, NPO, +/-5%

C0603

R174

8.2K

+/-5%

r0603h6

PEX REFCLKIN FREQ

0 = 100MHZ 1 = 200MHZ

R171

22

+/-5%

r0603h6

COMMON MODE LEVEL PEX REFCLK 1 = COMMON MODE ABOVE VDD/2 0 = *COMMON MODE BELOW VDD/2

3D3V_SYS3D3V_SYS3D3V_SYS

R175

8.2K

Dummy

+/-5%

r0603h6

LPC_FRAME* LPC_DRQ0*

LPC_SERIRQ

R178

8.2K

+/-5%

r0603h6

1

PCI_CLKSLOT2 PCI_CLKSLOT1 PCI_CLKSLOT3 PCI_CLKSLOT4

R172

1394_CLK

22

+/-5%

r0603h6

LPC_FRAME* 27,32 LPC_DRQ0* 32

LPC_SERIRQ 32

PCI_CLKSLOT2 22 PCI_CLKSLOT1 22 PCI_CLKSLOT3 23 PCI_CLKSLOT4 23 PCI_CLK_1394 25

5V_SYS5V_SB_SYS

R683

R682

10K

+/-5%

r0603h6

R683

10K

+/-5%

r0603h6

IDE_RSTJ 29

R684

A A

PCIRST_IDE*

5

R684

1K

r0603h6

+-5%

C740

0.1uF

*

50V, Y5V, +80%/-20%

C0603

Dummy

Q77

B

PMBT3904

E C

4

DS

Q78

G

2N7002-7-F

Title

Document Number Rev

Date: Sheet

3

2

Date: Sheet

CK804 PCI EXPRESS

CK804A07

TECHNOLOGY COPR.

of

16 41Tuesday, October 31, 2006

of

16 41Tuesday, October 31, 2006

of

16 41Tuesday, October 31, 2006

1

A

5

SATA: 233-100000-020 (AMOC)

PLACE CAPS AT CONN

1

SP_TX0P

C322 10nF

SATA_3

SATA

SATA7_LD18

D D

C C

EC1

100uF

*

16V, +/-20%

CE20D50H110

Dummy

B B

A A

FAB B change

3D3V_SYS

C337

1uF

*

10V, X5R, +/-10%

C0603

SATA7_LD18

U23

2

VIN

RT9166A-15PXL

SATA_4

SATA

SATA_1

SATA

SATA_2

SATA

PLACE VREG CLOSE TO CK804 PLL BALLS

VOUT

GND

1

3D3V_SYS

*

9

8 9

SATA_HDLED*40

3

*

C345

0.1uF

+/-10%

c0603h10

4 5 6 7

1 2 3 4 5 6 7

FB L0805 70 Ohm

+1.5V_SP_PLLPWR

C338

1uF

*

10V, X5R, +/-10%

C0603

FB7

FB L0805 70 Ohm

*

2 3

8

SATA_3

C322 10nF

SP_TX0M

C0402 25V, X7R, +/-10%

SP_RX0M

C324 10nF

SP_RX0P

C0402 25V, X7R, +/-10%

PLACE CAPS AT CONN

SP_TX1P

C326 10nF

SP_TX1M

C0402 25V, X7R, +/-10%

SP_RX1M

C328 10nF

SP_RX1P

C0402 25V, X7R, +/-10%

PLACE CAPS AT CONN

SP_TX2P

C330 10nF

SP_TX2M

C0402 25V, X7R, +/-10%

SP_RX2M

C332 10nF

SP_RX2P

C0402 25V, X7R, +/-10%

PLACE CAPS AT CONN

SP_TX3P

C321 10nF

SP_TX3M

C0402 25V, X7R, +/-10%

SP_RX3M

C334 10nF

SP_RX3P

C0402 25V, X7R, +/-10%

SATA_HDLED*

1D5V_CORE

FB33

Dummy

*

FB6

*

FB L0805 70 Ohm

*

3.3V_PLL_SP_CORE

C346

10uF

6.3V, X5R, +/-10%

C1206

Dummy

*

C347

0.1uF

+/-10%

c0603h10

4

*

* *

*

* *

*

* *

*

* *

*

C336

10nF

*

50V, X7R, +/-10%

C0603

*

C343

C342

0.1uF

10uF

*

+/-10%

6.3V, X5R, +/-10%

c0603h10

C1206

Dummy

*

C323 10nF

C0402 25V, X7R, +/-10%

*

C325 10nF

C0402 25V, X7R, +/-10%

*

C327 10nF

C0402 25V, X7R, +/-10%

*

C329 10nF

C0402 25V, X7R, +/-10%

*

C331 10nF

C0402 25V, X7R, +/-10%

*

C320 10nF

C0402 25V, X7R, +/-10%

*

C333 10nF

C0402 25V, X7R, +/-10%

*

C335 10nF

C0402 25V, X7R, +/-10%

*

TP46TP46 TP48TP48 TP47TP47 TP49TP49

TP50TP50

R185

2.49K

+/-1%

R0603

C339

10uF

*

6.3V, X5R, +/-10%

C1206

Dummy

C344

10nF

*

50V, X7R, +/-10%

C0603

C348

10nF

50V, X7R, +/-10%

C0603

C351

18pF

50V, NPO, +/-5%

C0603

RTC_XTALIN

X2 XTAL-32.768kHzX2 XTAL-32.768kHz

1 2

3

4

SP_RX3P_C

TP_SPREFCLK*

1

TP_SPREFCLK

1

TP_SPTSTCLK*

1

TP_SPTSTCLK

1

TP_ATEST

1

SP_TERMP SP_TERMN

1.5V_PLL_SP

C340

0.1uF

+/-10%

c0603h10

RTC_XTALOUT

*

SP_TX0P_C SP_TX0M_C

SP_RX0M_C SP_RX0P_C

SP_TX1P_C SP_TX1M_C

SP_RX1M_C SP_RX1P_C

SP_TX2P_C SP_TX2M_C

SP_RX2M_C SP_RX2P_C

SP_TX3P_C SP_TX3M_C

SP_RX3M_C

C341

10nF

*

50V, X7R, +/-10%

C0603

C352

18pF

50V, NPO, +/-5%

C0603

U6D

AK9

SP_TXP0

AJ9

SP_TXN0

AJ10

SP_RXN0

AH10

SP_RXP0

AJ11

SP_TXP1

AH11

SP_TXN1

AG11

SP_RXN1

AH12

SP_RXP1

AG13

SP_TXP2

AH13

SP_TXN2

AK13

SP_RXN2

AJ13

SP_RXP2

AJ14

SP_TXP3

AH14

SP_TXN3

AJ15

SP_RXN3

AH15

SP_RXP3

AA14

SP_LED*/GPIO

AD14

SP_REFCLKN

AE14

SP_REFCLKP

AF14

SP_TSTCLKN

AG14

SP_TSTCLKP

AF13

SP_ATEST

AC14

SP_TERMP

AB14

SP_TERMN

AG12

+1.5V_PLL_SP_DVDD

AF12

+1.5V_PLL_SP_AVDD

AE12

+1.5V_PLL_SP_CORE

AD13

+3.3V_PLL_SP_CORE

AF11

GND_PLL_SP

AF5

XTALIN_RTC

AG4

XTALOUT_RTC

NF4-4X-B1

3

XTALIN

XTALOUT

AE20 AA17 AB18 AD18 AE18 AJ17 AG17 AD17 AB17 AH17 AK17 AF18 AC18 AG18 AF20 AD20

AH20 AH19 AG21

AH21 AJ21 AH18 AB20 AJ19 AC20 AA19 AJ18 AG19

AG24 AG23 AJ23 AJ22 AF22 AB21 AF21 AK21 AG22 AD22 AE22 AC22 AH22 AH23 AH24 AF24

AJ28 AJ27 AH26

AG26 AH27 AK26 AE24 AJ26 AF23 AH25 AJ25 AK28

AD16 AE16

AJ29 AH29

IDE_PDD10

IDE_PDD11

IDE_PDD12

IDE_PDD13

IDE_PDD14

IDE_PDD15

IDE_SDD10

IDE_SDD11

IDE_SDD12

IDE_SDD13

IDE_SDD14

IDE_SDD15

IDE_DATA_P0 IDE_DATA_P1 IDE_DATA_P2 IDE_DATA_P3 IDE_DATA_P4 IDE_DATA_P5 IDE_DATA_P6 IDE_DATA_P7 IDE_DATA_P8

IDE_DATA_P9 IDE_DATA_P10 IDE_DATA_P11 IDE_DATA_P12 IDE_DATA_P13 IDE_DATA_P14 IDE_DATA_P15

IDE_ADDR_P0

IDE_ADDR_P1

IDE_ADDR_P2

IDE_CS1_P* IDE_CS3_P*

IDE_DACK_P*

IDE_IOW_P* IDE_INTR_P

IDE_DREQ_P

IDE_IOR_P* IDE_RDY_P

CBL_DET_P

IDE_DATA_S0

IDE_DATA_S1

IDE_DATA_S2

IDE_DATA_S3

IDE_DATA_S4

IDE_DATA_S5

IDE_DATA_S6

IDE_DATA_S7

IDE_DATA_S8

IDE_DATA_S9 IDE_DATA_S10 IDE_DATA_S11 IDE_DATA_S12 IDE_DATA_S13 IDE_DATA_S14 IDE_DATA_S15

IDE_ADDR_S0

IDE_ADDR_S1

IDE_ADDR_S2

IDE_CS1_S* IDE_CS3_S*

IDE_DACK_S*

IDE_IOW_S* IDE_INTR_S

IDE_DREQ_S

IDE_IOR_S* IDE_RDY_S

CBL_DET_S

IDE_COMP_3P3V IDE_COMP_GND

IDE_PDD[15..0]

IDE_PDD0

0

IDE_PDD1

1

IDE_PDD2

2

IDE_PDD3

3

IDE_PDD4

4

IDE_PDD5

5

IDE_PDD6

6

IDE_PDD7

7

IDE_PDD8

8

IDE_PDD9

9

10 11 12 13 14 15

IDE_ADDR_P0 IDE_ADDR_P1 IDE_ADDR_P2

IDE_CS1_P* IDE_CS3_P* IDE_DACK_P* IDE_IOW_P* IDE_INTR_P IDE_DREQ_P IDE_IOR_P* IDE_IORDY_P CBLE_DET_P

IDE_SDD[15..0]

IDE_SDD0

0

IDE_SDD1

1

IDE_SDD2

2

IDE_SDD3

3

IDE_SDD4

4

IDE_SDD5

5

IDE_SDD6

6

IDE_SDD7

7

IDE_SDD8

8

IDE_SDD9

9

10 11 12 13 14 15

IDE_ADDR_S0 IDE_ADDR_S1 IDE_ADDR_S2

IDE_CS1_S* IDE_CS3_S* IDE_DACK_S* IDE_IOW_S* IDE_INTR_S IDE_DREQ_S IDE_IOR_S* IDE_IORDY_S CBLE_DET_S

IDE_COMP_3P3V IDE_COMP_GND

XTALIN XTALOUT

2

*

IDE_ADDR_S0 29 IDE_ADDR_S1 29 IDE_ADDR_S2 29

IDE_CS1_SJ 29 IDE_CS3_SJ 29 IDE_DACK_SJ 29 IDE_IOW_SJ 29 IDE_INTR_S 29 IDE_DREQ_S 29 IDE_IOR_SJ 29 IDE_IORDY_S 29 CBLE_DET_S 29

FOR A02 UP

X1

12

C349

18pF

XTAL-25MHz

*

50V, NPO, +/-5%

C0603

IDE_PDD[15..0] 29

IDE_ADDR_P0 29 IDE_ADDR_P1 29 IDE_ADDR_P2 29

IDE_CS1_PJ 29 IDE_CS3_PJ 29 IDE_DACK_PJ 29 IDE_IOW_PJ 29 IDE_INTR_P 29 IDE_DREQ_P 29 IDE_IOR_PJ 29 IDE_IORDY_P 29 CBLE_DET_P 29

IDE_SDD[15..0] 29

C350

18pF

50V, NPO, +/-5%

C0603

3D3V_SYS

R186

R186 121

121

+/-1%

R0603

R187

R187 121

121

+/-1%

R0603

1

CL

Title

Document Number Rev

Date: Sheet

5

4

3

2

Date: Sheet

CK804 SATA / IDE

CK804A07

TECHNOLOGY COPR.

of

17 41Tuesday, October 31, 2006

of

17 41Tuesday, October 31, 2006

of

17 41Tuesday, October 31, 2006

1

A

5

4

3

2

1

RGMII_RXD[3..0]26

RGMII_TXD[3..0]26

D D

CHECK STRAP

C C

AC_SDOUT30

AC_RST*30 AC_SYNC30

R2F12 FOR GMII

B B

INTR

1 2

Header_1X2

R2F11 FOR MII

VBAT

R239

R239 1M

1M

+/-5%

R0603

R241 0R241 0

R243 0

RGMII_RXD0 RGMII_RXD1 RGMII_RXD2 RGMII_RXD3RGMII_RXD3

RGMII_TXD0 RGMII_TXD1 RGMII_TXD2 RGMII_TXD3

3D3V_DUAL

R189

2.4K

+/-1%

R0603

@8211BL

R195

1.47K

+/-1%

R0603

3D3V_DUAL 3D3V_SYS 3D3V_SYS

R206

10K

+/-5%

r0603h6

@8211BL

Dummy

@8211BL

CLR_CMOS(2-3)1

Jumper_2P-Blue

CLR_CMOS

3 2 1

Header_1X3

INTRUDER*

COPENJ 32

3 2 1

AC_SDOUT

AC_RST* AC_SYNC

C353

0.1uF

*

+/-10%

c0603h10

R209

10K

+/-5%

r0603h6

Dummy

R218

10K

+/-5%

r0603h6

Confirm NVIDIA

VBAT

R234

R234 1M

1M

+/-5%

R0603

Dummy

R210

10K

+/-5%

r0603h6

R219

10K

+/-5%

r0603h6

Dummy

SPDIF031 SPDIF1

VBAT

R235

R235 56K

56K

+/-5%

R0603

RN16

RGMII_TXD1 RGMII_TXD2 RGMII_TXD3 RGMII_TXCTL

RGMII_TXD026 RGMII_TXD126 RGMII_TXD226 RGMII_TXD326 RGMII_TXCLK26 RGMII_TXCTL26

RGMII_RXD026 RGMII_RXD126 RGMII_RXD226 RGMII_RXD326 RGMII_RXCLK26 RGMII_RXCTL26 RGMII_MDC26

CP-MII_RXER26

CP-MII_COL26

RGMII_MDIO26

CP-MII_CRS26

RGMII_25MHZ26

AC97CLK30 AC_BITCLK30

AC_SDIN_030

SPDIF0 SPDIF1

FLASH_TBL*27 FLASH_WP*27 RGMII_RESET*26

3D3V_SYS

*

RGMII_TXD1 RGMII_TXD2 RGMII_TXD3

RGMII_RXCLK RGMII_RXCTL RGMII_MDC USB_4*

RGMII_VREF

TP51TP51

AC_SDIN_0

3D3V_SYS

3D3V_DUAL

FB9

*

C361

FB L0805 70 Ohm

0.1uF

+/-10%

c0603h10

*

1

2

3

4

5

6

7 8

22

+/-5%

8P4R0603

1

R212 22R212 22

R216 10KR216 10K

Dummy

R233

10K

+/-5%

r0603h6

RGMII_RESET*

3.3V_PLL_USB

C362

10uF

*

6.3V, X5R, +/-10%

C1206

Dummy

GMII_TXD1 GMII_TXD2 GMII_TXD3

GMII_TXCTL

U6E

R190 22R190 22

R193 22R193 22

TP_MII_INTR

R211 22R211 22

AC97CLK_R

TP_AC_SDIN_1

3D3V_SYS 3D3V_DUAL

3D3V_SYS

R223

10K

Dummy

+/-5%

r0603h6

R226

R225

10K

+/-5%

r0603h6

TP_GPIO0

TP52TP52

1

R237

10K

TP_SLP_DEEP*

+/-5%

TP53TP53

1

r0603h6

R238

10K

+/-5%

r0603h6

C363

0.1uF

*

+/-10%

c0603h10

BUF_25_R

R224

10K

+/-5%

r0603h6

LID*

LLB*

*

GMII_TXD1 GMII_TXD2 GMII_TXD3

GMII_TXCTLRGMII_TXCTL

H28

J27 J28 J29

H26

J26

G29 E30 F29 F28 H27 G28 K24

E29 K29 K26

J30 K27 K25 K28

M24

AA5

AB8

AA9

AB7 AC7

AG8 AB2 AB3 AC2 AB1

AE6 AF6 AD6 AH6 AE2

AH1

C364

10nF

50V, X7R, +/-10%

C0603

G/MII_TXD0 G/MII_TXD1 G/MII_TXD2 G/MII_TXD3 G/MII_TXCLK G_TXCTL/MII_TXEN

G/MII_RXD0 G/MII_RXD1 G/MII_RXD2 G/MII_RXD3 G/MII_RXCLK G_RXCTL/MII_RXDV G/MII_MDC

MII_VREF MII_RXER_GPIO MII_COL G/MII_MDIO MII_CRS MII_PWRDWN/GPIO MII_INTR/GPIO

BUF_25MHZ

Y6

AC97_CLK AC_BITCLK

Y8

AC_SDATA_OUT/GPIO

Y7

AC_SDATA_IN0/SYS_PERR* AC_SDATA_IN1/SYS_SERR*

Y5

AC_RESET* AC_SYNC/GPIO

SPDIF0/GPIO SPDIF1/GPIO

GPIO_1 GPIO_2/CPU_SLP* GPIO_3/CPU_CLKRUN* GPIO_4/SUS_SATA* GPIO_5/SYS_ERR*

LID*/GPIO SLP_DEEP* V3P3_DEEP LLB* RTC_RST*

+3.3V_PLL_USB

NF4-4X-B1

USB_0

USB_0*

USB_1

USB_1*

USB_2

USB_2*

USB_3

USB_3*

USB_4

USB_4*

USB_5

USB_5*

USB_6

USB_6*

USB_7

USB_7*

USB_8

USB_8*

USB_9

USB_9*

USB_OC0* USB_OC1*/GPIO USB_OC2*/GPIO USB_OC3*/GPIO USB_OC4*/GPIO

USB_RBIAS

+3.3V_PLL_DUAL

A20GATE/GPIO

INTRUDER*

EXT_SMI*/GPIO

RI*/GPIO

SPKR

PWRBTN*

SIO_PME*/GPIO

KBRDRSTIN*/GPIO

SMB_CLK0/GPIO

SMB_DATA0/GPIO

SMB_CLK1/GPIO

SMB_DATA1/GPIO

+3.3V_VBAT BUF_SIO_CLK SUSCLK/GPIO THERM*/GPIO

RSTBIN* SLP_S5*

SLP_S3*

PWRGD_SB

PWRGD

FANRPM/GPIO FANCTL0/GPIO FANCTL1/GPIO

TEST

P2 P3

P8 P9

R2 R3

T3 R4

U3 U4

U1 U2

T5 T6

T7 T8

U5 V6

V7 V8

V4 V5 V3 V2 AA4 V9

A29

AG7 AK3 AH5 AJ3 AF3 AJ2 AJ5 AF2 Y3 W4 W2 W3 AH4 AF1 AG5 AD4 AJ6

AJ7 AH7 AG3 AC4 AA3 AA2 AB4 AE5

R191 15KR191 15K

R194 15K

R197 15KR197 15K

R199 15KR199 15K

R201 15KR201 15K

R220 15K

R204 15K

R207 15K

R221 15K

R214 15K

UNNAMED_25_CK804_I168_USBRBIAS

R222 732

3.3V_PLL_DUAL

C354

10nF

*

50V, X7R, +/-10%

C0603

A20GATE INTRUDER* EXTSMI* SER_RI* SPEAKER PWRBTN* IO_PME* SIO_KBRST* SMB_MEM_SCL SMB_MEM_SDA SMB_SCL SMB_SDA VBAT BUF_SIO_CLK_R SUSCLK_R CPU_THERM* FP_RESET*

SLP_S5* SLP_S3* PWRGD_SB CK8_PWRGD

1 1

CK8_TEST

TP54TP54 TP55TP55

R242 1KR242 1K

@BOTTOM

*

R694

4.7K

+/-5%

r0603h6

R192 15KR192 15K

R196 15K

R198 15KR198 15K

R200 15KR200 15K

R202 15KR202 15K

R203 15K

R205 15K

R208 15K

R213 15K

R215 15K

3D3V_DUAL

C355

0.1uF

+/-10%

c0603h10

R227

22K

+/-5%

r0603h6

USB_1

@BOTTOM

USB_2*

USB_3 USB_3*

USB_5

@BOTTOM

USB_6*

USB_7

@BOTTOM

USB_7*

@BOTTOM

USB_8*

@BOTTOM

USB_9*

@BOTTOM

R680

4.7K

+/-5%

r0603h6

C356

10uF

*

6.3V, X5R, +/-10%

C1206

3D3V_DUAL

Dummy

R228

4.7K

+/-5%

A20GATE 32

r0603h6

EXTSMI* 32 SER_RI* 35 SPEAKER 30,40

PWRBTN# 32

IO_PME* 32 SIO_KBRST* 32

CPU_THERM* 32 FP_RESET* 40

SLP_S5* 37 SLP_S3* 32,40 PWRGD_SB 39 CK8_PWRGD 9,39

R240

10K

3D3V_DUAL

+/-5%

r0603h6

USB_BKPNL_3_2_OC* 28 USB_BKPNL_5_4_OC* 28 USB_FNTPNL_1_0_OC* 28 USB_FNTPNL_6_7_OC* 28

3D3V_DUAL

R236 22R236 22

*

R244

4.7K

+/-5%

R0603

Dummy

USB_0 28 USB_0* 28

USB_1 28 USB_1* 28

USB_4 28 USB_4* 28

USB_5 28 USB_5* 28

USB_6 28 USB_6* 28

USB_7 28 USB_7* 28

USB_8 28 USB_8* 28

USB_9 28 USB_9* 28

FB8

*

FB L0805 70 Ohm

CHECK AGAIN

3D3V_DUAL

R229

2.7K

+/-5%

R0603

C358

10pF

*

50V, NPO, +/-5%

C0603

Dummy

3D3V_SYS

R245

4.7K

+/-5%

R0603

Dummy

3D3V_DUAL

R231

R230

2.7K

+/-5%

R0603

C359

10pF

50V, NPO, +/-5%

C0603

Dummy

*

C357

0.1uF

*

+/-10%

c0603h10

R232

2.7K

+/-5%

R0603

BUF_SIO_CLK

C360

0.1uF

+/-10%

c0603h10

@BOTTOM

SMB_MEM_SCL

SMB_MEM_SDA

J1D1

3 2 1

Header_1X3

dummy

SMB_MEM_SCL 11,12 SMB_MEM_SDA 11,12 SMB_SCL 20,21,22,23,41 SMB_SDA 20,21,22,23,41

BUF_SIO_CLK 32

3D3V_DUAL

21

D28

D29

BAV99

VBAT

BAV99

3

A A

TECHNOLOGY COPR.

Title

Document Number Rev

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

CK804 G/MII / AC97 / USB

CK804A07

1

TECHNOLOGY COPR.

of

18 41Tuesday, October 31, 2006

A

5

4

3

2

1

D D

U6G

AD15 AA15 AB15

AA12 AB12

AF15

AG2 AG1

K20 F25 D27 E26 B30 G24 D28 C29 J21

D30 K21 C30 H24 E27 J22 F26 E28 J24 K23 D29 L22 G25 K22 G26 F27 L21

H22 C28 B29 D26 F24 G23 E25 B27 C26 C27

Y21

U6G

+1.5V +1.5V +1.5V +1.5V +1.5V +1.5V +1.5V +1.5V +1.5V

+1.5V_PE_D +1.5V_PE_D +1.5V_PE_D +1.5V_PE_D +1.5V_PE_D +1.5V_PE_D +1.5V_PE_D +1.5V_PE_D +1.5V_PE_D +1.5V_PE_D +1.5V_PE_D +1.5V_PE_D +1.5V_PE_D +1.5V_PE_D +1.5V_PE_D +1.5V_PE_D +1.5V_PE_D

+1.5V_PE_A +1.5V_PE_A +1.5V_PE_A +1.5V_PE_A +1.5V_PE_A +1.5V_PE_A +1.5V_PE_A +1.5V_PE_A +1.5V_PE_A +1.5V_PE_A

+1.5V_SP_A +1.5V_SP_A +1.5V_SP_A +1.5V_SP_A

+1.5V_PLL_HT +1.5V_SP_D

+1.5V_SP_D

+1.5V_DUAL +1.5V_DUAL

NF4-4X-B1

+3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V

+1.2V_HT +1.2V_HT +1.2V_HT +1.2V_HT +1.2V_HT

+3.3V_DUAL +3.3V_DUAL +3.3V_DUAL +3.3V_DUAL

+3.3V_USB_DUAL +3.3V_USB_DUAL

SP-AGND SP-AGND SP-AGND SP-AGND SP-AGND SP-AGND

SP_DGND SP_DGND

UNNAMED_26_CK804_I21_

AH30

+5V

UNNAMED_26_CK804_I21__1

A6

+5V

AA20 AA18 U10 R10 J9 L10 Y10 W10 AA11

N21 P21 T21 V21 W21

AB9 Y9 P4 M21

AF4 T9

AG15 AH16 AK14 AB13 AG16 AA13

AD12 AC12

1D5V_CORE

FB11 FB L0805 30 Ohm

*

@BOTTOM

*

@BOTTOM/DUMMY

FB10 FB L0805 30 Ohm

C C

1D5V_CORE

C401

4.7uF

*

C0805

*

FB12

*

1.5V_PEX_A

C383

C366

0.1uF

*

C0603

Dummy

C386

0.1uF

*

C0603

FB L0805 70 Ohm

@BOTTOM

C402

0.1uF

*

C0603

@BOTTOM

*

C403

0.1uF

C0603

C367

0.1uF

*

C0603

C397

0.1uF

*

C0603

@BOTTOM

SP_1.5V_A

C404

0.1uF

*

C0603

@BOTTOM

C384

1uF

*

10V, X5R, +/-10%

C0603

@BOTTOM

C387

0.1uF

*

C0603

@BOTTOM

C405

0.1uF

*

C0603

@BOTTOM

C368

4.7uF

C0805

C398

0.1uF

C0603

1D5V_DUAL

1D2V_HT

*

3D3V_SYS

C388

0.1uF

+/-10%

c0603h10

5V_SYS 5V_SYS

R246

100

+/-5%

r0603h6

C369

0.1uF

*

+/-10%

c0603h10

C389

0.1uF

*

+/-10%

c0603h10

R247

100

+/-5%

r0603h6

C370

0.1uF

*

+/-10%

c0603h10

3D3V_DUAL

C391

C390

C399

0.1uF

*

+/-10%

c0603h10

0.1uF

*

+/-10%

c0603h10

1D5V_CORE

C371

0.1uF

*

C0603

1D5V_CORE

C379

10uF

*

10V, Y5V, +80%/-20%

Dummy

C0805

3D3V_SYS

C392

0.1uF

*

+/-10%

c0603h10

Reserved

CK804 DECOUPLING

C372

C373

0.1uF

*

C0603

*

C380

10uF

10V, Y5V, +80%/-20%

C0805

C394

0.1uF

*

+/-10%

c0603h10

@BOTTOM

*

C381

1uF

10V, X5R, +/-10%

C0603

@BOTTOM

*

C0603

*

Dummy

C393

0.1uF

*

+/-10%

c0603h10

@BOTTOM

C374

0.1uF

C0603

C395

0.1uF

*

+/-10%

c0603h10

@BOTTOM

C375

0.1uF

*

C0603

1D5V_DUAL

*

@BOTTOM

*

C365

0.1uF

+/-10%

c0603h10

C385

0.1uF

+/-10%

c0603h10

C376

0.1uF

C0603

*

1D2V_HT

*

C382

0.1uF

+/-10%

c0603h10

C400

0.1uF

*

+/-10%

c0603h10

@BOTTOM

C377

0.1uF

C0603

*

C396

0.1uF

*

+/-10%

c0603h10

@BOTTOM

C378

0.1uF

C0603

B B

M27

N12

N14

N15

N16

N17

N18

N19

AA24

N24

N10

P10

P12

P13

P14

P15

P16

P17

P18

P19

R24

R21

R12

R13

R14

R15

R16

R17

R18

R19

U21

R26

T10

T12

T13

T14

T15

T16

T17

T18

T19

T27

U12

U13

U14

U15

U16

U17

U18

U19

V10

V12

V13

V14

V15

V16

V17

V18

V19

M10

M14

M15

M16

M17

M18

M19

N13

L7

E11

G11

E7

K18

K17

K16

K15

K14

K13

K12

K11

K10

U6F

U6F NF4-4X-B1

GND

GNDM4GND

GNDF7GND

GND

GNDN7GND

GNDP1GND

GND

GNDR5GNDR7GNDR9GND

GND

GNDJ7GND

GNDT4GND

GND

GNDU7GNDU9GNDV1GND

GND

GNDK6GNDH5GND

GND

PE_AGND

PE_AGNDG9PE_AGNDG8PE_AGNDB6PE_AGNDD7PE_AGND

PE_DGND

GND

GNDA2GNDB1GND

GND

GNDC6GND

GND

GNDK1GNDW7GND

GND

GNDF1GND

GND

GNDW5GNDK9GND

GND

GNDW9GNDY4GND

GND

GNDL5PE_AGND

PE_AGND

L24

K30

AB5

AA1

AD7

AK10

A A

5

AH9

AK27

AA16

P27

U24

AK6

W24

AF10

R22

AE1

AE4

AH2

AB19

AB27

AE27

AC16

AE30

AD19

AD21

4

AJ1

AK2

G27

AH3

AJ30

AF19

AB16

AG10

AK18

AK22

AH28

AG20

AG25

H25

AA7

M12

W15

AF17

AK25

AK29

F30

V27

M13

M23

AG6

W12

W22

W13

W17

W26

AE25

AD23

AF8

AD9

AG9

W14

W18

AA21

AA10

3

L26

Y27

W16

W19

AA26

AB22

AD11

J20

E19

D25

E15

D20

D16

G21

G19

G17

PE_DGND

PE_AGND

G15

PE_DGND

PE_AGND

G13

PE_DGND

PE_AGND

J14

PE_DGND

PE_AGND

J13

PE_DGND

PE_AGND

J12

PE_DGND

PE_AGND

PE_DGND

PE_AGND

D12

NF4-4X-B1

TECHNOLOGY COPR.

Title

Document Number Rev

Date: Sheet

Date: Sheet of

2

Date: Sheet of

CK804 DECOUPLING

CK804A07

1

TECHNOLOGY COPR.

of

19 41Tuesday, October 31, 2006

A

5

4

3

2

1

PCI-E1_16X

pcie164_x16_atx

B1 B2 B3 B4 B5 B6 B7 B8

B9 B10 B11

B12 B13 B14 B15 B16 B17 B18

B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32

B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49

B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82

4

pcie164_x16_atx

+12V +12V +12V GND SMCLK SMDAT GND +3.3V TRST* +3.3V_AUX WAKE*

RSVD GND PETP0 PETN0 GND PRSNT2* GND

PETP1 PETN1 GND GND PETP2 PETN2 GND GND PETP3 PETN3 GND RSVD PRSNT2* GND

PETP4 PETN4 GND GND PETP5 PETN5 GND GND PETP6 PETN6 GND GND PETP7 PETN7 GND PRSNT2* GND

PETP8 PETN8 GND GND PETP9 PETN9 GND GND PETP10 PETN10 GND GND PETP11 PETN11 GND GND PETP12 PETN12 GND GND PETP13 PETN13 GND GND PETP14 PETN14 GND GND PETP15 PETN15 GND PRSNT2* RSVD

I1

12V_SYS

D D

3D3V_DUAL

PE_WAKE*15,21

PE0_OUT[15..0]15 PE0_OUT*[15..0]15

PE0_PRSNT*15

C C

B B

A A

5

SMB_SCL18,21,22,23,41

3D3V_SYS

SMB_SDA18,21,22,23,41

PE_WAKE*

PE0_OUT[15..0] PE0_OUT*[15..0]

PE0_PRSNT*

3D3V_SYS

R252

10K

+/-5%

r0603h6

SMB_SCL SMB_SDA

PE_TRST*

R251

10K

PE0_OUT*0

+/-5%

0

r0603h6

PE0_OUT*1

1

PE0_OUT*2

2

PE0_OUT*3

3

PE0_OUT*4

4

PE0_OUT*5

5

PE0_OUT*6

6

PE0_OUT*7

7

PE0_OUT*8

8

PE0_OUT*9

9

PE0_OUT*10

10

PE0_OUT*11

11

PE0_OUT*12

12

PE0_OUT*13

13

PE0_OUT*14

14

PE0_OUT*15

15

PE0_OUT0

0

PE0_OUT1

1

PE0_OUT2

2

PE0_OUT3

3

PE0_OUT4

4

PE0_OUT5

5

PE0_OUT6

6

PE0_OUT7

7

PE0_OUT8

8

PE0_OUT9

9

PE0_OUT10

10

PE0_OUT11

11

PE0_OUT12

12

PE0_OUT13

13

PE0_OUT14

14

PE0_OUT15

15

FAB B change

PCI_EXPRESS_X16

X1 CONNECTOR

X4 CONNECTOR

X8 CONNECTOR

X16 CONNECTOR

PRSNT1*

+12V +12V GND

TCK

TDO

TMS +3.3V +3.3V

PERST*

GND

REFCLK+

REFCLK-

GND PERP0 PERN0

GND

RSVD

GND PERP1 PERN1

GND

GND PERP2 PERN2

GND

GND PERP3 PERN3

GND

RSVD

GND PERP4 PERN4

GND

GND PERP5 PERN5

GND

GND PERP6 PERN6

GND

GND PERP7 PERN7

GND

RSVD

GND PERP8 PERN8

GND

GND PERP9 PERN9

GND

PERP10

PERN10

GND

PERP11

PERN11

GND

PERP12

PERN12

GND

PERP13

PERN13

GND

PERP14

PERN14

GND

PERP15

PERN15

GND

12V_SYS

A1 A2 A3 A4

PE_TCK

A5

PE_TDI

A6

TDI

A7

PE_TMS

A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18

A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32

A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49

A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82

3

PE0_IN0

0

PE0_IN1

1

PE0_IN2

2

PE0_IN3

3

PE0_IN4

4

PE0_IN5

5

PE0_IN6

6

PE0_IN7

7

PE0_IN8

8

PE0_IN9

9

PE0_IN10

10

PE0_IN11

11

PE0_IN12

12

PE0_IN13

13

PE0_IN14

14

PE0_IN15

15

PE_RESET*

PE0_REFCLK PE0_REFCLK* PE0_IN[15..0]

PE0_IN*[15..0]

PE0_IN*0

PE0_IN*1

PE0_IN*2

PE0_IN*3

PE0_IN*4

PE0_IN*5

PE0_IN*6

PE0_IN*7

PE0_IN*8

PE0_IN*9

PE0_IN*10

PE0_IN*11

PE0_IN*12

PE0_IN*13

PE0_IN*14

PE0_IN*15

R248

R249

10K

+/-5%

r0603h6

10K

+/-5%

r0603h6

R250

10K

+/-5%

r0603h6

3D3V_SYS

PE_RESET* 15,21

PE0_REFCLK 15 PE0_REFCLK* 15 PE0_IN[15..0] 15 PE0_IN*[15..0] 15

PLACE CAPS NEAR PEX CONNECTORS

12V_SYS 3D3V_SYS 3D3V_DUAL

C408

C406

0.1uF

*

50V, Y5V, +80%/-20%

C0603

C407

0.1uF

*

50V, Y5V, +80%/-20%

C0603

12V_SYS 3D3V_SYS

EC2

*

2

EC2

470uF

16V, +/-20%

ce35d80h125

Title

Document Number Rev

Date: Sheet

*

EC3

1000uF

6.3V, +/-20%

ce35d80h140

PCI EXPRESS X16 CONNECTOR

C408

0.1uF

*

50V, Y5V, +80%/-20%

C0603

CK804A07

TECHNOLOGY COPR.

of

20 41Tuesday, October 31, 2006

of

20 41Tuesday, October 31, 2006

of

20 41Tuesday, October 31, 2006

1

A

5

4

3

2

1

FAB B change

PCI-E1_1X

B10 B11

B12 B13 B14 B15 B16 B17 B18

B1 B2 B3 B4 B5 B6 B7 B8 B9

B10 B11

B12 B13 B14 B15 B16 B17 B18

B1 B2 B3 B4 B5 B6 B7 B8 B9

YELLOW

PCI-E1_1X

pcie36_x1A

+12V +12V +12V GND SMCLK SMDAT GND +3.3V TRST* +3.3V_AUX WAKE*

RSVD GND PETP0 PETN0 GND PRSNT2* GND

I1

FAB B change

PCI-E2_1X

pcie36_x1A

+12V +12V +12V GND SMCLK SMDAT GND +3.3V TRST* +3.3V_AUX WAKE*

RSVD GND PETP0 PETN0 GND PRSNT2* GND

I1

YELLOW

PCI_EXPRESS_X1

X1 CONNECTOR

PCI_EXPRESS_X1

X1 CONNECTOR

PRSNT1*

+12V +12V GND

TCK

TDO

TMS +3.3V +3.3V

PERST*

GND

REFCLK+

REFCLK-

GND

PERP0

PERN0

GND

PRSNT1*

PERST*

REFCLK+

REFCLK-

PERN0

3D3V_DUAL

R261

10K

+/-5%

r0603h6

3D3V_SYS3D3V_DUAL 12V_SYS

PE_TRST_1

R257

10K

+/-5%

r0603h6

3D3V_SYS12V_SYS

PE_TRST_2

R262

10K

+/-5%

r0603h6

D D

SMB_SCL18,20,22,23,41 SMB_SDA18,20,22,23,41

PE_WAKE*15,20

PE1_OUT15 PE1_OUT*15

PE1_PRSNT*15

C C

B B

SMB_SCL18,20,22,23,41 SMB_SDA18,20,22,23,41

PE_WAKE*15,20

PE2_OUT15 PE2_OUT*15

PE2_PRSNT*15

SMB_SCL SMB_SDA

PE_WAKE*

PE1_OUT PE1_OUT*

PE1_PRSNT*

3D3V_SYS

SMB_SCL

PE2_OUT*

PE2_PRSNT*

3D3V_SYS

R256

10K

+/-5%

r0603h6

TDI

+12V +12V GND

TCK

TDO

TMS +3.3V +3.3V

GND

PERP0

GND

12V_SYS

R253

PE_TCK_2 PE_TDI_2SMB_SDA

PE_TMS_2

R253

R254

10K

+/-5%

r0603h6

10K

+/-5%

PE_RESET*

r0603h6

PE1_REFCLK PE1_REFCLK*

PE1_IN PE1_IN*

R258

R259

10K

+/-5%

r0603h6

10K

+/-5%

PE_RESET*PE_WAKE*

r0603h6

PE2_REFCLK PE2_REFCLK*PE2_OUT

PE2_IN PE2_IN*

R255

10K

+/-5%

r0603h6

R260

10K

+/-5%

r0603h6

3D3V_SYS

PE_RESET* 15,20

PE1_REFCLK 15 PE1_REFCLK* 15

PE1_IN 15 PE1_IN* 15

3D3V_SYS

PE_RESET* 15,20

PE2_REFCLK 15 PE2_REFCLK* 15

PE2_IN 15 PE2_IN* 15

12V_SYS 3D3V_SYS

C411

*

12V_SYS

*

C409

0.1uF

*

C0603

EC4

470uF

16V, +/-20%

ce35d80h125

C410

0.1uF

C0603

C411

0.1uF

*

C0603

3D3V_DUAL

C412

0.1uF

*

C0603

*

C413

0.1uF

C0603

C414

0.1uF

*

C0603

A1 A2 A3 A4

PE_TCK_1

A5

PE_TDI_1

A6 A7

PE_TMS_1

A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18

12V_SYS

A1 A2 A3 A4 A5 A6

TDI

A7 A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18

A A

TECHNOLOGY COPR.

Title

Document Number Rev

Date: Sheet

5

4

3

2

Date: Sheet

PCI EXPRESS X1 CONNECTOR

CK804A07

TECHNOLOGY COPR.

of

21 41Tuesday, October 31, 2006

of

21 41Tuesday, October 31, 2006

of

21 41Tuesday, October 31, 2006

1

A

5

4

3

2

1

SLOT 1 (FURTHEST FROM CPU)

PCI4

I136

D D

C C

PCI_C/BE*[3..0]16,23,25

PCI_INTY*16,23,24 PCI_INTZ*16,23,24,25 PCI_INTW*16,23,24 PCI_INTX*16,23,24 PCI_REQJ[4..0]16,23,24,25 PCI_GNTJ[4..0]16,23,25

PCI_PME*16,23,24,25 PCI_FRAME*16,23,24,25 PCI_TRDY*16,23,24,25 PCI_STOP*16,23,24,25 PCI_IRDY*16,23,24,25 PCI_DEVSEL*16,23,24,25

PCI_AD[31..0]16,23,25

B B

PCI_LOCK*23,24 PCI_PERR*16,23,24,25 PCI_SERR*16,23,24

PCI_PAR16,23,25 SMB_SDA18,20,21,23,41

PCIRST_SLOT1*16

SMB_SCL18,20,21,23,41 PCI_REQ64A*24

PCI_ACK64*23,24

PCI_CLKSLOT116

PCI_AD[31..0]

PCI_C/BE*[3..0]

PCI_INTY* PCI_INTZ* PCI_INTW* PCI_INTX* PCI_REQJ[4..0] PCI_GNTJ[4..0]

PCI_PME* PCI_FRAME* PCI_TRDY* PCI_STOP* PCI_IRDY* PCI_DEVSEL* PCI_LOCK* PCI_PERR* PCI_SERR* PCI_PAR SMB_SDA PCIRST_SLOT1* SMB_SCL

PCI_REQ64A* PCI_ACK64* PCI_CLKSLOT1

0 1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 26

0

1

2

3

4

I136

PCI_AD0

A58

PCI_AD1

B58

PCI_AD2

A57

PCI_AD3

B56

PCI_AD4

A55

PCI_AD5

B55

PCI_AD6

A54

PCI_AD7

B53

PCI_AD8

B52

PCI_AD9

A49

PCI_AD10

B48

PCI_AD11

A47

PCI_AD12

B47

PCI_AD13

A46

PCI_AD14

B45

PCI_AD15

A44

PCI_AD16

A32

PCI_AD17

B32

PCI_AD18

A31

PCI_AD19

B30

PCI_AD20

A29

PCI_AD21

B29

PCI_AD22

A28

PCI_AD23

B27

PCI_AD24

A25

PCI_AD25

B24

PCI_AD26

A23

PCI_AD27

B23

PCI_AD28

A22

PCI_AD29

B21

PCI_AD30

A20

PCI_AD31

B20

PCI_AD26

A26

PCI_C/BE*0

A52

PCI_C/BE*1

B44

PCI_C/BE*2

B33

PCI_C/BE*3

B26

A6 B7 A7 B8

PCI_REQJ4

B18

PCI_GNTJ4

A17 A19

A34 A36 A38 B35 B37 B39 B40 B42 A43 A41 A15 A40

A60 B60 B16

AD0

AD2

AD2 AD3

AD3 AD4

AD4 AD5

AD5 AD6

AD6 AD7

AD7 AD8

AD8 AD9

AD9 AD10

AD10 AD11

AD11 AD12

AD12 AD13

AD13 AD14

AD14 AD15

AD15 AD16

AD16 AD17

AD17 AD18

AD18 AD19

AD19 AD20

AD20 AD21

AD21 AD22

AD22 AD23

AD23 AD24

AD24 AD25

AD25 AD26

AD26 AD27

AD27 AD28

AD28 AD29

AD29 AD30

AD30 AD31

AD31 IDSEL

IDSEL

CBE0*

CBE0* CBE1*

CBE1* CBE2*

CBE2* CBE3*

CBE3*

INTA*

INTA* INTB*

INTB* INTC*

INTC* INTD*

INTD*

REQ*

REQ* GNT*

GNT*

PME*

PME* FRAME*

FRAME*

STOP*

STOP* IRDY*

IRDY* DEVSEL*

DEVSEL* LOCK*

LOCK* PERR*

PERR* SERR*

SERR* PAR

PAR SBO*

SBO* RESET*

RESET* SDONE

SDONE

REQ64*

REQ64* ACK64*

ACK64* CLOCK

CLOCK

KEY<A50>

KEY<A50> KEY<A51>

KEY<A51> KEY<B50>

KEY<B50> KEY<B51>

KEY<B51>

PCI124

V2.2

5V 32BIT

3.3VAUX

PRSNT1*

PRSNT1* PRSNT2*

PRSNT2*

RSVD1

RSVD1 RSVD2

RSVD2 RSVD3

RSVD3 RSVD5

RSVD5

TRST*

+12V

-12V

+3.3V

+3.3V +3.3V

+3.3V

TDOAD1

TCK

TMS

TMS TDI

TDI

+5V

+5V +5V

+5V

GND

GND GNDTRDY*

GNDTRDY* GND

GND GND

GND

pci124h155

A14 B4 B9 B11 A9 B10 A11 B14 B2 A1 A3 A4

A2 B1

B5 B6 A5 A8 A10 B61 A16 B62 A59 B59 A61 B19 A62

A21 A27 A33 A39 A45 B43 B41 B36 B31 B25 B54 A53

A12 A13 A18 A24 A30 A35 A37 A42 A48 A56 B3 B12 B13 B15 B17 B22 B28 B34 B38 B46 B49 B57

3D3V_DUAL

12V_SYS -12V_SYS

5V_SYS

3D3V_SYS

PCI3

I136

A58 B58 A57 B56 A55 B55 A54 B53 B52 A49 B48 A47 B47 A46 B45 A44 A32 B32 A31 B30 A29 B29 A28 B27 A25 B24 A23 B23 A22 B21 A20 B20 A26

A52 B44 B33 B26

B18 A17

A19 A34 A36 A38 B35 B37 B39 B40 B42 A43 A41 A15 A40

A60 B60 B16

I136

PCI124

V2.2

5V 32BIT

AD0

AD2

AD2 AD3

AD3 AD4

AD4 AD5

AD5 AD6

AD6 AD7

AD7 AD8

AD8 AD9

AD9 AD10

AD10 AD11

AD11 AD12

AD12 AD13

AD13 AD14

AD14 AD15

AD15 AD16

AD16 AD17

AD17 AD18

AD18 AD19

AD19 AD20

AD20 AD21

AD21 AD22

AD22 AD23

AD23 AD24

AD24 AD25

AD25 AD26

AD26 AD27

AD27 AD28

AD28 AD29

AD29 AD30

AD30 AD31

AD31 IDSEL

IDSEL

CBE0*

CBE0* CBE1*

CBE1* CBE2*

CBE2* CBE3*

CBE3*

A6

INTA*

B7

INTB*

A7

INTC*

B8

INTD*

REQ*

REQ* GNT*

GNT*

PME*

PME* FRAME*

FRAME*

STOP*

STOP* IRDY*

IRDY* DEVSEL*

DEVSEL* LOCK*

LOCK* PERR*

PERR* SERR*

SERR* PAR

PAR SBO*

SBO* RESET*

RESET* SDONE

SDONE

REQ64*

REQ64* ACK64*

ACK64* CLOCK

CLOCK

KEY<A50>

KEY<A50> KEY<A51>

KEY<A51> KEY<B50>

KEY<B50> KEY<B51>

KEY<B51>

PCI_AD[31..0]16,23,25

PCI_C/BE*[3..0]16,23,25

PCI_INTW*16,23,24 PCI_INTX*16,23,24 PCI_INTY*16,23,24 PCI_INTZ*16,23,24,25 PCI_REQJ[4..0]16,23,24,25 PCI_GNTJ[4..0]16,23,25

PCI_PME*16,23,24,25 PCI_FRAME*16,23,24,25 PCI_TRDY*16,23,24,25 PCI_STOP*16,23,24,25 PCI_IRDY*16,23,24,25 PCI_DEVSEL*16,23,24,25 PCI_LOCK*23,24

PCI_PERR*16,23,24,25 PCI_SERR*16,23,24 PCI_PAR16,23,25 SMB_SDA18,20,21,23,41

PCIRST_SLOT2*16

SMB_SCL18,20,21,23,41 PCI_REQ64B*24

PCI_ACK64*23,24

PCI_CLKSLOT216

PCI_AD[31..0]

PCI_C/BE*[3..0]

PCI_INTW* PCI_INTX* PCI_INTY* PCI_INTZ* PCI_REQJ[4..0] PCI_GNTJ[4..0]

PCI_PME* PCI_FRAME* PCI_TRDY* PCI_STOP* PCI_IRDY* PCI_DEVSEL* PCI_LOCK* PCI_PERR* PCI_SERR* PCI_PAR SMB_SDA PCIRST_SLOT2* SMB_SCL

PCI_REQ64B* PCI_ACK64* PCI_CLKSLOT2

PCI_AD0

0

PCI_AD1

1

PCI_AD2

2

PCI_AD3

3

PCI_AD4

4

PCI_AD5

5

PCI_AD6

6

PCI_AD7

7

PCI_AD8

8

PCI_AD9

9

PCI_AD10

10

PCI_AD11

11

PCI_AD12

12

PCI_AD13

13

PCI_AD14

14

PCI_AD15

15

PCI_AD16

16

PCI_AD17

17

PCI_AD18

18

PCI_AD19

19

PCI_AD20

20

PCI_AD21

21

PCI_AD22

22

PCI_AD23

23

PCI_AD24

24

PCI_AD25

25

PCI_AD26

26

PCI_AD27

27

PCI_AD28

28

PCI_AD29

29

PCI_AD30

30

PCI_AD31

31

PCI_AD24

24

PCI_C/BE*0

0

PCI_C/BE*1

1

PCI_C/BE*2

2

PCI_C/BE*3

3

PCI_REQJ2

2

PCI_GNTJ2

2

3.3VAUX

PRSNT1*

PRSNT1* PRSNT2*

PRSNT2*

RSVD1

RSVD1 RSVD2

RSVD2 RSVD3

RSVD3 RSVD5

RSVD5

TRST*

+3.3V

+3.3V +3.3V

+3.3V

TDOAD1

TCK

TMS

TMS TDI

TDI

+12V

-12V

+5V

+5V +5V

+5V

GND

GND GNDTRDY*

GNDTRDY* GND

GND GND

GND

pci124h155

SLOT 2

A14 B4 B9 B11 A9 B10 A11 B14 B2 A1 A3 A4

A2 B1

B5 B6 A5 A8 A10 B61 A16 B62 A59 B59 A61 B19 A62

A21 A27 A33 A39 A45 B43 B41 B36 B31 B25 B54 A53

A12 A13 A18 A24 A30 A35 A37 A42 A48 A56 B3 B12 B13 B15 B17 B22 B28 B34 B38 B46 B49 B57

3D3V_DUAL

12V_SYS -12V_SYS

5V_SYS

3D3V_SYS

A A

TECHNOLOGY COPR.

Title

Document Number Rev

Date: Sheet

5

4

3

2

Date: Sheet

PCI CONNECTOR 1-2

CK804A07

TECHNOLOGY COPR.

of

22 41Tuesday, October 31, 2006

of

22 41Tuesday, October 31, 2006

of

22 41Tuesday, October 31, 2006

1

A

5

4

3

2

1

SLOT 3

PCI2

A58 B58 A57 B56 A55 B55 A54 B53 B52 A49 B48 A47 B47 A46 B45 A44 A32 B32 A31 B30 A29 B29 A28 B27 A25 B24 A23 B23 A22 B21 A20 B20 A26

A52 B44 B33 B26

B18 A17

A19 A34 A36 A38 B35 B37 B39 B40 B42 A43 A41 A15 A40

A60 B60 B16

PCI2

I136

A6 B7 A7 B8

AD0

AD2

AD2 AD3

AD3 AD4

AD4 AD5

AD5 AD6

AD6 AD7

AD7 AD8

AD8 AD9

AD9 AD10

AD10 AD11

AD11 AD12

AD12 AD13

AD13 AD14

AD14 AD15

AD15 AD16

AD16 AD17

AD17 AD18

AD18 AD19

AD19 AD20

AD20 AD21

AD21 AD22

AD22 AD23

AD23 AD24

AD24 AD25

AD25 AD26

AD26 AD27

AD27 AD28

AD28 AD29

AD29 AD30

AD30 AD31

AD31 IDSEL

IDSEL

CBE0*

CBE0* CBE1*

CBE1* CBE2*

CBE2* CBE3*

CBE3*

INTA*

INTA* INTB*

INTB* INTC*

INTC* INTD*

INTD*

REQ*

REQ* GNT*

GNT*

PME*

PME* FRAME*

FRAME*

STOP*

STOP* IRDY*

IRDY* DEVSEL*

DEVSEL* LOCK*

LOCK* PERR*

PERR* SERR*

SERR* PAR

PAR SBO*

SBO* RESET*

RESET* SDONE

SDONE

REQ64*

REQ64* ACK64*

ACK64* CLOCK

CLOCK

KEY<A50>

KEY<A50> KEY<A51>

KEY<A51> KEY<B50>

KEY<B50> KEY<B51>

KEY<B51>

PCI124

V2.2

5V 32BIT

3.3VAUX

PRSNT1*

PRSNT1* PRSNT2*

PRSNT2*

RSVD1

RSVD1 RSVD2

RSVD2 RSVD3

RSVD3 RSVD5

RSVD5

TRST*

+12V

-12V

+3.3V

+3.3V +3.3V

+3.3V

TDOAD1

TCK

TMS

TMS TDI

TDI

+5V

+5V +5V

+5V

GND

GND GNDTRDY*

GNDTRDY* GND

GND GND

GND

pci124h155

A14 B4 B9 B11 A9 B10 A11 B14 B2 A1 A3 A4

A2 B1

B5 B6 A5 A8 A10 B61 A16 B62 A59 B59 A61 B19 A62

A21 A27 A33 A39 A45 B43 B41 B36 B31 B25 B54 A53

A12 A13 A18 A24 A30 A35 A37 A42 A48 A56 B3 B12 B13 B15 B17 B22 B28 B34 B38 B46 B49 B57

D D

PCI_AD[31..0]16,22,25

C C

PCI_C/BE*[3..0]16,22,25

PCI_INTZ*16,22,24,25 PCI_INTW*16,22,24 PCI_INTX*16,22,24 PCI_INTY*16,22,24 PCI_REQJ[4..0]16,22,24,25 PCI_GNTJ[4..0]16,22,25

PCI_PME*16,22,24,25 PCI_FRAME*16,22,24,25

B B

PCI_TRDY*16,22,24,25 PCI_STOP*16,22,24,25 PCI_IRDY*16,22,24,25 PCI_DEVSEL*16,22,24,25 PCI_LOCK*22,24 PCI_PERR*16,22,24,25 PCI_SERR*16,22,24 PCI_PAR16,22,25 SMB_SDA18,20,21,22,41

PCIRST_SLOT4-3*16

SMB_SCL18,20,21,22,41 PCI_REQ64C*24

PCI_ACK64*22,24

PCI_CLKSLOT316

PCI_AD[31..0]

PCI_C/BE*[3..0]

PCI_INTZ* PCI_INTW* PCI_INTX* PCI_INTY*

PCI_REQJ[4..0] PCI_GNTJ[4..0]

PCI_PME* PCI_FRAME* PCI_TRDY* PCI_STOP* PCI_IRDY* PCI_DEVSEL* PCI_LOCK* PCI_PERR* PCI_SERR* PCI_PAR SMB_SDA PCIRST_SLOT4-3* SMB_SCL

PCI_REQ64C* PCI_ACK64* PCI_CLKSLOT3

PCI_AD0

0

PCI_AD1

1

PCI_AD2

2

PCI_AD3

3

PCI_AD4

4

PCI_AD5

5

PCI_AD6

6

PCI_AD7

7

PCI_AD8

8

PCI_AD9

9

PCI_AD10

10

PCI_AD11

11

PCI_AD12

12

PCI_AD13

13

PCI_AD14

14

PCI_AD15

15

PCI_AD16

16

PCI_AD17

17

PCI_AD18

18

PCI_AD19

PCI_AD20

20

PCI_AD21

21

PCI_AD22

22

PCI_AD23

23

PCI_AD24

24

PCI_AD25

25

PCI_AD26

26

PCI_AD27

27

PCI_AD28

28

PCI_AD29

29

PCI_AD30

30

PCI_AD31

31

PCI_AD23

23

PCI_C/BE*0

0

PCI_C/BE*1

1

PCI_C/BE*2

2

PCI_C/BE*3

3

PCI_REQJ1

1

PCI_GNTJ1

1

3D3V_DUAL

12V_SYS -12V_SYS

5V_SYS

3D3V_SYS

PCI_AD[31..0]16,22,25

PCI_C/BE*[3..0]16,22,25

PCI_INTX*16,22,24 PCI_INTY*16,22,24 PCI_INTZ*16,22,24,25 PCI_INTW*16,22,24 PCI_REQJ[4..0]16,22,24,25 PCI_GNTJ[4..0]16,22,25

PCI_PME*16,22,24,25 PCI_FRAME*16,22,24,25 PCI_TRDY*16,22,24,25 PCI_STOP*16,22,24,25 PCI_IRDY*16,22,24,25 PCI_DEVSEL*16,22,24,25 PCI_LOCK*22,24

PCI_PERR*16,22,24,25 PCI_SERR*16,22,24 PCI_PAR16,22,25 SMB_SDA18,20,21,22,41

PCIRST_SLOT4-3*16

SMB_SCL18,20,21,22,41 PCI_REQ64D*24

PCI_ACK64*22,24

PCI_CLKSLOT416

PCI_AD[31..0]

PCI_C/BE*[3..0]

PCI_INTX* PCI_INTY* PCI_INTZ* PCI_INTW*

PCI_REQJ[4..0] PCI_GNTJ[4..0]

PCI_PME* PCI_FRAME* PCI_TRDY* PCI_STOP* PCI_IRDY* PCI_DEVSEL* PCI_LOCK* PCI_PERR* PCI_SERR* PCI_PAR SMB_SDA PCIRST_SLOT4-3* SMB_SCL

PCI_REQ64D* PCI_ACK64* PCI_CLKSLOT4

PCI_AD0

0

A58

PCI_AD1

1

B58

PCI_AD2

2

A57

PCI_AD3

3

B56

PCI_AD4

4

A55

PCI_AD5

5

B55

PCI_AD6

6

A54

PCI_AD7

7

B53

PCI_AD8

8

B52

PCI_AD9

9

A49

PCI_AD10

10

B48

PCI_AD11

11

A47

PCI_AD12

12

B47

PCI_AD13

13

A46

PCI_AD14

14

B45

PCI_AD15

15

A44

PCI_AD16

16

A32

PCI_AD17

17

B32

PCI_AD18

18

A31

PCI_AD19

1919

B30

PCI_AD20

20

A29

PCI_AD21

21

B29

PCI_AD22

22

A28

PCI_AD23

23

B27

PCI_AD24

24

A25

PCI_AD25

25

B24

PCI_AD26

26

A23

PCI_AD27

27

B23

PCI_AD28

28

A22

PCI_AD29

29

B21

PCI_AD30

30

A20

PCI_AD31

31

B20

PCI_AD22

22

A26

PCI_C/BE*0

0

A52

PCI_C/BE*1

1

B44

PCI_C/BE*2

2

B33

PCI_C/BE*3

3

B26

A6 B7 A7 B8

PCI_REQJ3

3

B18

PCI_GNTJ3

3

A17 A19

A34 A36 A38 B35 B37 B39 B40 B42 A43 A41 A15 A40

A60 B60 B16

SLOT 4 (CLOSEST TO CPU)

PCI1

I136

AD0

AD2

AD2 AD3

AD3 AD4

AD4 AD5

AD5 AD6

AD6 AD7

AD7 AD8

AD8 AD9

AD9 AD10

AD10 AD11

AD11 AD12

AD12 AD13

AD13 AD14

AD14 AD15

AD15 AD16

AD16 AD17

AD17 AD18

AD18 AD19

AD19 AD20

AD20 AD21

AD21 AD22

AD22 AD23

AD23 AD24

AD24 AD25

AD25 AD26

AD26 AD27

AD27 AD28

AD28 AD29

AD29 AD30

AD30 AD31

AD31 IDSEL

IDSEL

CBE0*

CBE0* CBE1*

CBE1* CBE2*

CBE2* CBE3*

CBE3*

INTA*

INTA* INTB*

INTB* INTC*

INTC* INTD*

INTD*

REQ*

REQ* GNT*

GNT*

PME*

PME* FRAME*

FRAME*

STOP*

STOP* IRDY*

IRDY* DEVSEL*

DEVSEL* LOCK*

LOCK* PERR*

PERR* SERR*

SERR* PAR

PAR SBO*

SBO* RESET*

RESET* SDONE

SDONE

REQ64*

REQ64* ACK64*

ACK64* CLOCK

CLOCK

KEY<A50>

KEY<A50> KEY<A51>

KEY<A51> KEY<B50>

KEY<B50> KEY<B51>

KEY<B51>

PCI124

V2.2

5V 32BIT

3.3VAUX

PRSNT1*

PRSNT1* PRSNT2*

PRSNT2*

RSVD1

RSVD1 RSVD2

RSVD2 RSVD3

RSVD3 RSVD5

RSVD5

TRST*

+12V

-12V

+3.3V

+3.3V +3.3V

+3.3V

TDOAD1

TCK

TMS

TMS TDI

TDI

+5V

+5V +5V

+5V

GND

GND GNDTRDY*

GNDTRDY* GND

GND GND

GND

pci124h155

A14 B4 B9 B11 A9 B10 A11 B14 B2 A1 A3 A4

A2 B1

B5 B6 A5 A8 A10 B61 A16 B62 A59 B59 A61 B19 A62

A21 A27 A33 A39 A45 B43 B41 B36 B31 B25 B54 A53

A12 A13 A18 A24 A30 A35 A37 A42 A48 A56 B3 B12 B13 B15 B17 B22 B28 B34 B38 B46 B49 B57

12V_SYS

5V_SYS

3D3V_SYS

3D3V_DUAL

-12V_SYS

A A

TECHNOLOGY COPR.

Title

Document Number Rev

Date: Sheet

5

4

3

2

Date: Sheet

PCI CONNECTOR 3-4

CK804A07

TECHNOLOGY COPR.

of

23 41Tuesday, October 31, 2006

of

23 41Tuesday, October 31, 2006

of

23 41Tuesday, October 31, 2006

1

A

5

4

3

2

1

D D

C C

PCI_SERR*16,22,23

PCI_DEVSEL*16,22,23,25

PCI_IRDY*16,22,23,25

PCI_LOCK*22,23

PCI_PERR*16,22,23,25

PCI_FRAME*16,22,23,25

PCI_TRDY*16,22,23,25

PCI_STOP*16,22,23,25

PCI_ACK64*22,23

PCI_REQ64A*22

PCI_REQ64B*22

PCI_REQ64C*23

PCI_REQ64D*23

PCI_SERR*

PCI_DEVSEL*

PCI_IRDY*

PCI_LOCK*

PCI_PERR*

PCI_FRAME*

PCI_TRDY*

PCI_STOP*

PCI_ACK64*

PCI_REQ64A*

PCI_REQ64B*

PCI_REQ64C*

PCI_REQ64D*

PCI_REQ64A* PCI_REQ64B* PCI_REQ64C* PCI_ACK64*

PCI_FRAME* PCI_IRDY* PCI_TRDY* PCI_DEVSEL*

PCI_STOP* PCI_LOCK* PCI_PERR* PCI_SERR*

PCI_REQ64D*

RN17

*

1

2

3

4

5

6

7 8

8.2K

+/-5%

8.2K

+/-5%

8P4R0603

RN18

*

1

2

3

4

5

6

7 8

8.2K

+/-5%

8.2K

+/-5%

8P4R0603

RN20

*

1

2

3

4

5

6

7 8

8.2K

+/-5%

8.2K

+/-5%

8P4R0603

R270 8.2KR270 8.2K

3D3V_SYS

PCI_REQJ[4..0]16,22,23,25

PCI_INTW*16,22,23 PCI_INTX*16,22,23 PCI_INTY*16,22,23 PCI_INTZ*16,22,23,25

PCI_CLKRUN*16

PCI_PME*16,22,23,25

PCI_REQJ[4..0]

PCI_INTW* PCI_INTX* PCI_INTY* PCI_INTZ*

PCI_CLKRUN*

PCI_PME*

0

1

2

3

4

PCI_REQ*0

PCI_REQ*1

PCI_REQ*2

PCI_REQ*3

PCI_REQ*4

PCI_REQJ0

PCI_REQJ1

PCI_REQJ2

PCI_REQJ3

PCI_REQJ4

R263 8.2KR263 8.2K

R264 8.2KR264 8.2K

R265 8.2KR265 8.2K

R266 8.2KR266 8.2K

R267 8.2KR267 8.2K

RN19

*

1

2

3

4

5

6

7 8

8.2K

+/-5%

8.2K

+/-5%

8P4R0603

R268 8.2KR268 8.2K

R269 8.2KR269 8.2K

3D3V_DUAL

B B

12V_SYS 5V_SYS-12V_SYS

CE20D50H110

C416

0.1uF

C0603

C417

0.1uF

*

C0603

0.1uF

C0603

16V, +/-20%

*

100uF

EC5

Dummy

*

C415

0.1uF

*

C0603

A A

5

CE20D50H110

C418

C417

C419

0.1uF

C0603

C420

C421

0.1uF

C0603

4

0.1uF

*

C0603

*

EC6

1000uF

6.3V, +/-20%

ce35d80h140

C422

C423

C424

C425

EC61

0.1uF

*

C0603

0.1uF

*

C0603

3

0.1uF

C0603

*

Dummy

EC61

1000uF

6.3V, +/-20%

ce35d80h140

3D3V_SYS

*

C426

0.1uF

C0603

C427

0.1uF

*

C0603

2

EC7

C428

1000uF

0.1uF

*

6.3V, +/-20%

ce35d80h140

C0603

Title

Document Number Rev

Date: Sheet

EC62

1000uF

*

6.3V, +/-20%

ce35d80h140

PCI TERMINATION

CK804A07

TECHNOLOGY COPR.

24 41Tuesday, October 31, 2006

1

A

of

A

5

IEEE-1394

INTF#

Did not support S3 wake-up

D D

C C

TPBIAS0

TPBIAS1

B B

A A

AD27

PCI_C/BE*[3..0]16,22,23

PCI_C/BE*[3..0]

PCIRST_139416

PCI_CLK_139416

PCI_GNTJ016 PCI_REQJ016,24

PCI_INTZ*16,22,23,24

PCI_FRAME*16,22,23,24 PCI_IRDY*16,22,23,24 PCI_TRDY*16,22,23,24 PCI_DEVSEL*16,22,23,24 PCI_STOP*16,22,23,24 PCI_PERR*16,22,23,24 PCI_PAR16,22,23

PCI_AD[31..0]16,22,23

Place near chip side

R280

R281

*

TB0TB0+ TA0TA0+

54.9

+/-1%

R0603

R288

54.9

+/-1%

R0603

*

R303 0

R303 0 R296 0

R296 0 R298 0

R298 0 R300 0

R300 0

L1

Dummy

1 4 3

Common Choke 90 Ohm_2L

L3

Dummy

1 4 3

Common Choke 90 Ohm_2L

5

54.9

+/-1%

R0603

R287

54.9

+/-1%

R0603

TB0+ TPB0

TA0+ TPA0 TA0-

PCI_C/BE*0 PCI_C/BE*1 PCI_C/BE*2 PCI_C/BE*3

PCIRST#1 1394_CLK PCI_GNTJ0 PCI_REQJ0 PIRQ#Z

FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# PAR

AD[31..0]

C449

0.33uF

16V, X7R, +/-10%

C0805

TPA0 TPA0#

C451

0.33uF

16V, X7R, +/-10%

C0805

TPA1 TPA1#

Co-Layout

*

2

R282 4.99K

R0603 +/-1%

C450 270pF

C0603

R289 4.99K

R0603 +/-1%

C452 270pF

C0603

TPB0# TPB0 TPA0# TPA0

TPB0#TB0-

TPA0#

AD27

3D3V_1394

*

AD26 AD25 AD24

R276 100R276 100

PCI_C/BE*3 AD23

AD22 AD21

VDD_1394

AD20 AD19 AD18 AD17 AD16

PCI_C/BE*2 FRAME# IRDY#

TRDY# DEVSEL# STOP#

R283 54.9 R0603 +/-1%R283 54.9R0603 +/-1%

R286 54.9 R0603 +/-1%R286 54.9R0603 +/-1%

R290 54.9 R0603 +/-1%R290 54.9R0603 +/-1%

R294 54.9 R0603 +/-1%R294 54.9R0603 +/-1%

TA1+ TB1+

1394_POW_CON_A 1394_POW_CON_A

TB1+ TPB1

TA1+ TPA1 TA1-

TPB0#

TPB0

TB1TB1+ TA1TA1+

TPB1#

TPB1

4

103

GND16

104

AD26

105

AD25

106

AD24

107

CBE3#

108

IDSEL

109

AD23

110

AD22

111

GND17

112

AD21

113

VCC1

114

VCC/VDD1

115

GND18

116

AD20

117

AD19

118

AD18

119

AD17

120

AD16

121

GND19

122

CBE2#

123

FRAME#

124

IRDY#

125

VCC2

126

TRDY#

127

DEVSEL#

128

STOP#

F_1394

1 2 3

4 5106 7 8

X

Header_2X5_9

HH2X5MZO9H91

Co-Layout

R297 0

*

R299 0

*

R301 0

*

R302 0

*

L2

Dummy

1 4 3

Common Choke 90 Ohm_2L

L4

Dummy

1 4 3

Common Choke 90 Ohm_2L

4

FAB B change

PCIRST#1

3D3V_1394

TPBIAS1

TPA1

TPA1#

TPB1

TPB1#

AD3

81

XTPBIAS1

AD2

80

78

79

XTPA1P

XTPA1M

VDD_1394

D1

B340B-13-FD1B340B-13-F

C459

0.1uF

C0603

TPBIAS0

75

74

77

PVA376PVA2

XTPB1P

XTPB1M

AD1

AD0

EECS

1394_POW_CON_A

CA

F2

*

Fuse 1.5A

AD29

AD30

AD31

AD28

AD27

PCI_REQJ0

PCI_GNTJ0

1394_CLK

102

2

94

95

101

100

97

96

92

93

AD27

AD28

AD2999AD3098AD31

VCC6

GNT#

REQ#

GND15

PCICLK

GND01PERR#2PAR

CBE1#4AD155AD146AD137VCC38GND29AD1210AD1111AD1012AD913AD814CBE0#15GND116AD717AD618AD519VCC420AD421AD322AD223VCC/VDD224GND325GND426AD127AD028EECS29EEDO30SDA/EEDI31SCL/EECK32VCC/VDD333GND534VCC/PWRDET35GND636PME#37NC0

3

AD15

AD14

AD13

AD12

AD11

PCI_C/BE*1

PAR

PERR#

12V_SYS

C454

0.1uF

*

C0603

TA1TB1-

TPB1# TPB1 TPA1# TPA1

TPB1#TB1-

TPA1#

PIRQ#Z

91

PCIRST#

AD10

*

PVA590PVA4

INTA#

AD8

AD9

F1

Fuse 1.5A

REG_FB

REG_OUT

89

88

87

REG_OUT

PCI_C/BE*0

REG_FB

NC1786NC16

AD7

BJT_CTL

82

85

84

GND1483GND13

BJT_CTL

AD5

AD6

AD4

C455

0.1uF

*

C0603

*

3

R272 6.2K

C429 47pF

C0603

TPB0

TPA0#

TPA0

TPB0#

73

71

72

70

XTPA0P

XTPB0P

XTPA0M

XTPB0M

XTPBIAS0

EEDI

EECK

VDD_1394

C456

0.1uF

*

C0603

*

3

+/-1%R0603

*

68

67

GND1269GND11

PWR_DET

R295

R295 1M

1M

+/-5%

R0603

Dummy

C457

0.1uF

C0603

FB13

VCCA_1394

6307=6.34K 6308=6.2K

65

66

PVA1

NC15

XREXT

PHYRESET#

PVD/VDD4

I2CEEN

PVD/VCC5

38

3D3V_1394

GND10

XCPS

PVA0

GND9

NC14 NC13 NC12 NC11 NC10

GND8

GND7

XO

NC9 NC8

NC7 NC6

NC5 NC4 NC3 NC2

NC1

FB13

*

80 Ohm@100MHz

XOUT XIN

R273 1M

Reserved

X3

1 2

24.576MHzX324.576MHz

C437

12pF

U29

*

50V, NPO, +/-5%

C0603

64 63 62

XOUT

61

XIN

60

XI

59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39

VT6308P

6308P

C444

*

1uF

C0603

VDD_1394

R284 0 +/-5%

R0603

Dummy

U30

1 2 3

AT24C02N-2.7V

A0 A1 A2/NC VSS/GND4SDA

+/-5%R0603

*

for cost down, R574R575 can be removed

1394_POW_CON_BACK12V_SYS

D2

CA

B340B-13-FD2B340B-13-F

C458

EC8

0.1uF

100uF

*

16V, +/-20%

C0603

CE20D50H110

C438

12pF

50V, NPO, +/-5%

C0603

8

VCC

7

WP/NC

6

SCL

5

3D3V_SYS

R274

R274 11K

11K

+/-1%

R0603

R275

1K

+-5%

r0603h6

VCCA_1394

3D3V_1394

R277

4.7K

r0603h6

+/-5%

PCI_PME* 16,22,23,24

3D3V_SYS

EECK EEDI

1394_POW_CON_BACK

TB0TB0+

TA0TA0+

2

FB L0805 70 Ohm

1394_POW_CON_A

R291

R292

4.7K

+/-5%

r0603h6

2

3D3V_SYS 3D3V_1394

FB14

*

C430

4.7uF

*

Dummy

C1206

VCCA_1394

NEAR EACH POWER PIN

C439

0.1uF

*

C0603

VDD_1394

NEAR EACH POWER PIN

C445

0.1uF

*

C0603

REG_OUT

R279

REG_FB

0 r0603h6

for cost down, Q117 R568 can be removed

BJT_CTL

6308 pop

PWR_DET

*

1394_USB

1394VCC 1394D01394D0+

1394D11394D1+ 1394GND GND5

GND6 GND7 GND8

USBV1

USBVCC0

-USBD0

+USBD0

-USBD1

+USBD1

GND3 GND0 GND9 GND2 GND4 GND1

USBX2_1394

1394_USB

5 1

2 3 6 7 17

4 15 16 18 8

9 11 12

13 14 10 19

20 21 22

R271 0

C431

0.1uF

*

C0603

C440

0.1uF

*

C0603

C446

0.1uF

*

C0603

3D3V_SYS

6308 pop

EC

Q9

B

X_2SB1197K

Dummy

+/-5%

*

@6308

R285 4.7K

R0603 +/-5%

R293

C453

4.7K

0.1uF

r0603h6

C0603

+/-5%

USB_POWER_1394

1

VDD_1394

@6307

C432

0.1uF

*

C0603

C441

0.1uF

*

C0603

C447

0.1uF

*

C0603

C433

0.1uF

C0603

C442

0.1uF

C0603

C448

0.1uF

C0603

C434

0.1uF

*

C0603

C443

10uF

*

6.3V, X5R, +/-10%

C1206

Dummy

EECS

C435

C436

0.1uF

*

0.1uF

*

C0603

R278 4.7K R0603 +/-5%

Dummy

3D3V_SYS

use internal eeprom, pull high

VDD_1394

2.5V

3D3V_SYS

Dummy

3D3V_1394

@6308

R293-S1

R293-S1 0

0

+/-5%

N/A@6307

USB_8*_R 28

USB_8_R 28

USB_9*_R 28

USB_9_R 28

TECHNOLOGY COPR.

Title

Document Number Rev

Date: Sheet

Date: Sheet of

VT6308

CK804A07

1

TECHNOLOGY COPR.

25 41Tuesday, October 31, 2006

A

of

1

MII_MDC

RGMII_MDC18

MII_MDIO

RGMII_MDIO18

CP-MII_CRS18

CP-MII_COL18

CP-MII_RXER18

RGMII_RXD[3..0]18

RGMII_RXCTL18

RGMII_TXD[3..0]18

A A

RGMII_TXCLK18 RGMII_TXCTL18

RGMII_25MHZ18

NC FOR 25MHZ INPUT

B B

C C

CTRL15

D D

R685 0R685 0

3D3V_DUAL

B

*

EC

Q10

Q10 2SB1188

2SB1188

@8211BL

EC10

100uF

*

16V, +/-20%

CE20D50H110

@8211BL

RGMII_RXD0 RGMII_RXD1 RGMII_RXD2 RGMII_RXD3RGMII_RXD3

RGMII_TXD0 RGMII_TXD1 RGMII_TXD2 RGMII_TXD3

X4

1 2

Dummy

XTAL-25MHz

C464

18pF

50V, NPO, +/-5%

C0603

Dummy

RGMII_RXCLK18

C481

10uF

*

C1206

Dummy

config9 CP-MII_RXER CP-MII_COL CP-MII_CRS config7

1. RTL8211BL:Hardware config 1111=NWay,advertise all capabilities,prefer Slave

2.RTL8201:R714,R716,R720,R721(NC)

XTAL1

XTAL2

C465

18pF

*

50V, NPO, +/-5%

C0603

Dummy

C460

22pF

*

C0603

Dummy

RTL8201CL/CP: R704(2K) RTL8211BL: R704 (2.49K)

C471

C470

0.1uF

*

C0603

@8211BL

CP4

C482

0.1uF

*

C0603

@8211BL

2

RGMII_RESET*

R306 4.7K @8211BLR306 4.7K @8211BL R307 4.7K @8211BLR307 4.7K @8211BL R310 4.7K

R310 4.7K R309 4.7K @8211BLR309 4.7K @8211BL R308 4.7K @8211BLR308 4.7K @8211BL

R718 is reserved for 8201CL/CP LED Mode Change to compatible with BL pop, CL dummy

R718 0R718 0

RSET

C472

0.1uF

*

C0603

@8211BL

1 2

C483

X_COPPER

0.1uF

dummy

*

C0603

@8211BL

C755

22pF

*

C0603

Dummy

R331 2.49K

C473

0.1uF

C0603

@8211BL

R304

4.7K

+/-5%

r0603h6

3D3V_DUAL

Dummy

RGMII_RXCLK_R

DVDD15

AVDD15

RGMII_RESET* 18

+/-1%R0603

3

RSET

1

RSET

2

*

RN27

1 3 5 7 8

4.7K

+/-5%

8P4R0603

@8211BL

3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

2 4 6

config0

@8211BL

R326

TXDLY

4.7K r0603h6

R330

RXDLY

4.7K r0603h6

C484

4.7uF

*

25V, Y5V, +80%/-20%

NC1 AVDD181 MDIP0 MDIN0 AGND1 NC2 AVDD182 MDIP1 MDIN1 AGND2 AVDD331 CTRL18 AGND3 AVDD183 MDIP2 MDIN2 AGND4 AVDD184 MDIP3 MDIN3 AGND5 NC3 NC4 GND1

U31

Dummy

*

C485

0.1uF

C0603

@8211BL

AVDD18 GBIT_MDI0+ GBIT_MDI0GND

AVDD18 GBIT_MDI1+ GBIT_MDI1GND AVDD33 CTRL18 GND AVDD18 GBIT_MDI2+ GBIT_MDI2GND AVDD18 GBIT_MDI3+ GBIT_MDI3GND

GND

config4 config3 config2 config1

3D3V_DUAL

R317 4.7K

RTL8211B PHY address is 00001 RTL8201:R715,RN107(NC)

R327

+/-5%

R327

+/-5%

4.7K r0603h6

@8211BL

R329

+/-5%

R329

+/-5%

4.7K r0603h6

@8211BL

4.7K r0603h6

@8211BL

TXDLY/RXDLY is for RTL8211BL RGMII use Without Tx/Rx delay:R140,R142(NC) RTL8201:R723,R719,R724,R725 (NC)

3D3V_DUAL

CTRL18

EC

Q11

B

2SB1188

@8211BL

EC11

100uF

*

16V, +/-20%

CE20D50H110

@8211BL

4

GND

XTAL2

XTAL1

AVDD33

93

XTAL192XTAL2

AGND6

RGMII_RXD3

RGMII_RXCLK_R

DVDD33

3D3V_DUAL

C487

0.1uF

C0603

@8211BL

GND

AVDD15

config0

config1

config2

DVDD33

config3

91

AVDD332

90

RGMII_TXCLK

RGMII_TXD0

LED_100 LED_1000 LED_TX

*

88

NC889NC9

RGMII_TXD1

C488

0.1uF

C0603

@8211BL

config4

86

82

87

81

85

GND16

GND17

LED_TX LED_1000 LED_100

config[4]80config[3]

config[2]83config[1]84config[0]

DVDD335

DVDD154

RGMII_MDIO

GND

RGMII_TXD2

RGMII_TXD3

RGMII_TXCTL

RGMII_MDC

GREEN = LINK UP BLINKING = TX/RX ACTIVITY

C489

0.1uF

*

C0603

@8211BL

RXDLY

TXDLY

78

79

RXDLY

GND

DVDD15

GND

CTRL15

AVDD15

96

100

94

97

95

NC1098NC1199NC12

AGND7

CRTL15

AVDD15

RTL8211B_100pin

RXD027GND228GND332RXD333RXC34DVDD33235TX_CLK36TXD037TXD138GND439TXD240TXD341TX_CTL(TXEN)42GND543MDC44GND645MDIO46GND747DVDD15148config[9]49DVDD333

RX_CTL(RXDV)26DVDD33129RXD231RXD1

30

GND

RGMII_RXD0

RGMII_RXCTL

RGMII_RXD2

RGMII_RXD1

DVDD33

+/-5%

Dummy

C486

0.1uF

*

C0603

@8211BL

GND

77

76

TXDLY

GND15

LED_LINK10

LED_LINK100

CRS(config5)

LED_LINK1000

LED_DUPLEX

RX_ER(config8)

50

config9

DVDD33

GND14

DVDD334

GND13 GND12

COL(config6)

DVDD153

GND11

DVDD33

CLK125 LED_RX LED_TX

PHYRSTB

config[7]

GND10

DVDD152

GND9 GND8

R663 0

R663 0 R664 0R664 0 R665 0

R665 0 R666 0

R666 0 R667 0

R667 0

R668 0

Dummy

R669 0

Dummy

R670 0R670 0 R671 0

R671 0

Dummy

R672 0

Dummy

AVDD18

NC7 NC6 NC5

RTL8211BL-GR

Dummy

Dummy Dummy

Dummy

3D3V_DUAL

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

*

5

3D3V_DUAL

R305

NV suggest

1.5K

+/-5%

R0603

RGMII_MDIO

GND

DVDD33 LED_100 GND CP-MII_CRS GND CP-MII_COL DVDD15 GND LED_1000

DVDD33

LED_TX RGMII_RESET* config7 GND DVDD15 GND GND CP-MII_RXER

OFF = LINK 10 Mbps GREEN = LINK 100 Mbps YELLOW = LINK 1000 Mbps

LED caps. should be placed next to connector

CP3

EC9

100uF

16V, +/-20%

CE20D50H110

ACTIVE LED

1 2

X_COPPER

*

dummy

1 2

CP5

X_COPPER

dummy

50V, X7R, +/-10%

3D3V_DUAL 3D3V_DUAL

R333

330

+-5%

r0603h6

50V, X7R, +/-10%

C474

0.1uF

C0603

3D3V_DUAL 3D3V_DUAL

C680

470pF

C0402

Dummy

C682

470pF

C0402

C475

0.1uF

*

C0603

C491

0.1uF

*

C0603

R318

330

+-5%

r0603h6

330

+-5%

r0603h6

*

R334

*

GBIT_MDI0+ GBIT_MDI0GBIT_MDI1+ GBIT_MDI1GBIT_MDI2+ GBIT_MDI2GBIT_MDI3+ GBIT_MDI3-

*

C476

0.1uF

C0603

C492

0.1uF

*

C0603

R319

R319 330

330

+/-5%

R0603

Dummy

C679

470pF

C0402

50V, X7R, +/-10%

*

C477

0.1uF

*

C0603

*

6

C681

470pF

C0402

C683

470pF

C0402

50V, X7R, +/-10%

C478

0.1uF

*

C0603

AVDD33

C493

0.1uF

C0603

3D3V_DUAL

R316

*

0

Dummy

+/-5%

r0603h6

*

Dummy

C479

0.1uF

C0603

7

Giga RU1-250A9WGF/JFM38U1A-21C7-4F JFM38U1A-21U5-4F(NWInG)

C466

1nF

*

50V, X7R, +/-10%

C0603

@8201

*

R335

R335 0

0

+/-5%

r0603h6

@8201

22 21

9 10 11 12 13 14 15 16 17 18

20 19

JFM38U1A-21U5-4F

C480

0.1uF

C0603

GRN_LED

USBX2_RJ45 Gigabit LAN

YLW_LED

GRN_LED

1G Conn P/N : JFM31U1A-01U5W

DVDD33

RJ45-MJ2

USB-2

USB-1

NIC_USB

ぃ癸嘿

27 28 29 30

1 5

2 6

3 7

4 8

23 24 25 26

*

C467

0.1uF

C0603

USB_POWER_NIC

USB_4*_R 28 USB_5*_R 28

USB_4_R 28 USB_5_R 28

8

TECHNOLOGY COPR.

Title

Document Number Rev

Date: Sheet

Date: Sheet of

1

2

3

4

5

6

Date: Sheet of

7

LAN RTL8211BL / RTL8201CL

CK804A07

TECHNOLOGY COPR.

of

26 41Tuesday, October 31, 2006

8

A

5

4

3

2

1

R338

*

0

+/-5%

r0603h6

R681

*

0

+/-5%

r0603h6

BOARD_ID0 BOARD_ID1 BOARD_ID2 BOARD_ID3 BOARD_ID4

3D3V_SYS

R339

4.7K

+/-5%

r0603h6

BOARD_ID4 BOARD_ID3 BOARD_ID2 BOARD_ID1 BOARD_ID0

R341

*

0

+/-5%

r0603h6

*

3D3V_SYS

C494

0.1uF

*

C0603

3D3V_SYS

R707

8.2K

Dummy

+/-5%

r0603h6

R712

8.2K

Dummy

+/-5%

r0603h6

C495

0.1uF

C0603

Dummy

*

R708

8.2K

+/-5%

r0603h6

R713

8.2K

+/-5%

r0603h6

C496

0.1uF

C0603

Dummy

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

R709

8.2K

+/-5%

r0603h6

R714

8.2K

+/-5%

r0603h6

Dummy

U52_1

PLCC

PLCC 32pin

32pin

Socket

D D

PLCC-32-SKT

R337 0

FLASH_WP*18 FLASH_TBL*18

R337 0 R342 0

R342 0

ICH_SPI_WPJ

*

* *

*

3D3V_SYS

r0603h6+/-5%

r0603h6+/-5% r0603h6+/-5%

r0603h6+/-5%

R343 0

R340

4.7K

+/-5%

r0603h6

Dummy

*

R336

4.7K

+/-5%

r0603h6

r0603h6+/-5%

Default

C C

WP_EN

Unlock Lock

WP_EN

(1-2) (2-3)

LPCRST_FLASH*16

1 2 3

LPC_AD[3..0]16,32

LPC_FRAME*16,32 PCI_CLKLPC16

WP_EN

1 2 3

Header_1X3

Dummy

LPC_FRAME* PCI_CLKLPC LPCRST_FLASH*

LPC_AD[3..0]

TBL_EN(1-2)1

1 2 3

TBL_EN

1 2 3

Header_1X3

TBL_EN(1-2)1

Jumper_2P-Blue

Confirm default setting

SPI Interface

FWH_WP* FWH_TBL*

U2G1

SST49LF004B

SST49LF004B PLCC32J

PLCC32J

4MB FLASH

LAD0

LAD0 LAD1

LAD1 LAD2

LAD2 LAD3

LAD3

FRAME*

LCLK

RESET*

WP*

TBL*

MODE

MODE GND

GND GND

GND

I115

4MB FLASH

LPC_AD0

0

13

LPC_AD1

1

14

LPC_AD2

2

15

LPC_AD3

3

17 23 24 31

2

7 8

29 28 16

INIT*

GPI0

GPI0 GPI1

GPI1 GPI2

GPI2 GPI3

GPI3 GPI4

GPI4

1

NC

22

NC

26

NC

27

NC

UNNAMED_38_FLASH4MBIT_I115_INIT

18

RES

RES RES

RES

VDD

VDD VDD

VDD

ID0

ID0 ID1

ID1 ID2

ID2 ID3

ID3

Dummy

19 20 21

25 32

6 5 4 3 30

12 11 10 9

U12, U27 Co-layout

3D3V_DUAL

R345

Dummy

+/-5%

r0603h6

ICH_SPI_HOLDJ

close to ICH7

10K

Dummy

R346

10K

+/-5%

r0603h6

R353

R353 47

47

+/-5%

R0603

3D3V_DUAL

R344

10K

Dummy

+/-5%

r0603h6

B B

SPI_CE32

SPI_SCK32

SPI_SO232 SPI_SO132

R350 0

R350 0 R352 0

R352 0

Dummy

*

Dummy

*

SPI_SI32

ICH_SPI_CSJ ICH_SPI_CLK ICH_SPI_MOSI ICH_SPI_MISO

close to ICH7 within 100 mils

R349 47

R349 47 R351 47

R351 47

Dummy

Dummy Dummy

Dummy

U33

8

VCC

7

HOLD#

6

SCK

5

SI

SST25VF020

Dummy

U34

Dummy

8

VCC

7

HOLD#

6

SCK

5

SI

SST25LF040A

SOP8JG

CE#

SO WP# GND

SOP8JA

CE#

SO WP# GND

1 2 3 4

Dummy

1 2 3 4

SPI Population Options

ICH_SPI_CSJ

ICH_SPI_WPJ

3D3V_DUAL

C497

0.1uF

*

50V, Y5V, +80%/-20%

C0603

ICH_SPI_HOLDJ

ICH_SPI_WPJ

R347

3.3K

Dummy

+/-5%

R0603

R348

3.3K

Dummy

+/-5%

R0603

8P4R0603

+/-5%

8.2K

7 8 5 3

*

1

RN47

R710

8.2K

+/-5%

r0603h6

R715

8.2K

+/-5%

r0603h6

3D3V_SYS

6 4 2

Dummy

R711

8.2K

+/-5%

r0603h6

R716

8.2K

+/-5%

r0603h6

SPI

Dummy

3D3V_SYS

H9

H8

4 3 2

H8 Mounting Hole

Mounting Hole

7 8 9

mh40x80_8

3

5

6

4 3 2

1

H2

H1

H1 Mounting Hole

Mounting Hole

5

6

4

7

3

A A

8 9

mh40x80_8

2

1

5

H2 Mounting Hole

Mounting Hole

7 8 9

mh40x80_8

5

6

1

4 3 2

mh40x80_8

GND_AUDIO

H3

H3 Mounting Hole

Mounting Hole

6

7 8 9

5

1

4 3 2

mh40x80_8

H4

H4 Mounting Hole

Mounting Hole

7 8 9

6

5

1

4

H5

H5 Mounting Hole

Mounting Hole

4 3 2

mh40x80_8

6

7 8 9

5

1

4 3 2

mh40x80_8

H6

H6 Mounting Hole

Mounting Hole

5

6

7 8 9

1

4 3 2

mh40x80_8

H7

H7 Mounting Hole

Mounting Hole

5

6

7 8 9

1

H9 Mounting Hole

Mounting Hole

7 8 9

mh40x80_8

H10

H10 Mounting Hole

Mounting Hole

5

6

4 3 2

1

mh40x80_8

5

6

4

7

3

8

2

9

1

Title

Document Number Rev

Date: Sheet

2

Date: Sheet

ICH_SPI_HOLDJ ICH_SPI_CLK ICH_SPI_MOSI

FWH / SPI

1 2 3 5 7 8

Header_2X4

SPI

CK804A07

ICH_SPI_CSJ ICH_SPI_MISO

4

TECHNOLOGY COPR.

27 41Tuesday, October 31, 2006

1

A

of

A

5

5V_DUALUSB_POWER_1394 USB_POWER_NIC 5V_DUAL

F3

F3 Fuse 1.5A

Fuse 1.5A

*

D D

*

USB_POWER_1394 USB_POWER_NIC

C499

C498

470pF

*

50V, X7R, +/-10%

C0402

C499

470pF

*

50V, X7R, +/-10%

C0402

*

R354

EC12

5.1K

470uF

r0603h6

16V, +/-20%

ce35d80h125

+/-1%

4

C500

10K

C500

0.1uF

*

50V, Y5V, +80%/-20%

C0603

R356

+/-5%

r0603h6

3

F4

F4 Fuse 1.5A

Fuse 1.5A

*

C501

470pF

*

50V, X7R, +/-10%

C0402

*

2

C502

470pF

50V, X7R, +/-10%

C0402

EC13

470uF

*

16V, +/-20%

ce35d80h125

R355

5.1K

r0603h6

+/-1%

R357

10K

+/-5%

r0603h6

C503

0.1uF

*

50V, Y5V, +80%/-20%

C0603

1

USB_BKPNL_3_2_OC* 18USB_BKPNL_5_4_OC* 18

F6

F6 Fuse 1.5A

Fuse 1.5A

4 6

10

USB_4

R359 0

USB_4*

R361 0

USB_5

R363 0

USB_5*

R365 0

L6

1 4 3

Common Choke 90 Ohm_2L

Common Choke 90 Ohm_2L L8

L8

1 4 3

Common Choke 90 Ohm_2L

C508

470pF

*

50V, X7R, +/-10%

C0402

USB_6*USB_0 USB_6

USB_9

R358 0

USB_9*

R360 0

USB_8

R362 0

USB_8*

R364 0

L5

1 4 3

Common Choke 90 Ohm_2L

Common Choke 90 Ohm_2L L7

L7

1 4 3

Common Choke 90 Ohm_2L

50V, X7R, +/-10%

C505

470pF

*

C0402

USB_1* USB_1

USB_0*

USB_9*18 USB_918

USB_8*18 USB_818

5V_DUAL

F5

F5 Fuse 1.5A

Fuse 1.5A

*

C504

470pF

*

50V, X7R, +/-10%

C0402

F_USB1

1 2 3

4

5

6

7 8

10

X

Header_2X5_9

HH2X5MZO9H91

C C

B B

USB_0*18 USB_018

Dummy

*

Dummy

*

Dummy

*

Dummy

*

USB_9_R USB_9*_R USB_8_R USB_8*_R

2

EC14

470uF

*

16V, +/-20%

ce35d80h125

USB_1* 18 USB_1 18

USB_9*_R USB_9_R

USB_8*_R USB_8_R

R366

5.1K

r0603h6

+/-1%

USB_9*_R 25

USB_9_R 25

USB_8*_R 25

USB_8_R 25

R368

10K

*

+/-5%

r0603h6

FRONT PANEL USB

C506

0.1uF

50V, Y5V, +80%/-20%

C0603

USB_FNTPNL_1_0_OC* 18

USB_7*18 USB_718

USB_7* USB_7

USB_418 USB_4*18

USB_518 USB_5*18

5V_DUAL

*

C507

470pF

*

50V, X7R, +/-10%

C0402

F_USB2

1 2 3 5 7 8

X

Header_2X5_9

HH2X5MZO9H91

Dummy

*

Dummy

*

Dummy

*

Dummy

*

USB_4_R USB_4*_R USB_5_R USB_5*_R

USB_4_R

2

USB_4*_R

USB_5_R

2

USB_5*_R

EC15

470uF

*

16V, +/-20%

ce35d80h125

USB_6* 18 USB_6 18

R367

5.1K

r0603h6

+/-1%

USB_4_R 26

USB_4*_R 26

USB_5_R 26

USB_5*_R 26

R369

10K

*

+/-5%

r0603h6

C509

0.1uF

50V, Y5V, +80%/-20%

C0603

USB_FNTPNL_6_7_OC* 18

U35

A A

1 2 3

IP4220CZ6

USB_0*USB_0

6 5 4

5

5V_DUAL 5V_DUAL 5V_DUAL 5V_DUAL

USB_1*USB_1

U36

1 2 3

IP4220CZ6

USB_6*USB_6

6 5

USB_7*USB_7

4

U37

1 2 3

IP4220CZ6

USB_8*USB_8

6 5

USB_9*USB_9

4

3

U38

1 2 3

IP4220CZ6

USB_4*USB_4

6 5

USB_5*USB_5

4

TECHNOLOGY COPR.

Title

Document Number Rev

Date: Sheet

2

Date: Sheet

USB CONNECTORS

CK804A07

TECHNOLOGY COPR.

of

28 41Tuesday, October 31, 2006

of

28 41Tuesday, October 31, 2006

of

28 41Tuesday, October 31, 2006

1

A

5

4

3

2

1

IDE_PDD[15..0]17

IDE_PDD7 IDE_PDD6

D D

R373

33

IDE_RSTJ16

IDE_DREQ_P17 IDE_IOW_PJ17 IDE_IOR_PJ17

IDE_IORDY_P17 IDE_DACK_PJ17

IDE_INTR_P17 IDE_ADDR_P117 IDE_ADDR_P017 IDE_CS1_PJ17

P_HDLEDJ40

IDE_CS3_PJ17

C C

IDE_ADDR_P217

IDE_DREQ_P IDE_IOW_P# IDE_IOR_P# IDE_IORDY_P IDE_DACK_P# IDE_INTR_P IDE_ADDR_P1 IDE_ADDR_P0 IDE_CS1_P# P_HDLED#

IDE_CS3_P#

IDE_ADDR_P2

33

+/-5%

r0603h6

3D3V_SYS 3D3V_SYS

R371

4.7K

+/-5%

r0603h6

R375

+/-5%

r0603h6

5.6K

R372

Dummy

+/-5%

r0603h6

8.2K

R376

10K

+/-5%

r0603h6

IDE_PDD5 IDE_PDD4 IDE_PDD3 IDE_PDD2 IDE_PDD1 IDE_PDD0

IDE_SDD[15..0]17

3D3V_SYS

R380

4.7K

+/-5%

r0603h6

R378

33

B B

IDE_RSTJ16 IDE_DREQ_S17

IDE_IOW_SJ17 IDE_IOR_SJ17 IDE_IORDY_S17 IDE_DACK_SJ17 IDE_INTR_S17 IDE_ADDR_S117 IDE_ADDR_S017 IDE_CS1_SJ17 S_HDLEDJ40

IDE_CS3_SJ17 IDE_ADDR_S217

IDE_DREQ_S IDE_IOW_S# IDE_IOR_S# IDE_IORDY_S IDE_DACK_S# IDE_INTR_S IDE_ADDR_S1 IDE_ADDR_S0 IDE_CS1_S# S_HDLED#

IDE_CS3_S# IDE_ADDR_S2

33

+/-5%

r0603h6

R382

5.6K

+/-5%

r0603h6

R377

Dummy

+/-5%

r0603h6

8.2K

R383

10K

+/-5%

r0603h6

IDE_SDD7 IDE_SDD6 IDE_SDD5 IDE_SDD4 IDE_SDD3 IDE_SDD2 IDE_SDD1 IDE_SDD0

IDE_PDD[15..0]

PIDE

IDE_HDR

3 4

DD7

5 6

DD6

7 8

DD5

9 10

DD4

11 12

DD3

13 14

DD2

15 16

DD1

17 18

DD0

1

RESET*

21

DMARQ

23

DIOW*

25 27

IORDY

29

DMACK*

31

INTRQ

33

DA1

35

DA0

37

CS0*

39

DASP*

32

NC GND

I268

DD8

DD8 DD9

DD9

DD10

DD10 DD11

DD11 DD12

DD12 DD13

DD13 DD14

DD14 DD15

DD15

CSEL

PDIAG*DIOR*

DA2

CS1*

GND

GND GND

GND

IDE40MZO20

IDE_SDD[15..0]

SIDE

IDE_HDR

3 4

DD7

5 6

DD6

7 8

DD5

9 10

DD4

11 12

DD3

13 14

DD2

15 16

DD1

17 18

DD0

1

RESET*

21

DMARQ

23

DIOW*

25 27

IORDY

29

DMACK*

31

INTRQ

33

DA1

35

DA0

37

CS0*

39

DASP*

32

NC GND

I268

DD8

DD8 DD9

DD9

DD10

DD10 DD11

DD11 DD12

DD12 DD13

DD13 DD14

DD14 DD15

DD15

CSEL

PDIAG*DIOR*

DA2

CS1*

GND

GND GND

GND

IDE40MZO20

R370

10K

+/-5%

r0603h6

IDE_PDD8 IDE_PDD9 IDE_PDD10 IDE_PDD11 IDE_PDD12 IDE_PDD13 IDE_PDD14 IDE_PDD15

IDE_PDD7

28

34 36 38

2 19 22 24 26 30 40

IDE_SDD8 IDE_SDD9 IDE_SDD10 IDE_SDD11 IDE_SDD12 IDE_SDD13 IDE_SDD14 IDE_SDD15

CBLE_DET_P

R374

15K

+/-5%

r0603h6

IDE_SDD7

CBLE_DET_P 17

R379

10K

+/-5%

r0603h6

28

34 36 38

2 19 22 24 26 30 40

CBLE_DET_S

R381

15K

+/-5%

r0603h6

CBLE_DET_S 17

A A

TECHNOLOGY COPR.

Title

Document Number Rev

Date: Sheet

5

4

3

2

Date: Sheet

IDE CONNECTORS

CK804A07

TECHNOLOGY COPR.

of

29 41Tuesday, October 31, 2006

of

29 41Tuesday, October 31, 2006

of

29 41Tuesday, October 31, 2006

1

A

5

3D3V_SYS

FB26

FB26 FB L0805 70 Ohm

FB L0805 70 Ohm

*

D D

10V, Y5V, +80%/-20%

AC97CLK18

AC_RST*18

AC_BITCLK18 AC_SYNC18

AC_SDIN_018 AC_SDOUT18

C C

CD_GND31

SPDIF_OUT31

R673 22R673 22

JD231 JD131

CD_L31 CD_R31

MIC131 MIC231

*

C685

C729

*

Reserved

C689 22pF

*

C690 22pF

*

C691 22pF

*

* *

*

C729

0.1uF

+/-10%

c0603h10

C0603

50V, NPO, +/-5%

C0603

50V, NPO, +/-5%

C0603

50V, NPO, +/-5%

AUX_L AUX_R

LINE_IN_L LINE_IN_R

JD5

C684

10uF

C0805

C693 2.2uF C0805 16V, Y5V, +80%/-20%

C693 2.2uF C0805 16V, Y5V, +80%/-20% C694 1uF 16V, Y5V, +80%/-20%C0603

C694 1uF 16V, Y5V, +80%/-20%C0603 C695 2.2uF C0805 16V, Y5V, +80%/-20%

C695 2.2uF C0805 16V, Y5V, +80%/-20% C697 2.2uF C0805 16V, Y5V, +80%/-20%

C697 2.2uF C0805 16V, Y5V, +80%/-20% C696 2.2uF C0805 16V, Y5V, +80%/-20%

C696 2.2uF C0805 16V, Y5V, +80%/-20%

C685

0.1uF

50V, Y5V, +80%/-20%

C0603

AC97_BEEP

GND_AUDIO

*

C701

*

1uF

C0603

Dummy

4

C686

50V, X7R, +/-10%

3 2

11

6

10

8 5

12 13 14 15 16 17 18 19 20 21 22 23 24 47 48

*

10nF

C0603

XTL_OUT XTL_IN

RESET# BIT_CLK SYNC SDATA_IN SDATA_OUT

PC_BEEP PHONE AUX_L AUX_R JD2 JD1 CD_L CD_GND CD_R MIC1 MIC2 LINE_IN_L LINE_IN_R SPDIFI(EAPD for 655) SPDIFO

@653

5V_AUDIO3D3V_AUDIO

1

DVdd1

ALC653-GR

GND_AUDIO GND_AUDIO

9

25

38

AVdd1

AVdd2

DVdd2

DVss1

DVss2

4

7

26

GND_AUDIO

C687

*

0.1uF

50V, Y5V, +80%/-20%

C0603

FRONT_OUT_L

FRONT_OUT_R

MONO_OUT

Front-MIC1

SURR-OUT-L

SURR-OUT-R

CEN-OUT

LFE-OUT

JD0(GPIO0)

XTLSEL

VREFOUT

Front-MIC2

AVss1

AVss2

ALC653-GR

42

NC1

NC2

VREF AFILT1 AFILT2

VRDA

3

C688

*

0.1uF

50V, Y5V, +80%/-20%

C0603

U53

Default: ALC 850, and use ALC655 Symbol

EC54 100uF

35 36 37 33 34 39 40 41 43 44 45 46

28 27 29 30 31 32

EC55 100uF

C692 2.2uF 16V, Y5V, +80%/-20%

FAB B change

R674

R674 0

0

Dummy

*

+/-5%

r0603h6

C698 1uFC698 1uF C699 1uFC699 1uF C700 1nF 50V, X7R, +/-10%C0603

C700 1nF 50V, X7R, +/-10%C0603 C702 1nF 50V, X7R, +/-10%C0603

C702 1nF 50V, X7R, +/-10%C0603 C703 1uF 16V, Y5V, +80%/-20%C0603

C703 1uF 16V, Y5V, +80%/-20%C0603 C704 1uF 16V, Y5V, +80%/-20%C0603

C704 1uF 16V, Y5V, +80%/-20%C0603

CE20D50H110

*

CE20D50H110

*

C0805

*

R600

5.6K

+/-5%

r0603h6

*

* *

*

16V, +/-20%

2

FRONT_OUT_L

FRONT_OUT_R

FRONT-MIC1 31

JD3

JD0 31

VREF_AUDIO 31

GND_AUDIO

FRONT_OUT_L 31

FRONT_OUT_R 31

Audio Jack X3

LINE IN C

LINE OUT B

MIC IN

1

A

B B

12V_SYS

Standby Mode: For Power ON/OFF POP Noise

5V_AUDIO

A A

SPEAKER18,40

5V_SB_SYS

D25

D25 SD103AW

SD103AW

C A

EC58

100uF

*

16V, +/-20%

CE20D50H110

GND_AUDIO GND_AUDIO GND_AUDIO

R608

10K

+/-5%

r0603h6

Dummy

5

r0603h6

Dummy

R639

1K

+-5%

r0603h6

C707 1uF

*

GND_AUDIO

*

C709

100pF

C0603

50V, NPO, +/-5%

Dummy

1

C730

0.1uF

+/-10%

c0603h10

C0603

Dummy

16V, Y5V, +80%/-20%

*

OUT

GND

2

4

U55

IN

LM78L05

AC97_BEEP

D24

D24 1N4148W

1N4148W

C A

3

C731

EC59

0.1uF

100uF

*

+/-10%

16V, +/-20%

c0603h10

CE20D50H110

Dummy

AUX_L

AUX_R

LINE_IN_L

LINE_IN_R

C706 2.2uF 16V, Y5V, +80%/-20%C0805

*

C708 2.2uF 16V, Y5V, +80%/-20%C0805

*

C710 2.2uF C0805 16V, Y5V, +80%/-20%

*

C711 2.2uF C0805 16V, Y5V, +80%/-20%

*

3

CP9

Dummy

1 2

X_COPPER

GND_AUDIO

AUX_L_CODEC 31

AUX_R_CODEC 31

LINE_IN_L_CODEC 31

LINE_IN_R_CODEC 31

TECHNOLOGY COPR.

Title

Document Number Rev

Date: Sheet

2

Date: Sheet

AUDIO ALC653/850

CK804A07

TECHNOLOGY COPR.

of

30 41Tuesday, October 31, 2006

of

30 41Tuesday, October 31, 2006

of

30 41Tuesday, October 31, 2006

1

A

5

4

3

2

1

D D

MIC230

MIC130

C C

LINE_IN_R_CODEC30

LINE_IN_L_CODEC30

B B

FRONT-MIC130

5V_AUDIO

VREF_AUDIO30

FRONT_OUT_R30 FRONT_OUT_L30

VREF_AUDIO30

3

1

R613

4.7K

+/-5%

r0603h6

R615

R615 22K

22K

r0603h6

+/-5%

R628 100

+/-5%

r0603h6

R633

10K

+/-5%

R634 2K +/-5%

r0603h6

Dummy

JUMPER(F_AUDIO:9-10)1

Jumper_2P-Blue

D26

D26 BAT54A

BAT54A

2

R614

4.7K

+/-5%

r0603h6

FB27 FB L0603 80 Ohm

*

FB28 FB L0603 80 Ohm

*

R616

22K

r0603h6

+/-5%

C714

*

100pF

50V, NPO, +/-5%

FB L0603 80 Ohm

FB31

*

FB32 FB L0603 80 Ohm

*

R626

22K

+/-5%

r0603h6

GND_AUDIO GND_AUDIO

JUMPER(F_AUDIO:5-6)1

Jumper_2P-Blue

*

R627

22K

+/-5%

r0603h6

R675

R675 0

0

+/-5%

r0603h6

C725

100pF

50V, NPO, +/-5%

C0603

F_AUDIO

1 2 3 5106 7

X

9

Header_2X5_8

*

4

C715

*

100pF

50V, NPO, +/-5%

*

CD_L30

CD_GND30

CD_R30

Default: No Smart Jack Funtion

R609

+/-5%

r0603h6

Dummy

M_R_2

5

JDO_1

4 3

M_R_1

2 1

Default: No Smart Jack Funtion

Dummy

L_I_R

35

JD2_1

34 33

L_I_L

32

C726

100pF

50V, NPO, +/-5%

C0603

5V_AUDIO

C732

0.1uF

*

+/-10%

c0603h10

GND_AUDIO

FRONT_RET_R FRONT_RET_L

10K

*

GND_AUDIO

AUDIOA

JACK_AUDX3 Vertical

R619

10K

+/-5%

r0603h6

*

GND_AUDIO

AUDIOC

JACK_AUDX3 Vertical

1 2 3 4

CD-IN

JD0 30

C712

4.7uF

10V, Y5V, +80%/-20%

C0805

Dummy

36 37

GND_AUDIOGND_AUDIO GND_AUDIO GND_AUDIO

C722

4.7uF

10V, Y5V, +80%/-20%

C0805

Dummy

40

CD_IN

5

Header_1X5

Reserved

MIC-IN

(CEN/LFE)

LINE IN

(SURR_OUT)

SPDIF_OUT30

JD2 30

SPDIF_OUT

SPDIF018

Reserved

R637

R637 0

0

*

+/-5%

r0603h6

R638

Dummy*R638

Dummy

0

*

+/-5%

r0603h6

FRONT_RET_R

FRONT_RET_L

5V_SYS

Default: No Smart Jack Funtion

C717

100pF

*

50V, NPO, +/-5%

FR_R

25

JD1_1

24 23

FR_L

22

GND_AUDIO

AUX LINE-IN

FB29 FB L0603 80 Ohm

*

FB30 FB L0603 80 Ohm

*

R618

R617

22K

+/-5%

r0603h6

GND_AUDIO GND_AUDIO GND_AUDIO

AUX_R_CODEC30

AUX_L_CODEC30

SPDIF_OUT

1

3

4

Header_1X4_2

Reserved

SPDIF_OUT

100pF

50V, NPO, +/-5%

C716

*

R610

10K

+/-5%

r0603h6

*

Dummy

GND_AUDIO

AUDIOB

JACK_AUDX3 Vertical

FRONT_OUT

AUX_IN

1 2 3 4

Header_1X4

hauxin4mh136

C713

4.7uF

10V, Y5V, +80%/-20%

C0805

Dummy

38 39

JD1 30

A A

TECHNOLOGY COPR.

Title

Document Number Rev

Date: Sheet of

5

4

3

2

Date: Sheet of

AUDIO CONNECTORS 653/850

CK804A07

1

TECHNOLOGY COPR.

31 41Tuesday, October 31, 2006

A

5

Power On Strapping Options

Disabled.

FAB B change

R437 0

R437 0 R439 0

R439 0

1

Flash I/F Address Segment 1 (FFFE_0000h~FFFF_FFFFh,

0

000F_0000h~000F_FFFFh) is enabled

1

FLH_SO1 is selected as the Serial Flash I/F SO pin.

0

FLH_SO2 is selected as the Serial Flash I/F SO pin. Chip selection in configuration. The output buffers of PCIRST1#, PCIRST2#, PCIRST3#, PCIRST4# and

1

PCIRST5# are open-drain.

0

The output buffers are push-pull.

1

The default value of EC Index 15h / 16h / 17h is 00h

0

The default value of EC Index 15h / 16h / 17h is 40h The threshold voltage of VID is 2.0 / 0.8V

1 0

The threshold voltage of VID is 0.8 / 0.4V

R428 680

R427 680

R430 680

R430 680 R429 680

R429 680

R432 680R432 680 R431 680R431 680

3D3V_SYS

R725

4.7K

+/-5%

r0603h6

AMDSIC

*

Dummy

AMDSID

*

Dummy

3D3V_SYS

3D3V_DUAL

Flashseg1_EN

JP1

JP2

SerFlh_SO_SEL

JP3 --

D D

C C

B B

A A

CHIP_SEL

BUF_SEL

JP4

JP5

FAN_CTL_SEL

VID_ISEL

JP6

Note: If 75232 is connected, please use 680 ohm to

be the pull down resistor value. Since powered by 12V, 75232 has a very strong internal pull-up. It is hard to be pulled low. (Please see specification for detail of power on strapping setting)

CPU_THERM*18

Default DIOD8

CPU_SIC9 CPU_SID9

DescriptionSymbol value

Dummy

Dummy Dummy

Dummy

R686 0

R686 0 R687 0

R687 0

*

R438 0

R438 0 R440 0

R440 0

Dummy

*

Dummy

*

r0603h6

*

* *

*

DCD1J RI1J CTS1J DTR1J RTS1J DSR1J TXD1 RXD1 DCD2J RI2J CTS2J DTR2J RTS2J DSR2J

RXD2

DENSELJ INDEXJ MOTEAJ AMDSIC DRVAJ AMDSID DIRJ STEPJ WDATAJ WGATEJ TK00J WPTJ RDATAJ SIDE1J DSKCHGJ

LRESETJ LPC_DRQ0* SERIRQ LPC_FRAME* LAD0 LAD1 LAD2 LAD3

PCI_CLKSIO

BUF_SIO_CLK IO_PME*

SIO_KBRST* A20GATE KDAT KCLK MDAT MCLK

DCD1J35

RI1J35

CTS1J35

DTR1J35

RTS1J35

DSR1J35

TXD135

RXD135

DCD2J35 RI2J35 CTS2J35 DTR2J35 RTS2J35 DSR2J35 TXD235 RXD235

SPI_SO227 SPI_SCK27 SPI_SI27

PWM_GIOP236

PWM_GIOP136 DDR_GPIO237,41 DDR_GPIO137,41

R435 0 +/-5%

Reserved for SIO Thermal SMI alert .

DENSELJ33 INDEXJ33 MOTEAJ33 DRVBJ33 DRVAJ33 MOTEBJ33 DIRJ33 STEPJ33 WDATAJ33 WGATEJ33 TK00J33 WPTJ33 RDATAJ33 SIDE1J33 DSKCHGJ33

LPCRST_SIO*16

LPC_DRQ0*16

LPC_SERIRQ16

LPC_FRAME*16,27

LPC_AD016,27 LPC_AD116,27 LPC_AD216,27 LPC_AD316,27

24MHz

PCI_CLKSIO16

BUF_SIO_CLK18

SIO_KBRST*18

RN29

1

*

3 5 7 8

10K

+/-5%

8p4r0603h7

IO_PME*18

A20GATE18

KDAT33 KCLK33 MDAT33 MCLK33

SERIRQ

2 4 6

IO_PME*

4

118

DCD1#

119

RI1#

120

CTS1#

121

DTR1#/JP1

122

RTS1#/JP2

123

DSR1#

124

SOUT1/JP3

125

SIN1

126

DCD2#/GP67

127

RI2#/GP66

128

CTS2#/GP65

1

DTR2#/JP4

2

RTS2#/JP5

3

DSR2#/GP64

5

SOUT2/JP6

6

SIN2/GP63

29

MIDI_IN/GP16/SO2

25

JSAB1/GP22/SCK

24

JSAB2/GP23/SI

20

FAN_CTL4/JSBB2/GP27

21

FAN_CTL5/JSBB1/GP26

26

JSACY/GP21

27

JSACX/GP20

28

MIDI_OUT/GP17

51

DENSEL#

63

INDEX#

52

MTRA#

55

ETS_CLK/DRVB#

54

DRVA#

53

ETS_DAT/MTRB#

57

DIR#

58

STEP#

56

WDATA#

60

WGATE#

62

TRK0#

64

WPT#

61

RDATA#

59

HDSEL#

65

DSKCHG#

37

LRESET#

38

LDRQ#

39

SERIRQ

40

LFRAME#

41

LAD0

42

LAD1

43

LAD2

44

LAD3

47

PCICLK

48

PCIRST5#/GP50

49

CLKIN

73

PME#/GP54

45

KRST#/GP62

46

GA20

80

KDAT/GP61

81

KCLK/GP60

82

MDAT/GP57

83

MCLK/GP56

5V_SYS

C558

0.1uF

*

C0603

50V, Y5V, +80%/-20%

5V_SYS

4

35

VCC

GNDD

15

50

*

50V, Y5V, +80%/-20%

5V_SYS

21

FB23

FB23 FB 100 Ohm

FB 100 Ohm +/-25%

+/-25%

C559

10uF

*

C0805

10V, Y5V, +80%/-20%

HMGND

99

AVCC

Serial Port 1/2

IT8716F-S/CX-L

SPI

RESETCON#/CIRTX/GP15/CE_N

MISC.

SCR I/F

PCIRST4#/SCRPSNT#/GP10

Floppy I/F

Hardware Monitoring

LPC I/FKB/MS

GNDD

74

117

FB24

21

FB 100 Ohm

FB 100 Ohm +/-25%

+/-25%

1 2

CP6

X_COPPER

dummy

5V_SYS

C555

C556

0.1uF

*

C0603

50V, Y5V, +80%/-20%

5V_SB_SYS

R426

22

+/-5%

r0603h6

C561

0.1uF

*

+/-10%

c0603h10

67

VCCH

Parallel Port

ERR# SLIN#

ACK# BUSY

Power-on

Control

Power-on

Control

PWROK2/GP41

SUSC#/GP53

PSON#/GP42

PANSWH#/GP43

PWRON#GP44

SUSB#/GP45

RSMRST#/CIRRX/GP55

IRTX/GP47 IRRX/GP46

COPEN#

3VSBSW#/GP40

PCIRST3#/SCRCLK/GP11

PCIRST2#/SCRIO/GP12

PWROK1/SCRPFET#/GP13

PCIRST1#/SCRRST/GP14

VIN3/ATXPG

VIN7/PCIRSTIN#

VREF TMPIN1 TMPIN2

TMPIN3/SO1 FAN_TAC5/JSBCX/GP24 FAN_TAC4/JSBCY/GP25

FAN_CTL3/GP36 FAN_TAC3/GP37 FAN_CTL2/GP51 FAN_TAC2/GP52

FAN_CTL1 FAN_TAC1 GP30/VID0 GP31/VID1 GP32/VID2 GP33/VID3 GP34/VID4 GP35/VID5

VBAT

VIDVCC

GNDA

86

HMGND

C557

0.1uF

*

C0603

50V, Y5V, +80%/-20%

U42

116

PD7

115

PD6

114

PD5

113

PD4

112

PD3

111

PD2

110

PD1

109

PD0

108

STB#

107

AFD#

106 105

INIT#

104 103 102 101

PE

100

SLCT

78 77 76 75 72 71

30 85 66 70 68 79

84 34 33 32 31

98

VIN0

97

VIN1

96

VIN2

95 94

VIN4

93

VIN5

92

VIN6

91 90 89 88 87 23 22 12 11 10 9 8 7 19 18 17 16 14 13

69 36

*

VIDVCC

C560

0.1uF

+/-10%

c0603h10

PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

STBJ AFDJ ERRJ INITJ SLINJ ACKJ BUSY PE SLCT

PANSWHJ PWRBTN#

C562

1uF

IRTX

IRRX

COPENJ

S1LED

EXTSMI*

VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VREF TMPIN1 TMPIN2

R689 0

Dummy

R688 0

Dummy

FAN_CTL3 FAN_CTL2

FAN_TAC2 FAN_CTL1 FAN_TAC1

VBAT

3

PD[0..7]

R706 4.7K

*

C0603

Dummy

16V, Y5V, +80%/-20%

*

C565

C565 1uF

1uF

16V, X5R, +/-10%

PD[0..7] 35

STBJ 35 AFDJ 35 ERRJ 35 INITJ 35 SLINJ 35 ACKJ 35 BUSY 35 PE 35 SLCT 35

5V_SB_SYS

S3_LED 40

r0603h6+/-5%

PS_ON# 40

SLP_S3* 18,40

SPI_CE 27 RSMRSTJ 39

S1_LED 40 EXTSMI* 18

SIO_BEEP 40

VIN0 34 VIN1 34 VIN2 34 VIN3 34 VIN4 34 VIN5 34 VIN6 34 VIN7 34

TMPIN1 34

TMPIN2 34 SPI_SO1 27 CORE_GPIO1 38,41 CORE_GPIO2 38,41 FAN_CTL3

PWM_GIOP4 36

FAN_CTL2 34

FAN_TAC2 34 FAN_CTL1 34

FAN_TAC1 34

3V_CPU_VID0 9,41 3V_CPU_VID1 9,41 3V_CPU_VID2 9,41 3V_CPU_VID3 9,41 3V_CPU_VID4 9,41

PWM_GIOP3 36

VBAT

Place C593 close to IT8712 as possible

VIDVCC

Power button input

3D3V_DUAL

R434

4.7K

+/-5%

r0603h6

VBAT

R436

10M

+/-5%

r0603h6

Place C749 close to IT8712, and Do Not remove this 1uF Cap. of VREF.

Default DIOD8

CPU shut down

3D3V_SYS

1D2V_HT

R441

*

0

+/-5%

r0603h6

3D3V_DUAL

EXTSMI*

PWRBTN# 18

output to SB

Near CPU

*

HMGND

R442

R442 0

0

+/-5%

r0603h6

Dummy

R433

4.7K

Dummy

+/-5%

r0603h6

COPENJ 18

VREF 34

C564

1uF

C0603

16V, Y5V, +80%/-20%

Note:

PANSWHJ

2

POWER ON SCHEME

PWBTN#

PWRBTN#

PWRON#

PANSWH#

(75) (76)

Power Bottom in

PANSWH# 40

Near SIO (U22)

C563

0.1uF

*

C0603

50V, Y5V, +80%/-20%

1

CK804

SLP_S3# SLP_S5#

IT8716F

PSIN

(71)

PSON#

ATX Power

Supply

PSON#

(72)

IR Connector

5V_SYS

IRRX

IRTX

IR

1

3

4

5

Header_1X5_2

GPIO NEED PULL HIGH

5V_SYS

RN28

DDR_GPIO1 DDR_GPIO2 CORE_GPIO1 CORE_GPIO2

RN28

1

*

3 5 7 8

10K

Dummy

+/-5%

8p4r0603h7

2 4 6

TECHNOLOGY COPR.

Title

Document Number Rev

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

SIO ITE8716

CK804A07

1

TECHNOLOGY COPR.

of

32 41Tuesday, October 31, 2006

A

5

5V_DUAL

F7

*

KEYBRD_PWR1

Fuse 1.1A

D D

C C

Fuse 1.1A

SIO_KBDATA

KDAT32

SIO_KBCLOCK

KCLK32

SIO_MSDATA SIO_MSDATA_FB

MDAT32

SIO_MSCLOCK

MCLK32

4

RN30

642

4.7K

8P4R0603

135

7 8

+/-5%

*

3

FB25

*

300 Ohm@100MHz

SIO_MSCLOCK_FB

KEYBRD_PWR2

*

SIO_KBCLOCK_FB

*

C566

C567

0.1uF

470pF

*

50V, Y5V, +80%/-20%

50V, X7R, +/-10%

C0603

C0402

BCN1

220pF

50V, NPO, +/-10%

8P4R0603

2

PS2 KB / MS

KB/MS

ps2x2h286

KEYBOARD (PURPLE)

I55

PS2

DATA

DATA NC

NC GND

GND PWR

PWR CLK

CLK NC

NC

DATA

DATA NC

NC GND

GND PWR

PWR CLK

CLK NC

NC

SHLD SHLD SHLD SHLD SHLD

KEYBOARD (PURPLE)

65

4

13 14

15

16

MOUSE (GREEN)

17

12

10

1 2 3 4 5 6

7 8

9 10 11 12

21

8

1

3

11

9

7

5V_SYS

R443

RN31

642

150

B B

DENSELJ32

INDEXJ32 MOTEAJ32 DRVBJ32 DRVAJ32 MOTEBJ32 DIRJ32 STEPJ32 WDATAJ32 WGATEJ32 TK00J32 WPTJ32 RDATAJ32 SIDE1J32 DSKCHGJ32

A A

5

4

SIO_FDD_DRVDEN0

SIO_FDD_INDEX* SIO_FDD_MTR0*

SIO_FDD_DS0* SIO_FDD_DIR*

SIO_FDD_STEP* SIO_FDD_WDATA*

SIO_FDD_TRK0* SIO_FDD_WGATE* SIO_FDD_WRTPRT* SIO_FDD_RDATA*

SIO_FDD_HDSEL* SIO_FDD_DSKCHG*

135

*

150

8P4R0603

7 8

+/-5%

R443 150

150

+/-5%

R0603

3

FLOPPY

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

Header_2X17_3 (FDD)

1

X

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

TECHNOLOGY COPR.

Title

Document Number Rev

Date: Sheet

2

Date: Sheet

FDD / PS2

CK804A07

TECHNOLOGY COPR.

of

33 41Tuesday, October 31, 2006

of

33 41Tuesday, October 31, 2006

of

33 41Tuesday, October 31, 2006

1

A

5

D D

Voltage Monitor

VIN032 VIN132 VIN232 VIN332 VIN432 VIN532 VIN632 VIN732

*

R446

R446 10K

10K

+/-1%

r0603h6

C570

0.1uF

*

50V, Y5V, +80%/-20%

C0603

R447

R448

R449

10K

+/-1%

r0603h6

C571

0.1uF

*

50V, Y5V, +80%/-20%

C0603

R449

10K

6.8K

+/-1%

r0603h6

R457

R457 10K

10K

+/-1%

r0603h6

Dummy

HMGND HMGND HMGND HMGND

C573

C572

0.1uF

*

50V, Y5V, +80%/-20%

C0603

R458

R458 10K

10K

+/-1%

r0603h6

4

12V_SYS+V_CPU 1D5V_CORE 5V_SYS3D3V_SYS 5V_SB_SYS1D8V_STR1D2V_HT

R450

30K

+/-1%

r0603h6

FAB B change

R459

R459 10K

10K

+/-1%

r0603h6

C574

0.1uF

*

50V, Y5V, +80%/-20%

C0603

3D3V_DUAL

R451

R451 10K

10K

Dummy

+/-1%

r0603h6

C575

0.1uF

*

50V, Y5V, +80%/-20%

C0603

R452

R452 10K

10K

+/-1%

r0603h6

R453

R453 10K

10K

+/-1%

r0603h6

C576

0.1uF

*

50V, Y5V, +80%/-20%

C0603

FAB B change

R454

6.8K

Dummy

+/-1%

r0603h6

R460

R460 10K

10K

+/-1%

r0603h6

C577

0.1uF

*

50V, Y5V, +80%/-20%

C0603

HMGND

3

Peak fan current draw: 1.5A Average fan current draw: 1.1A Fan start-up current draw: 2.2A Fan start-up current draw maximum duration: 1.0 second

5V_SYS

R444

4.7K

+/-5%

r0603h6

placed near the LM358 pin 8

R455 10K

FAN_CTL132

R455 10K

+/-5%

r0603h6

C568

10uF

C1206h18

*

Fan header voltage: 12V +/- 10%

U43A

84

3

+

1

2

-

LM358M

R464

20K

+/-5%

r0603h6

LM358M

R461 28K Ohm

C569

*

0.1uF

C0603

RN42

4 2

2.2K

8p4r0603h7

+/-5%

+/-1%

2

R445 100

5786 3

*

B

1

EC22

100uF

16V, +/-20%

CE20D50H110

CPU FAN

Dummy

+/-5%

12V_SYS12V_SYS

EC

4

*

RN32

Dummy

BCP69

*

135

Q16

0

+/-5%

8p4r0603h7

CPU_FAN

Header_1X4

1

New FAN Header Definition pin1. GND pin2. +12V pin3. Sense pin4. Control

642

7 8

4

3

2

1

12V_SYS

CA

D7 1N4148WD71N4148W

C578

470pF

*

50V, X7R, +/-10%

C0402

R462

4.7K

+/-5%

r0603h6

R463 27KR463 27K

R465

22K

+/-5%

r0603h6

FAN_TAC1 32

C C

Thermal Controller

Thermal Diode layout notice: a. Place T.D. close to IT8712F/H. c. Recommanded trace widths & spacings is 10 miles. b. Keep the trace away from; +12V, Fast data bus, CRTs. d. Isolate GNDA, GND.

VREF32

CP7

CPU_THERMDA9

CPU_THERMDC9

Near CPU

B B

TMPIN232

1 2

X_COPPER

X_COPPER CP8

CP8

1 2

X_COPPER

VREF32

C583

*

0.1uF

*

T

+/-10%

c0603h10

HMGND

R476

R476 10K

10K

+/-1%

r0603h6

RT1

10K

+/-5%

R0603

R469

30K

+/-1%

r0603h6

Dummy

C579

3.3nF

*

50V, X7R, +/-10%

C0603

HMGND

TMPIN1 32

5V_SYS

R466

4.7K

+/-5%

r0603h6

placed near the LM358 pin 8

U43B

84

5

+

R474

20K

+/-5%

r0603h6

Dummy

+

6

-

LM358M

R472 28K Ohm

R468 10K

Dummy

FAN_CTL232

Dummy

+/-5%

C580

10uF

Dummy

C1206h18

C581

*

C581

*

0.1uF

C0603

Dummy

R467 100

RN48

5786 3

4

7

1

2

2.2K

8p4r0603h7

+/-5%

Dummy

+/-1%

EC23

100uF

16V, +/-20%

CE20D50H110

*

B

12V_SYS12V_SYS

Dummy

*

+/-5%

EC

4

SYS FAN

642

RN33

BCP69

BCP69 Q17

Q17

*

135

7 8

0

+/-5%

8p4r0603h7

SYS_FAN1

4

3

2

1

Header_1X4

12V_SYS

CA

D8 1N4148WD81N4148W

C582

470pF

*

50V, X7R, +/-10%

C0402

R471

4.7K

+/-5%

r0603h6

R473 27KR473 27K

R475

22K

+/-5%

r0603h6

FAN_TAC2 32

CHIP FAN

12V_SYS

*

FAB B change

C584

0.1uF

C0603

FAN1

3 214

Header_1X3

CA

D9 1N4148WD91N4148W

C585

470pF

*

50V, X7R, +/-10%

C0402

R477

4.7K

+/-5%

r0603h6

R478 27KR478 27K

R479

22K

+/-5%

r0603h6

FAN_TAC3

A A

TECHNOLOGY COPR.

Title

Document Number Rev

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

FAN / HARDWARE MONITOR

CK804A07

1

TECHNOLOGY COPR.

of

34 41Tuesday, October 31, 2006

A

5

4

3

2

1

5V_SYS

1

*

D D

C C

RRTS1J RTXD1 RDTR1J RDCD1J RDSR1J RRXD1 RCTS1J RRI1J

B B

RRTS2J RTXD2 RDTR2J RDCD2J RDSR2J RRXD2 RCTS2J RRI2J

A A

STBJ32

AFDJ32

PD0

PD032

PD1

PD132

INITJ32

PD2

PD232

SLINJ32

PD3

PD332

PD4

PD432

PD5

PD532

PD6

PD632

PD7

PD732

ERRJ32

ACKJ32 BUSY32

PE32

SLCT32

BCN6

220pF

50V, NPO, +/-10%

*

50V, NPO, +/-10%

8P4R0603

BCN8

220pF

50V, NPO, +/-10%

8P4R0603

5

*

3 5 7 8

1

*

3 5 7 8

1

*

3 5 7 8

2 4 6

RN34

22

+/-5%

8P4R0603

RN39

22

+/-5%

8P4R0603

RN40

22

+/-5%

8P4R0603

*

D10

SD103AW

BCN7

220pF

50V, NPO, +/-10%

8P4R0603

BCN9

220pF

50V, NPO, +/-10%

8P4R0603

CA

R481

22K

+/-5%

r0603h6

R482

8.2K

+/-5%

r0603h6

R483

22K

+/-5%

r0603h6

R484

8.2K

+/-5%

r0603h6

PRN13 PRN12 PRN11 PRN10 PRN9 PRN8 PRN7 PRN6 PRN5

PRN17 PRN4 PRN16 PRN3 PRN15 PRN2 PRN14 PRN1

RRI1J RDTR1J RCTS1J RTXD1 RRTS1J RRXD1 RDSR1J RDCD1J

RDCD2J RTXD2

RRTS2J RRI2J

Title

Document Number Rev

Date: Sheet

R480

2.2K

+/-5%

r0603h6

4

RN35

135

*

2.2K

+/-5%

8p4r0603h7

*

-12V_SYS

642

7 8

-12V_SYS

RN36

642

*

135

7 8

2.2K

+/-5%

8p4r0603h7

BCN2

220pF

50V, NPO, +/-10%

*

8P4R0603

12V_SYS 5V_SYS

1

+12V

5

DY1

6

DY2

8

DY3

2

RA1

3

RA2

4

RA3

7

RA4

9

RA5

10

-12V

C591

0.1uF

*

C0603

12V_SYS

1

+12V

5

DY1

6

DY2

8

DY3

2

RA1

3

RA2

4

RA3

7

RA4

9

RA5

10

-12V

C592

0.1uF

*

C0603

RN37

7 8

2.2K

+/-5%

8p4r0603h7

BCN3

220pF

50V, NPO, +/-10%

*

8P4R0603

U44

20

VCC

16

DA1

15

DA2

13

DA3

19

RY1

18

RY2

17

RY3

14

RY4

12

RY5

11

GND

GD75232

U45

20

VCC

16

DA1

15

DA2

13

DA3

19

RY1

18

RY2

17

RY3

14

RY4

12

RY5

11

GND

GD75232

642

*

135

5V_SYS

3

RN38

642

*

135

7 8

2.2K

+/-5%

8p4r0603h7

BCN4

220pF

50V, NPO, +/-10%

*

8P4R0603

RTS1J 32 TXD1 32 DTR1J 32 DCD1J 32 DSR1J 32 RXD1 32 CTS1J 32 RI1J 32

SER_RI*18

RTS2J 32 TXD2 32 DTR2J 32 DCD2J 32 DSR2J 32 RXD2 32 CTS2J 32 RI2J 32

BCN5

*

220pF

50V, NPO, +/-10%

8P4R0603

Q18

2N7002-7-F

Q19

2N7002-7-F

PRN1 PRN14 PRN2 PRN3 PRN16 PRN4 PRN17 PRN5 PRN6 PRN7 PRN8 PRN9 PRN15

PRN10 PRN11 PRN12 PRN13

C588

220pF

PRINT PORT

50V, NPO, +/-5%

C0402

RRI1J

DS

G

RRI2J

DS

G

2

PRT

13 25 12 24 11 23 10 22

9

21

8

26

20

27

7

28

19

6

18

5

17

4

16

3

15

2

14

10

11

CONN-D-SUB

1

COM1

5 9 4 8 3 7 2 6 1

CONN-COM PORT

COM2

1 2 3 5 6 7 9

Hearer_2X5_K10

PRT COM PORT

RRXD2 RDTR2J

4

RDSR2J

RCTS2J

8

CK804A07

*

1

5V_SYS

C586

*

C586

0.1uF

C0603

C587

0.1uF

*

C0603

12V_SYS

C589

0.1uF

*

C0603

TECHNOLOGY COPR.

of

35 41Tuesday, October 31, 2006

of

35 41Tuesday, October 31, 2006

of

35 41Tuesday, October 31, 2006

C590

0.1uF

C0603

A

5

12

JS1 SHORTJS1 SHORT

D D

U46

*

+/-5%

*

+/-1%

*

+/-5%

*

R498

R498 0

0

*

+/-5%

r0603h6

R506

R506 150K

150K

+/-1%

R511

R511 470

470

+/-5%

*

R513

*

C624

18K

47pF

+/-1%

50V, NPO, +/-5%

C0603

C629

*

3.3nF

*

R525

1.54K

+/-1%

R0603

C618

470pF

R521

R521 0

0

+/-5%

r0603h6

13

24 25 26 27 28 23

29

20

21

22

31

30

10

OUTEN

VID0 VID1 VID2 VID3 VID4 VID5

VID_SEL

9

OVP

TC

CS_SEL

6

OFFSET

OSC/FAULT

SGND

SS_END

VSEN

8

FB

7

COMP

OVLOVL

*

0.1uF

C634

+/-10%

FBR

11

VRM_EN

VREG_VID041 VREG_VID141 VREG_VID241 VREG_VID341 VREG_VID441

R494 0

Dummy

R495 100KOhm

Dummy

C602 10nF

Dummy

R497 0

R497 0 C604 10nF

C604 10nF

Dummy

CPU_VLD14

+V_CPU

Dummy

*

R523

6.2K

+/-1%

R0603

R517

R517 51 Ohm

51 Ohm

+/-5%

OVLOVL

3D3V_SYS

Dummy

R524

3.09K

+/-1%

R0603

R507

10K

+/-5%

r0603h6

R678

10K

+/-5%

r0603h6

*

Dummy

C C

B B

CPU_VDD_RUN_FB_H9

CPU_VDD_RUN_FB_L9

R522

R522 12K

12K

Dummy

+/-1%

r0603h6

PWM_GIOP132

A A

PWM_GIOP232 PWM_GIOP332 PWM_GIOP432

r0603h6

R486

*

10

+/-5%

C593

C593 1uF

1uF

5

SGND

C739

470pF

*

50V, X7R, +/-10%

Dummy

C0402

4

C595

C595 1uF

1uF

4

38

35

VCC

PGND3

VCCDR3

L6711TR

FBG

12

R520

R520 51 Ohm

51 Ohm

+/-5%

*

39

PGND2

NC4848ThermalPad

41

R597

2.2

+/-5%

VCCDR2

3

37

NC37

D11

D11 BAT54C

BAT54C

3

PGND1

C596

C596 1uF

1uF

49

1

VCCDR1

2 1

BOOT1

UGATE1

PHASE1

LGATE1

CS1+

BOOT2

UGATE2

PHASE2

LGATE2

CS2+

BOOT3

UGATE3

PHASE3

LGATE3

CS3+

CS1-

CS2-

CS3-

12V_VRM

5V_SB_SYS

45

46

47

2

14

15

44

43

42

40

16

17

34

33

32

36

18

19

D12

D12 1N4148W

1N4148W

C A

C605

0.22uF

25V, X7R, +/-10%

D13

D13 1N4148W

1N4148W

C A

C603

0.22uF

25V, X7R, +/-10%

D14

D14 1N4148W

1N4148W

C A

C619

0.22uF

25V, X7R, +/-10%

12V_VRM

2

1

12V_VRM

C594

C594 1uF

1uF

VBOOT

R491

2.2

*

+/-5%

R500

R500 0

0

+/-5%

R496

1K

+/-1%

r0603h6

VBOOT

R502

2.2

*

+/-5%

R503

R503 0

0

+/-5%

R509

1.65K

+/-1%

R508

1K

+/-1%

r0603h6

VBOOT

R512

2.2

*

+/-5%

R514

R514 0

0

+/-5%

R519

1.65K

+/-1%

R518

1K

+/-1%

r0603h6

L12

4

1.2uH@100KHz

PWR1

PWR1 HM3502E-P1

HM3502E-P1

3

C733

*

0.1uF

+/-10%

R501

1.65K

+/-1%

*

R499

2.2

+/-5%

R676

R677

R679

G

12V_VIN

Dummy

12V_VIN

Dummy

12V_VIN

3

DS

10K

DS

10K

DS

10K

DS

*

Q21

Q21 AOD452

AOD452

Q23

Q23 AOD472

AOD472

Q26

Q26 AOD452

AOD452

Q28

Q28 AOD472

AOD472

Q30

Q30 AOD452

AOD452

Q32

Q32 AOD472

AOD472

EC32

1500uF

16V, +/-20%

2

5V_SB_SYS

R487

10K

+/-5%

r0603h6

R488

R492

2.2

+/-5%

C601

1.5nF

50V, X7R, +/-10%

R504

2.2

+/-5%

C611

1.5nF

50V, X7R, +/-10%

R515

2.2

+/-5%

C630

1.5nF

50V, X7R, +/-10%

12V_VIN

EC34

1500uF

16V, +/-20%

R488

4.7K

Dummy

L9

Choke 700nH

*

R493

+/-5%

r0603h6

L10

Choke 700nH

*

R505

+/-5%

r0603h6

L11

Choke 700nH

*

R516

+/-5%

r0603h6

EC35

1500uF

*

16V, +/-20%

22.1K

+/-1%

R0603

680

R489

+V_CPU

C600

C600 1uF

1uF

C610

C610 1uF

1uF

C625

C625 1uF

1uF

CPUVDD_EN14

Q22

C599

DS

AOD452

4.7uF

*

25V, Y5V, +80%/-20%

Q24

DS

AOD472

Q27

DS

AOD452

Q29

DS

AOD472

Q31

DS

AOD452

Dummy

Q33

DS

AOD472

EC33

1500uF

16V, +/-20%

25V, Y5V, +80%/-20%

*

C606

4.7uF

*

25V, Y5V, +80%/-20%

*

C620

4.7uF

*

25V, Y5V, +80%/-20%

*

G

*

B

C597

C597 1uF

1uF

Q25

Q25 PMBT3904

PMBT3904

E C

**

EC24

3300uF

6.3V, +/-20%

EC25

3300uF

6.3V, +/-20%

EC28

3300uF

6.3V, +/-20%

Dummy

12V_VRM

DS

G

**

R485

10K

+/-5%

r0603h6

Q20

2N7002-7-F

EC30

3300uF

6.3V, +/-20%

EC26

3300uF

6.3V, +/-20%

R490

*

4.7K

+/-5%

r0603h6

**

VRM_EN

C598

1nF

50V, X7R, +/-10%

EC31

3300uF

6.3V, +/-20%

EC27

3300uF

6.3V, +/-20%

1

VCORE over VID CKT

TECHNOLOGY COPR.

Title

Document Number Rev

Date: Sheet of

5

4

3

2

Date: Sheet

PWM ST L6711 for AM2

CK804A07

1

TECHNOLOGY COPR.

of

36 41Tuesday, October 31, 2006

A

5

4

3

2

1

AP15N03H

AP15N03H Q76

Q76

EC39

1000uF

6.3V, +/-20%

ce35d80h140

5V_SB_SYS

C A

EC40

1000uF

*

6.3V, +/-20%

ce35d80h140

D27

D27 B120-13-F

B120-13-F

*

5V_DUAL_DDR

EC41

1000uF

6.3V, +/-20%

ce35d80h140

*

EC42

1000uF

*

6.3V, +/-20%

Dummy

ce35d80h140

C643

10uF

6.3V, X5R, +/-10%

C1206

1D8V_STR

C644

10uF

*

6.3V, X5R, +/-10%

C1206

5V_SYS

EC66

*

C762

Dummy

2.2uF

D D

D15

B120-13-F

B120-13-F D16

D16

B120-13-F

Open

L

Open

Q34

Q34 PMBT3904

PMBT3904

E C

CA

12V_SYS

5V_SB_SYS

R528

4.7K

+/-5%

L

r0603h6

H

L

B

C C

B B

SLP_S5*18

First H

R531 1K

+-5%

S5

r0603h6

S0

S3

L

*

H

DDR_GPIO132,41

L

B

E C

C639

2.2uF

C0805

10V, X5R, +/-10%

Dummy

Q36

Q36 PMBT3904

PMBT3904

2.2uF

C0805

10V, X5R, +/-10%

R726

R726 10

10

*

+/-5%

R527

r0805h6

10

*

+/-5%

r0805h6

C637

R529

14.3K

+/-1%

R0603

Rocset

R534

R534 910

910

+/-1%

R0603

1uF

5

U47

7

COMP/OCSET

6

FB

RT9214PS

VOUT= 0.8V(1+R638 / R658) R638,R658 must less than 1k

DDR_GPIO232,41

VCC

GND

3

For DDRII 800

EC66

100uF

*

16V, +/-20%

CE20D50H110

FAB B change

D17

B120-13-F

1

BOOT

2

UGATE

8

PHASE

4

LGATE

CA

Near MOSFET

R535

R535 453

453

+/-1%

r0603h6

*

?

C734

0.1uF

+/-10%

c0603h10

R530

0

+/-5%

r0805h6

R538

R538 91

91

+/-1%

r0603h6

18V_PHASE

5V_DUAL_DDR

*

L13

900nH@1KHz

DS

Q35

G

AOD452

18V_PHASE

DS

Q37

G

AOD472

R533 115

*

R536 220 R0603 +/-1%

Reserved

PWOK+39

close to Q61 Drain

C638

0.1uF

*

50V, Y5V, +80%/-20%

C0603

R532

2.2

+/-5%

r0805h6

C640

2.2nF

*

50V, X7R, +/-10%

C0603

L14

*

3.3uH@100KHz

*

EC36

1500uF

16V, +/-20%

CE50D100H300

C641

0.1uF

C0603

Pull FB trace out after Cout

C642 18nF C0603 50V, Y5V, +80%/-20%

Dummy

*

G

*

EC38

1000uF

6.3V, +/-20%

ce35d80h140

D S

EC37

1500uF

16V, +/-20%

CE50D100H300

*

DDR_GPIO1

1D8V_STR

EC43

1000uF

*

6.3V, +/-20%

ce35d80h140

R540

100K

+/-1%

r0603h6

R541

100K

+/-1%

A A

+/-1%

r0603h6

5

U48

1

VIN

VCNTL4 VCNTL3 VCNTL2 VCNTL1

REFEN

RT9173

VOUT

GND

3

C645

0.1uF

*

3D3V_DUAL

*

VTT_DDR

EC44

1000uF

6.3V, +/-20%

ce35d80h140

NOTE:1=OD

C647

4.7uF

*

C0805

3

8 7 6 5

4 2

C646

0.1uF

*

4

DDR_GPIO2

1D8V_STR

11

0

1

0

1 1.9V

0

1.8V

2.0V

2.1V

TECHNOLOGY COPR.

Title

Document Number Rev

Date: Sheet

2

Date: Sheet

DDR Power

CK804A07

TECHNOLOGY COPR.

of

37 41Tuesday, October 31, 2006

of

37 41Tuesday, October 31, 2006

of

37 41Tuesday, October 31, 2006

1

A

5

4

3

2

1

1D5V FOR CHIP

1D5V_PHASE

3D3V_DUAL

12V_SYS

*

L15

900nH@1KHz

DS

G

1D5V_PHASE

DS

G

R548 105r0603h6+/-1%R548 105r0603h6+/-1%

R551

R551 220

220

+/-1%

R0603

Dummy

R554

2.1K

+/-1%

R0603

*

R556

50V, Y5V, +80%/-20%

1.21K

C0603

+/-1%

r0603h6

*

Q40

AOD452

Q41

AOD472

*

Pull FB trace out after Cout

C658 18nF C0603 50V, Y5V, +80%/-20%

Dummy

*

C659

0.1uF

C649

0.1uF

50V, Y5V, +80%/-20%

C0603

L16

*

3.3uH@100KHz

R547

2.2

+/-5%

r0805h6

C656

2.2nF

50V, X7R, +/-10%

C0603

HT

1.2V @ 850MA AMPS MAX

12V_SYS

84

3

+

2

-

LM358DR2

R702

R701

1.21K

2.4K

+/-1%

r0603h6

U51A

1

*

R558 100R558 100

Change 680uF 16V

EC46

1500uF

*

16V, +/-20%

CE50D100H300

C651

0.1uF

*

50V, Y5V, +80%/-20%

C0603

CORE GPIO1

NOTE:1=OPEN DRAIN

G

R719 1KR719 1K

EC45

1500uF

*

16V, +/-20%

CE50D100H300

EC47

*

CORE GPIO2

EC47

1000uF

6.3V, +/-20%

ce35d80h140

1D5V_CORE

EC48

1000uF

6.3V, +/-20%

ce35d80h140

11

0

1 1.6V

0

1

0

1D8V_STR

EC49

1000uF

*

6.3V, +/-20%

ce35d80h140

Q44

AP15N03H

EC50

1000uF

6.3V, +/-20%

ce35d80h140

DS

*

CK804 CORE AUX

C650

4.7uF

*

25V, Y5V, +80%/-20%

C1206

Dummy

1D5V_CORE

EC65

1000uF

*

6.3V, +/-20%

ce35d80h140

1.5V

1.7V

1.8V

1D2V_HT

*

C660

4.7uF

6.3V, X5R, +/-10%

C0805

1D5V_DUAL_GPIO241

C661

0.1uF

*

50V, Y5V, +80%/-20%

C0603

1.5V_DUAL @ 275MA MAX

3D3V_DUAL

C743

10uF

*

10V, Y5V, +80%/-20%

C0805

10V, Y5V, +80%/-20%

3D3V_DUAL

4.7K

3D3V_DUAL

G

R700

4.7K

+/-5%

r0603h6

R651

1.21K

+/-1%

r0603h6

R652

3.83K

+/-1%

R0603

DS

*

R699

+/-5%

r0603h6

AME1117ACGTZ

10uF

C0805

Q79

2N7002-7-F

DS

G

C738

0.1uF

50V, Y5V, +80%/-20%

C0603

U50

C745

*

Q80

2N7002-7-F

5 6

3

12V_SYS

+

-

4

ADJ1Vout2Vin

R695

124

+/-1%

r0603h6

R696

R697

R698

249

+/-1%

R0603

G

R720 1KR720 1K

R698

54.9

+/-1%

R0603

3D3V_SYS

Dummy

DS

100

+/-1%

r0603h6

U51B

84

7

LM358DR2

R653 100R653 100

C736

4.7uF

*

6.3V, X5R, +/-10%

C0805

Q72

AP15N03H

*

1D5V_DUAL

C744

10uF

C654

10V, Y5V, +80%/-20%

0.1uF

C0805

*

50V, Y5V, +80%/-20%

C0603

GPIO1

GPIO2

11

1

0

NOTE:1=OPEN DRAIN

C737

0.1uF

*

50V, Y5V, +80%/-20%

C0603

Dummy

G

1D5V_DUAL

1.5V

0 1.6V

1

1.7V

0

1.8V

DS

Q73

2N7002-7-F

+2.5V

*

EC60

100uF

16V, +/-20%

CE20D50H110

Dummy

C735

Near MOSFET

4.7K

C735

0.1uF

+/-10%

c0603h10

*

R544

0

+/-5%

r0805h6

R546

0

+/-5%

r0805h6

R550

R550 432

432

+/-1%

r0603h6

Q45

B

PMBT3904

E C

D18

R542

R542 10

10

*

12V_SYS

D D

C C

B B

R543

14.3K

+/-1%

R0603

Rocset

CORE_GPIO132,41

HTVDD_EN14

*

+/-5%

r0805h6

C648

1uF

7

COMP/OCSET

6

FB

R545

RT9214PS

118

+/-1%

R0603

VOUT= 0.8V(1+R638 / R658) R638,R658 must less than 1k

R557 1KR557 1K

CA

1N4148W

5

U49

1

BOOT

VCC

2

UGATE

8

PHASE

4

LGATE

GND

3

R549

R549 953

953

+/-1%

R0603

CORE_GPIO232,41 1D5V_DUAL_GPIO141

5V_SB_SYS

R555

+/-5%

r0603h6

Q46

B

PMBT3904

E C

1D2V_HT_GPIO141

1D2V_HT_GPIO241

1D2V_HT_GPIO1

1D2V_HT_GPIO2

11

0

1

A A

5

0

NOTE:1=OPEN DRAIN

1D2V_HT

1.2V

1 1.25V

0

1.3V

0

1.35V

TECHNOLOGY COPR.

Title

Document Number Rev

Date: Sheet

Date: Sheet of

4

3

2

Date: Sheet of

CK804 CORE POWER

CK804A07

1

TECHNOLOGY COPR.

of

38 41Tuesday, October 31, 2006

A

5

5V_SB_SYS 3D3V_DUAL

R559

8.2K

Dummy

+/-5%

G

DS

Dummy

+/-5%

r0603h6

Q47

2N7002-7-F

UNNAMED_38_MOSFETNSOT23_I146_GPWRGD_Q1

R565

0

+/-5%

r0603h6

G

*

Dummy

D D

5V_DUAL

C C

MIN 10ms

R561

Dummy

4.7K

r0603h6

+/-5%

RSMRSTJ32

*

Dummy

C663

4.7uF

6.3V, X5R, +/-10%

C0805

DS

R560

4.7K

r0603h6

+/-5%

PWRGD_SB

Q48

2N7002-7-F

PWRGD_SBRSMRSTJ

4

*

FAB B change

R566

10K

+/-5%

r0603h6

PWRGD_SB 18

C662

0.1uF

50V, Y5V, +80%/-20%

C0603

Dummy

3

5V_SB_SYS 3D3V_DUAL

1D2V_HT

R564

1K

r0603h6

+-5%

R569

Dummy

*

0

+/-5%

r0603h6

PWRGD_PS

PWRGD_PS40

3D3V_DUAL5V_SB_SYS

R567

10K

Dummy

+/-5%

r0603h6

DS

Q51

G

2N7002-7-F

Dummy

HT_BASE

C664

0.1uF

*

50V, Y5V, +80%/-20%

C0603

Dummy

R568

5.1K

+/-1%

r0603h6

CK8_PWRGD

R570

*

10K

+/-5%

r0603h6

B

C666

0.1uF

50V, Y5V, +80%/-20%

C0603

Dummy

R562

10K

+/-5%

r0603h6

Q49

Q49 PMBT3904

PMBT3904

E C

CK8_PWRGD 9,18

2

R563

10K

+/-5%

r0603h6

DS

Q50

G

2N7002-7-F

HT_VLD

C665

0.1uF

*

50V, Y5V, +80%/-20%

C0603

Dummy

1

HT_VLD 14

DS

Q52

Dummy

PWOKJ

4

Dummy

G

Dummy

G

5V_SB_SYS

DS

R576

1K

+-5%

r0603h6

2N7002-7-F

Q53

2N7002-7-F

Q57

G

2N7002-7-F

PWRGD_PS

5V_DUAL 3D3V_DUAL

U52

AZ1084D-ADJTRE1

C669

1uF

*

16V, Y5V, +80%/-20%

C0603

5V_SYS

5V_DUAL

PWOK+37

G

3

D S

5V level

AP15N03H

AP15N03H Q56

Q56

U52

ADJ1Vout

Vin

2

3

R573

301

+/-1%

r0603h6

R574

499

+/-1%

r0603h6

Power sequence

2

3D3VADJ

MAX PCB COPPER

Title

Document Number Rev

Date: Sheet

Max. output current = 3A

EC52

1000uF

*

6.3V, +/-20%

ce35d80h140

CK804A07

TECHNOLOGY COPR.

of

39 41Tuesday, October 31, 2006

of

39 41Tuesday, October 31, 2006

of

39 41Tuesday, October 31, 2006

1

A

R571

8 7 6

Id(N MOS) max= 6.9A Id(P MOS) max= -5A

5

PWRGD_PS

1D5V_CORE

D1 D1 D2 D2

PWRGD_PS40

B B

5V_DUAL

A A

EC53

1000uF

*

6.3V, +/-20%

ce35d80h140

1

S2G2S1G1

2 3 45

5V_SYS

R571

Dummy

+/-5%

r0603h6

Dummy

Q54

Q54 AO4600

AO4600

10K

R572

10K

+/-5%

r0603h6

5V_SB_SYS

PWOK+

C667

0.33uF

*

16V, X7R, +/-10%

Dummy

C0805

12V_SYS

DS

C668

0.33uF

*

16V, X7R, +/-10%

C0805

Dummy

R575

1K

+-5%

r0603h6

Q55

G

2N7002-7-F

5

4

3

2

1

PWR2

+3.3V1 +3.3V2

GND1 GND2 GND3

PWR0K

+5V_AUX

+12V_1 +12V_2

+3.3V4

R589

+-5%

r0603h6

+5V1 +5V2

330

R592 33R592 33

3D3V_SYS3D3V_SYS-12V_SYS 5V_SYS5V_SYS 12V_SYS

1 2 3 4 5 6 7 8 9 10 11 12

3D3V_DUAL

S1_LED32

Date:10/09

D22

Dummy

CA

1N4148W

PLED

R581

+/-5%

r0603h6

Dummy

5V_SB_SYS

D D

PS_ON#32

R579 1K

SLP_S3*18,32

Dummy

B

Modify V1.0

C C

D19

3D3V_SYS

R586

+/-5%

r0603h6

D19

C A

1N4148W

D21

1 2

BAT54A-7-F

10K

C673

1uF

*

16V, Y5V, +80%/-20%

C0603

3

*

SATA_HDLED*17

P_HDLEDJ29 S_HDLEDJ29

FP_RESET*18

B B

SATA_HDLED*

P_HDLED* S_HDLED*

FP_RESET*

R577

22K

+/-5%

r0603h6

C670

Q58

Q58 PMBT3904

PMBT3904

Dummy

E C

R591 33R591 33

UNNAMED_41_CAP_I163_A

C674

470pF

50V, X7R, +/-10%

C0402

C670

470pF

*

50V, X7R, +/-10%

C0402

5V_SYS 5V_DUAL

R585

330

+-5%

r0603h6

FP1

1 2 3 5 7 8 9

X

Header_2X5_10 Shield

HH2X5MZO10

4 6

SWITCH_ON*

13

+3.3V3

14

-12V

15

GND4

16

PSON

17

GND5

18

GND6

19

GND7

20

RSVD

21

+5V3

22

+5V4

23

+5V5

24

GND8

PWR24NWP2_HM25A

5V_DUAL

R588

10K

+/-5%

r0603h6

C675

0.1uF

*

50V, Y5V, +80%/-20%

C0603

Dummy

HM1512E-EP1

4.7K

4.7K D20

D20

C A

1N4148W

S3_LED 32

PANSWH# 32

5V_SB_SYS

3D3V_SYS

R582

4.7K

+/-5%

r0603h6

B

5V_SYS

R578

R578 100K

100K

+/-5%

r0603h6

PWRGD_PS

C671

0.1uF

*

50V, Y5V, +80%/-20%

C0603

PLED

Q59

Q59 PMBT3904

PMBT3904

SOT23_BEC

E C

5V_SB_SYS

R580

+/-5%

r0603h6

AUX PEX PWR

5V_SYS

*

Dummy

SPEAKER

5V_SYS

12V_SYS

*

EC64

100uF

16V, +/-20%

CE20D50H110

3D3V_SYS

FAB B change

R593

10K

+/-5%

r0603h6

R594 1KR594 1K

EC63

470uF

16V, +/-20%

ce35d80h125

SPEAKER STRAPS

ROM TABLE SELECT

1 = SAFE (DEFAULT)

O = USER (User Mode)->Clone

R584

1K

Dummy

+-5%

r0603h6

B

PWR3

Dummy

1

2

3

4

R590

1K

+-5%

r0603h6

E C

+12V

GND

+5V

R587 4.7KR587 4.7K

Q61

Q61 PMBT3904

PMBT3904

5

Header_1X4_Power

B

5V_SYS

E C

R583

100

+/-5%

r0603h6

Dummy

Q60

PMBT3904

SOT23_BEC

RN41

*

1 3 5 7 8

100 Ohm

+/-5%

8p4r0603h7

BUZ

BUZ Buzzer

Buzzer

Reserved

BUZZER

2 4 6

5V_SYS

1

+

2

-

FAB B change

5V_SYS

SPEAKER

SPEAKER Header_1X4_2

Header_1X4_2

1

3

C672

1nF

*

50V, X7R, +/-10%

C0603

SPEAK

3

4

PWRGD_PS 39

4.7K

SPEAKER18,30

SIO_BEEP32

5V_SB_SYS

R595

330

+-5%

r0603h6

12

D23

D23 LED_Yellow

LED_Yellow

BATT1

LITHIUM BATT

Battery

3D3V_DUAL VBAT

BATT_PWR_R

R596 1K

BATT_PWR

CR2032

Battery Holder

2 1

BAT1

+-5%

1 2

Q62

BAT54C

C676

0.1uF

+/-10%

c0603h10

VBAT

C678

C677

4.7uF

0.1uF

*

6.3V, X5R, +/-10%

+/-10%

C0805

c0603h10

3

*

This is for battery cell.

A A

TECHNOLOGY COPR.

Title

Document Number Rev

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

POWER CON /FNT PNAL / VBAT

CK804A07

1

TECHNOLOGY COPR.

of

40 41Tuesday, October 31, 2006

A

5

4

3

2

1

3D3V_DUAL

D D

C741

0.1uF

C0603

3V_CPU_VID4

3V_CPU_VID0 3V_CPU_VID1 3V_CPU_VID2 3V_CPU_VID3

3D3V_DUAL

1 2 3 4 5 6 7 8

9 10 11 12 13 14

R691

Dummy

0 r0603h6

0 r0603h6 RN44

RN44

Dummy

1

*

3 5 7 8

0

+/-5%

8p4r0603h7

U56

3VSB GPIO3 GPIO4 GPIO5 VIDIN0 VIDIN1 VIDIN2 VIDIN3 VIDIN4 GPIO0 GPIO1 GPIO2 SDA SCL

+/-5%

*

TEST/ASEL

VIDOUT0 VIDOUT1 VIDOUT2 VIDOUT3 VIDOUT4

SLOTOCC#

RSTOUT#

R690 4.7K

r0603h6+/-5%

RN43

*

1

2

3

4

5

6

7 8

4.7K

+/-5%

8p4r0603h7

*

50V, Y5V, +80%/-20%

C C

CORE_GPIO232,38 1D5V_DUAL_GPIO138 1D5V_DUAL_GPIO238

3V_CPU_VID09,32 3V_CPU_VID19,32 3V_CPU_VID29,32 3V_CPU_VID39,32 3V_CPU_VID49,32

DDR_GPIO132,37 DDR_GPIO232,37

CORE_GPIO132,38

SMB_SDA18,20,21,22,23 SMB_SCL18,20,21,22,23

50V, Y5V, +80%/-20%

2 4 6

GPIO6 GPIO7 GPIO8 GPIO9

VBAT

GND

IT8203R

VREG_VID4

VREG_VID0 VREG_VID1 VREG_VID2 VREG_VID3

28 27 26 25 24 23 22 21 20 19 18 17 16 15

3D3V_DUAL

R693

1K

+-5%

r0603h6

GPIO8 GPIO9

*

C742

0.1uF

+/-10%

c0603h10

3D3V_SYS

R692 4.7K

Dummy

RN45

Dummy

*

1

2

3

4

5

6

7 8

4.7K

+/-5%

8p4r0603h7

R705

10M

+/-5%

r0603h6

r0603h6+/-5%

1D2V_HT_GPIO1 38 1D2V_HT_GPIO2 38

VREG_VID0 36 VREG_VID1 36 VREG_VID2 36 VREG_VID3 36 VREG_VID4 36

VBAT

CPU_PRESENT 36

GPIO9 GPIO8

FAB B change

3D3V_DUAL

R703

4.7K

r0603h6

+/-5%

R704

4.7K

r0603h6

+/-5%

B B

A A

EMI

+V_CPU

C757

0.1uF

*

C0603

50V, Y5V, +80%/-20%

1D2V_HT

*

50V, Y5V, +80%/-20%

5

*

C758

0.1uF

C0603

C763

0.1uF

C0603

-12V_SYS

C746

0.1uF

*

C0603

50V, Y5V, +80%/-20%

12V_SYS 3D3V_SYS

FAB B change

12V_SYS

C748

0.1uF

*

C0603

50V, Y5V, +80%/-20%

C750

*

0.1uF

C0603

50V, Y5V, +80%/-20%

*

50V, Y5V, +80%/-20%

5V_SYS

C751

0.1uF

*

C0603

50V, Y5V, +80%/-20%

4

*

50V, Y5V, +80%/-20%

5V_SYS

C749

C759

0.1uF

*

C0603

50V, Y5V, +80%/-20%

3D3V_SYS

C752

0.1uF

C0603

50V, Y5V, +80%/-20%

C756

0.1uF

*

C0603

50V, Y5V, +80%/-20%

C753

0.1uF

*

C0603

Dummy

50V, Y5V, +80%/-20%

5V_SYS

*

Dummy

C754

0.1uF

C0603

3D3V_SYS

C747

*

0.1uF

C0603

50V, Y5V, +80%/-20%

3

T2T1T2

1 2

T1

2

T1T1T1

1 2

T1

TECHNOLOGY COPR.

Title

Document Number Rev

Date: Sheet

VID CONTROLLER

CK804A07

TECHNOLOGY COPR.

41 41Tuesday, October 31, 2006

1

A

of

A

5

4

3

2

1

D D

Fab. A to Fab.B change list

SCH change list 1, Add VID level shift. 2, Remove LDSTOP, PWROK, LRESET co-layout. 3, Change R272 from 6.34K to 6.2k 4, Add C464 10pF for EMI 5, Change FAN circuit. 6, Add R726, C762, EC66.

C C

7, Add memvld level shift. 8, Add R725 pull high cpu_therm*

Layout change list 1, Add VID level shift. 2, Remove LDSTOP, PWROK, LRESET co-layout. 3, Change FAN circuit. 4, Add R726, C762, EC66. 5, Add memvld level shift. 6, Add R725 pull high cpu_therm* 7, Add 5v_sys Power Plane for USB droop. 8, Change silkscreen.

B B

A A

TECHNOLOGY COPR.

Title

Document Number Rev

Date: Sheet

5

4

3

2

Date: Sheet

change list

CK804A07

TECHNOLOGY COPR.

of

42 42Tuesday, October 31, 2006

of

42 42Tuesday, October 31, 2006

of

42 42Tuesday, October 31, 2006

1

A

Foxconn CK804A07 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual