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C51GK8MB
Schematics
38 pgs1.35 Mb0

Foxconn C51GK8MB Schematics

5
4
3
Foxconn C51GK8MB
2
1
D D
Fab :A
nVIDIA C51G (A01) + MCP51 (A01) Chipset for AMD K8 939 CPU
(Mar./31B/2005)
PAGE PAGECONTENT CONTENT
01. COVER
1
02. BLOCK DIAGRAM
2
03. RESET MAP
3
04. CLOCK DISTRIBUTION
C C
B B
A A
4
05. PCI DEVICE / VID TABLE
5
06. Athlon 64-1 Hyper Transport
6
07. Athlon 64- 2 DDR -1
7
08. Athlon 64- 2 DDR -2
8
09. Athlon 64_ 3 MISC
9
10. Athlon 64- 4 Power
10
11. DDR SDRAM DIMM1-2
11
12. DDR SDRAM DIMM3-4
12
13. DDR ADD / CTL TERMINATI
13
133 DDRTerminator
14
14. C51G_HT
15
15. C51G_VGA PCI-E
16
16. C51G_POWER
17
17. MCP51_HT PCI
18
18. MCP51_SATA IDE RGMII
19
19. MCP51_AC97 USB
20
20. MCP51_POWER & VGA CONN
21
21. PCI_E X16 Slot
22
22. PCI SLOT 1 2 3
23
23. SIO IT8712F
24
LEADTEK RESEARCH INC. ASSUMES NO RESPONSIBILITY FOR ANY ERRORS IN DRAWING THESE SCHEMATICS. THESE SCHEMATICS ARE SUBJECT TO CHANGE AT ANY TIME WITHOUT NOTICE. COPYRIGHT 2002 LEADTEK RESEARCH INC. .
5
4
24. IDE / Floppy / PS2
25
25. PLT / COM
26
26. FAN / HARDWARE MONITOR /VID
27
27. USB CONNECTORS
28
28. FLASH / PWRGD SKT
29
29. PWR CONN / FNT PNL / VBAT
30
30. ACPI VREG
31
31. CK51 CORE / HT VREGS
32
32. VRM
33
33. TI 1394
34
34. LAN 88E1111 RTL8201
35
35. Audio ALC655 ALC880 ALC850
36
36. Audio Connector
37
37 ACPIW83304
38
3
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Cover
Cover
Cover
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
FOXCONN PCEG
138Monday, June 13, 2005
138Monday, June 13, 2005
138Monday, June 13, 2005
1
of
of
of
AC
AC
AC
5
4
3
2
1
C51GM02 Block Diagram
K8 CPU
SOCKET 939
D D
POWER
SUPPLY CONNECTOR 2*12 = 24 pin
PCI Express X16
C C
PCI Express X1
VREG -> ISL6566 => 3 phase
60 Amp
PCI EXPRESS Lane * 16
PCI EXPRESS Lane * 1
Athlon & Athlon FX & Sempron
HT 16X16 1600GT/S => 800M-HT Link
NFORCE CRUSH 51
468 Ball BGA 25mm * 25mm
HT 8X8 2000GT/S => 1G-HT Link
DDR Memory CH:A
64-BIT 100/133/166/200MHZ
DDR Memory CH:B2*2 = 4 pin (12V)
RGB Output
PCI SLOT 1
PCI V2.3 / 33MHZ
PRIMARY IDE
SECONDRY IDE
B B
ATA 133
ATA 133
NFORCE
MCP51
508 Ball BGA 27mm * 27mm
AC97 /HDA
DDR SDRAM CONN 0
DDR SDRAM CONN 2
DDR SDRAM CONN 1
DDR SDRAM CONN 3
VGA CONN * 1
PCI SLOT 2
TSB43AB22A
AC97 / ALC655 (5.1 Audio) => Default
or
Azalia / ALC880 (7.1 Audio)
PCI_RESET0*
SB ACPIPS_ON#
1394 header * 1 #2
1394 header * 1 #1
SLP_S5* SLP_S3*
S I/OPWRBTN#
CPU_VLD
HT_VLD
VRM_EN
VRM
PWM_GD
SWPANSWHJ
PS_OUT#
PWRGD_PS
ATX POWER
SIO
ITE IT8712F/IX
INTEGRATED SATA
LPC BUS V1.0 / 33MHZ
4MB FLASH
4
X8 USB ( V2.0 EHCI / V1.1 OHCI )
RGMII/MII
3
BACK PANEL CONN => 4 Port
USB2 PORTS 7,8 USB2 PORTS 1,6
10/100Mb (Giga-Bit )LAN PHY
FRONT PANEL Header * 2 => 4 Port
USB2 PORTS 2,3
USB2 PORTS 4,5
Broadcom AC131 Default ( & B5011U co-lay )
2
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Block Diagram
Block Diagram
Block Diagram
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
FOXCONN PCEG
C51GK8MB
C51GK8MB
C51GK8MB
238Monday, June 13, 2005
238Monday, June 13, 2005
238Monday, June 13, 2005
1
of
of
of
ACustom
ACustom
ACustom
SATA-II CONN * 4
FLOPPY CONN
PS2/KB CONN
PARALLEL CONN
A A
SERIAL CONN (COM1)
SERIAL Header (COM2)
5
5
4
3
2
1
RESET MAP
D D
K8 Socket 939
CPU RST*
CPU PWRGD
CRUSH 51
PE_RESET*
C C
PEX X16
PEX X1
HT CPU PWRGD HT CPU RST*
HT MCP PWRGD HT MCP RST*
PWR SWTCH
HT_CPU_PWRGD HT_CPU_RST*
HT_MCP_PWRGD HT_MCP_RST*
MCP 51
AUDIO_PHY
RESET*
HT_MCP_RST* HT_MCP_PWRGD
PCIRST_SLOT1* PCIRST_SLOT2* PCIRST_SLOT3* PCIRST_IDE* LPCRST_FLASH* LPCRST_SIO*
3
SEC IDE
PCI SLOT 1PCI SLOT 2TI1394PRI IDEFLASHSIO
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Reset Map
Reset Map
Reset Map
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
FOXCONN PCEG
C51GK8MB
C51GK8MB
C51GK8MB
1
ACustom
ACustom
ACustom
of
of
of
338Monday, June 13, 2005
338Monday, June 13, 2005
338Monday, June 13, 2005
B B
A A
PS ON
PWR GOOD
PWRGD SB
CIRCUIT
5
PWR CONN
PWRBTN*
SLP_S3*
POWER_GOOD
PWRGD_SB
PWR BUTTON
SLP S3*
PWRGD
PWRGD_SB
GPIO_AUX*
4
LAN_PHY
RESET*
HT MCP RST*
HT MCP PWRGD
PCI RST0* PCI RST1* PCI RST2* PCI RST3*
LPC_RST*
AC_RESET*
5
4
3
2
1
D D
C C
B B
32.0 KHZ
25 MHZ
A A
HT_CPU_TXCLK0 HT_CPU_TXCLK0*
HT_CPU_RXCLK0 HT_CPU_RXCLK0*
HT_CPU_TXCLK1 HT_CPU_TXCLK1*
HT_CPU_RXCLK1 HT_CPU_RXCLK1*
CPUCLK_IN* CPUCLK_IN
CLKOUT_200MHZ CLKOUT_200MHZ*
HT_CPU_RXCLK1* HT_CPU_RXCLK1
HT_CPU_TXCLK1* HT_CPU_TXCLK1
HT_CPU_RXCLK0* HT_CPU_RXCLK0
HT_CPU_TXCLK0* HT_CPU_TXCLK0
HT_MCP_TXCLK0 HT_MCP_TXCLK0*
HT_MCP_RXCLK0 HT_MCP_RXCLK0*
CLKIN_25MHZ
CLKIN_200MHZ* CLKIN_200MHZ
MCPCLK_OUT MCPCLK_OUT*
25MHZ_CLKOUT
HT_MCP_RXCLK0* HT_MCP_RXCLK0
HT_MCP_TXCLK0* HT_MCP_TXCLK0
RTC_XTAL
XTAL_IN
XTAL_OUT
K8 939 CPU
CRUSH 51
MCP 51
PE0_REFCLK PE0_REFCLK*
PE1_REFCLK PE1_REFCLK*
PE2_REFCLK PE2_REFCLK*
PCI_CLK_FB
AC_BITCLK
BUF_25MHZ
MEMCLK_L[0,5,7] MEMCLK_H[0,5,7]
MEMCLK_L[2,3] MEMCLK_H[2,3]
MEMCLK_L[1,4,6] MEMCLK_H[1,4,6]
XTAL_IN
XTAL_OUT
BUF_SIO
SUSCLK
LPC_CLK0
PCI_CLK0 PCI_CLK1 PCI_CLK2 PCI_CLK3 PCI_CLK4
LPC_CLK1
AC_97CLK
14MHZ OR 24MHZ
NC
27 MHZ (TV OUT ONLY)
CHANNEL A1 0-63
CHANNEL B1 0~63
DIMM 0
DIMM 1
PEX X16
SIO
AC97 CODEC
AZALIA CODEC
LAN PHY
FLASH
HEADER
LPC
PCI SLOT 1
PCI SLOT 2
TI1394
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Clock Distribution
Clock Distribution
Clock Distribution
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
FOXCONN PCEG
438Monday, June 13, 2005
438Monday, June 13, 2005
438Monday, June 13, 2005
1
AC
AC
AC
of
of
of
5
4
3
2
1
D D
C C
B B
CPU VID TABLE
VID [4..0]
0X00000 0X00001 0X00010 0X00011 0X00100 0X00101 0X00110 0X00111 0X01000 0X01001 0X01010 0X01011 0X01100 0X01101 0X01110 0X01111
VDD
SMBUS ADDRESS MAP
DEVICE
DIMM 0 0 DIMM 1 0 DIMM 2 DIMM 3 SIO PCI SLOT 1 PCI SLOT 2 TI 1394
DDC BUS DDC BUS
1.550V
1.525V
1.500V
1.475V
1.450V
1.425V
1.400V
1.375V
1.350V
1.325V
1.300V
1.275V
1.250V
1.225V
1.200V
1.175V 0X11111
VID [4..0]
0X10000 0X10001 0X10010 0X10011 0X10100 0X10101 0X10110 0X10111 0X11000 0X11001 0X11010 0X11011 0X11100 0X11101 0X11110
SMBUS #
0 0 1 1 1 1
BA?
ADDRESS
1010 000 = 0X50 1010 001 = 0X51 1010 010 = 0X52 1010 011 = 0X53 0101 101 = 0X2D ARP ARP ARP
?
VDD
1.150V
1.125V
1.100V
1.075V
1.050V
1.025V
1.000V
0.975V
0.950V
0.925V
0.900V
0.875V
0.850V
0.825V
0.800V OFF
BACK PANEL
SLOT
TI 1394 PCI 1 PCI 2
PCI DEVICE MAP
DEVICE
MCP 51
MAC /MAC
PCI-PCI BRIDGE
SATA1 X8 0
SATA0 0 X8 0
IDE X6
MODEM CODEC 0
AUDIO CODEC X4 0
USB 2.0 X2
USB 1.1 0 X2 0
SHAPE TRIM
LDT 0 X0 0
SMBUS2
LEGACY SLAVE
LPC
LOGICAL PCI BUS
PCI SLOT 1
PCI SLOT 2
PCI SLOT 3
PCI SLOT 4
PCI SLOT 5
PCI INTERRUPT/IDSEL MAP
PCI BUS# DEVICE# IDSEL PIN PCI SLOT PCI SLOT
22
0X06
01
0X08
01
PCI BUS#
MCP51 LOGICAL PCI BUS 0
DEVICE#
0X01-0X0F
0
00
0
0
0
0
0
0
0
0
1
P_INTZ*
P_INTX*
P_INTW*
23
P_INTX* P_INTW*
0
0
1
1
2
1?0X0052
0
?
DEVICE ID
0X56/57
0X005C
0X0055
0X0054
0X0053
0X0058
0X0059
0X005B
0X005A
0X005F
0X005E
0X00D3
0X0050/51
?
P_INTY*
24
FUNCTION
XA
X9
X4
X1
X1
?
X1
?
INTC*INTB*INTA*
P_INTY* P_INTZ*
----
SOT23
1
SOT23-6
6
12
1/1 2/2P_INTZ* 3/301 0X09
SOT23-5/SC70
3
SOT89-5
45
2
3
21
SOT223
45
3
4
321
REQ/GNT
PCI SLOTPCI SLOT
INTD*
A A
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
PCI Device / VID Table
PCI Device / VID Table
PCI Device / VID Table
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
FOXCONN PCEG
538Monday, June 13, 2005
538Monday, June 13, 2005
538Monday, June 13, 2005
1
of
of
of
AC
AC
AC
5
4
3
2
1
C179
C179
0.22uF
0.22uF
*
*
C0603
C0603
DUMMY
DUMMY
10V, X7R, +/-10%
10V, X7R, +/-10%
HTCPU_UP15 HTCPU_UP14 HTCPU_UP13 HTCPU_UP12 HTCPU_UP11 HTCPU_UP10 HTCPU_UP9 HTCPU_UP8 HTCPU_UP7 HTCPU_UP6 HTCPU_UP5 HTCPU_UP4 HTCPU_UP3 HTCPU_UP2 HTCPU_UP1 HTCPU_UP0
HTCPU_UP*15 HTCPU_UP*14 HTCPU_UP*13 HTCPU_UP*12 HTCPU_UP*11 HTCPU_UP*10 HTCPU_UP*9 HTCPU_UP*8 HTCPU_UP*7 HTCPU_UP*6 HTCPU_UP*5 HTCPU_UP*4 HTCPU_UP*3 HTCPU_UP*2 HTCPU_UP*1 HTCPU_UP*0
+1.2V_HT
U16A
U16A
SEC 1 OF 6
SEC 1 OF 6
<PART_NAME>
E2
V_HT
E1
V_HT
F1
V_HT
F2
V_HT
R5
HT_RXD<15>
P3
HT_RXD<14>
N5
HT_RXD<13>
M3
HT_RXD<12>
K3
HT_RXD<11>
J5
HT_RXD<10>
H3
HT_RXD<9>
G5
HT_RXD<8>
R3
HT_RXD<7>
N1
HT_RXD<6>
N3
HT_RXD<5>
L1
HT_RXD<4>
J1
HT_RXD<3>
J3
HT_RXD<2>
G1
HT_RXD<1>
G3
HT_RXD<0>
T5
HT_RXD<15>*
P4
HT_RXD<14>*
P5
HT_RXD<13>*
M4
HT_RXD<12>*
K4
HT_RXD<11>*
K5
HT_RXD<10>*
H4
HT_RXD<9>*
H5
HT_RXD<8>*
R2
HT_RXD<7>*
P1
HT_RXD<6>*
N2
HT_RXD<5>*
M1
HT_RXD<4>*
K1
HT_RXD<3>*
J2
HT_RXD<2>*
H1
HT_RXD<1>*
G2
HT_RXD<0>*
L3
HT_RXCLK<0>
L2
HT_RXCLK<0>*
L5
HT_RXCLK<1>
M5
HT_RXCLK<1>*
R1
HT_RXCTL
T1
HT_RXCTL*
<PATH>
<PATH>
4
<PART_NAME>
V_HT V_HT V_HT V_HT
HT_TXD<15> HT_TXD<14> HT_TXD<13> HT_TXD<12> HT_TXD<11> HT_TXD<10>
HT_TXD<9> HT_TXD<8> HT_TXD<7> HT_TXD<6> HT_TXD<5> HT_TXD<4> HT_TXD<3> HT_TXD<2> HT_TXD<1> HT_TXD<0>
HT_TXD<15>* HT_TXD<14>* HT_TXD<13>* HT_TXD<12>* HT_TXD<11>* HT_TXD<10>*
HT_TXD<9>* HT_TXD<8>* HT_TXD<7>* HT_TXD<6>* HT_TXD<5>* HT_TXD<4>* HT_TXD<3>* HT_TXD<2>* HT_TXD<1>* HT_TXD<0>*
HT_TXCLK<0>
HT_TXCLK<0>*
HT_TXCLK<1>
HT_TXCLK<1>*
HT_TXCTL HT_TXCTL*
AG4 AG3 AG2 AG1
V4 Y5 Y4 AB5 AD5 AD4 AF5 AF4 V1 W2 Y1 AA2 AC2 AD1 AE2 AF1
V3 W5 Y3 AA5 AC5 AD3 AE5 AF3 U1 W3 W1 AA3 AC3 AC1 AE3 AE1
AB1 AA1
AB4 AB3
U2 U3
3
HTCPU_DWN15 HTCPU_DWN14 HTCPU_DWN13 HTCPU_DWN12 HTCPU_DWN11 HTCPU_DWN10 HTCPU_DWN9 HTCPU_DWN8 HTCPU_DWN7 HTCPU_DWN6 HTCPU_DWN5 HTCPU_DWN4 HTCPU_DWN3 HTCPU_DWN2 HTCPU_DWN1 HTCPU_DWN0
HTCPU_DWN*15 HTCPU_DWN*14 HTCPU_DWN*13 HTCPU_DWN*12 HTCPU_DWN*11 HTCPU_DWN*10 HTCPU_DWN*9 HTCPU_DWN*8 HTCPU_DWN*7 HTCPU_DWN*6 HTCPU_DWN*5 HTCPU_DWN*4 HTCPU_DWN*3 HTCPU_DWN*2 HTCPU_DWN*1 HTCPU_DWN*0
HTCPU_DWNCLK0 HTCPU_DWNCLK0*
HTCPU_DWNCLK1 HTCPU_DWNCLK1*
HTCPU_DWNCNTL HTCPU_DWNCNTL*
C247
C247
4.7uF
4.7uF
10V, Y5V, +80%/-20%C1206
10V, Y5V, +80%/-20%C1206
*
*
HTCPU_DWN[15..0]
HTCPU_DWN*[15..0]
HTCPU_DWNCLK0 14 HTCPU_DWNCLK0* 14
HTCPU_DWNCLK1 14 HTCPU_DWNCLK1* 14
HTCPU_DWNCNTL 14 HTCPU_DWNCNTL* 14
HTCPU_DWN[15..0] 14
HTCPU_DWN*[15..0] 14
2
Retention Module for CPU
814-PS21BA
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Athlon 64-1 HyperTransport
Athlon 64-1 HyperTransport
Athlon 64-1 HyperTransport
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
FOXCONN PCEG
C51GK8MB
C51GK8MB
C51GK8MB
638Wednesday, July 20, 2005
638Wednesday, July 20, 2005
638Wednesday, July 20, 2005
1
of
of
of
AB
AB
AB
D D
C183
C183
C190
C190
0.22uF
0.22uF
0.22uF
0.22uF
*
*
*
*
C0603
C0603
C0603
C0603
DUMMY
DUMMY
DUMMY
DUMMY
10V, X7R, +/-10%
10V, X7R, +/-10%
10V, X7R, +/-10%
10V, X7R, +/-10%
HTCPU_UP*[15..0]
5
HTCPU_UP[15..0]
HTCPU_UPCLK014 HTCPU_UPCLK0*14
HTCPU_UPCLK114 HTCPU_UPCLK1*14
HTCPU_UPCNTL14 HTCPU_UPCNTL*14
HTCPU_UPCLK0 HTCPU_UPCLK0*
HTCPU_UPCLK1 HTCPU_UPCLK1*
HTCPU_UPCNTL HTCPU_UPCNTL*
HTCPU_UP[15..0]14
C C
HTCPU_UP*[15..0]14
B B
A A
5
5
MEM_DATA[63..0]
MEM_DATA63 MEM_DATA62 MEM_DATA61 MEM_DATA60 MEM_DATA59 MEM_DATA58 MEM_DATA57 MEM_DATA56 MEM_DATA55 MEM_DATA54 MEM_DATA53 MEM_DATA52 MEM_DATA51 MEM_DATA50 MEM_DATA49 MEM_DATA48 MEM_DATA47 MEM_DATA46 MEM_DATA45 MEM_DATA44 MEM_DATA43 MEM_DATA42 MEM_DATA41 MEM_DATA40 MEM_DATA39 MEM_DATA38 MEM_DATA37 MEM_DATA36 MEM_DATA35 MEM_DATA34 MEM_DATA33 MEM_DATA32 MEM_DATA31 MEM_DATA30 MEM_DATA29 MEM_DATA28 MEM_DATA27 MEM_DATA26 MEM_DATA25 MEM_DATA24 MEM_DATA23 MEM_DATA22 MEM_DATA21 MEM_DATA20 MEM_DATA19 MEM_DATA18 MEM_DATA17 MEM_DATA16 MEM_DATA15 MEM_DATA14 MEM_DATA13 MEM_DATA12 MEM_DATA11 MEM_DATA10 MEM_DATA9 MEM_DATA8 MEM_DATA7 MEM_DATA6 MEM_DATA5 MEM_DATA4 MEM_DATA3 MEM_DATA2 MEM_DATA1 MEM_DATA0
MEM_DATA[63..0]11,12,39
D D
C C
B B
A A
AE16 AG17 AG18 AE18 AJ16 AG16 AE17 AJ18 AJ20 AE20 AE23 AG24 AG19 AE19 AJ24 AE24 AG25 AE25 AD25 AC25 AF25 AJ26 AE27 AD29 AB25 AB27 AA28
AC26 AB29 AA27
4
U16C
U16C
Y25
Y27 N25
M25
K27
K25 M29 M27
K29
J27 H27 G27 D27 F25 H29 G26 E26 G25 G23 F23 C20 F19 E24 C24 G19 E19 E18 G17 E16 E15 G18 C18 G16 C16
I134
I134
4
MEMDATA<63> MEMDATA<62> MEMDATA<61> MEMDATA<60> MEMDATA<59> MEMDATA<58> MEMDATA<57> MEMDATA<56> MEMDATA<55> MEMDATA<54> MEMDATA<53> MEMDATA<52> MEMDATA<51> MEMDATA<50> MEMDATA<49> MEMDATA<48> MEMDATA<47> MEMDATA<46> MEMDATA<45> MEMDATA<44> MEMDATA<43> MEMDATA<42> MEMDATA<41> MEMDATA<40> MEMDATA<39> MEMDATA<38> MEMDATA<37> MEMDATA<36> MEMDATA<35> MEMDATA<34> MEMDATA<33> MEMDATA<32> MEMDATA<31> MEMDATA<30> MEMDATA<29> MEMDATA<28> MEMDATA<27> MEMDATA<26> MEMDATA<25> MEMDATA<24> MEMDATA<23> MEMDATA<22> MEMDATA<21> MEMDATA<20> MEMDATA<19> MEMDATA<18> MEMDATA<17> MEMDATA<16> MEMDATA<15> MEMDATA<14> MEMDATA<13> MEMDATA<12> MEMDATA<11> MEMDATA<10> MEMDATA<9> MEMDATA<8> MEMDATA<7> MEMDATA<6> MEMDATA<5> MEMDATA<4> MEMDATA<3> MEMDATA<2> MEMDATA<1> MEMDATA<0>
SEC 3 OF 6
SEC 3 OF 6
SOCKET_939
SOCKET_939
MEMCHECK<7> MEMCHECK<6> MEMCHECK<5> MEMCHECK<4> MEMCHECK<3> MEMCHECK<2> MEMCHECK<1> MEMCHECK<0>
MEMDM<8>* MEMDM<7>* MEMDM<6>* MEMDM<5>* MEMDM<4>* MEMDM<3>* MEMDM<2>* MEMDM<1>* MEMDM<0>*
MEMDQS<8> MEMDQS<7> MEMDQS<6> MEMDQS<5> MEMDQS<4> MEMDQS<3> MEMDQS<2> MEMDQS<1> MEMDQS<0>
MEMCLK2_L<0>
MEMCLK2_L<0>*
MEMCLK2_L<1>
MEMCLK2_L<1>*
MEMCLK2_L<2>
MEMCLK2_L<2>*
MEMCLK1_L<0>
MEMCLK1_L<0>*
MEMCLK1_L<1>
MEMCLK1_L<1>*
MEMCLK1_L<2>
MEMCLK1_L<2>*
MEMADDA<13> MEMADDA<12> MEMADDA<11> MEMADDA<10>
MEMADDA<9> MEMADDA<8> MEMADDA<7> MEMADDA<6> MEMADDA<5> MEMADDA<4> MEMADDA<3> MEMADDA<2> MEMADDA<1> MEMADDA<0>
MEMBANKA<1> MEMBANKA<0>
MEMRASA* MEMCASA*
MEMCS_1L<1>* MEMCS_1L<0>*
MEMCS_2L<1>* MEMCS_2L<0>*
MEMCKEA MEMCKEB
MEMWEA*
Y29 W27 P27 R25 W26 V25 R28 P29
V29 AF17 AG21 AH27 AA25 L26 F27 G20 E17
U26 AH17 AG20 AG26 AA26 L25 E27 E20 F17
T27 U27
G21 G22
AF21 AE21
R27 R26
D23 E23
AH23 AG23
AF23 C26 E28 V27 F29 H25 G28 J26 J25 L27 L28 N26 P25 U25
W25 AC27
AD27 AF27 AE28
AG28 AF29
AG27 AE26
G24 E25
3
MEM_ECC7 MEM_ECC6 MEM_ECC5 MEM_ECC4 MEM_ECC3 MEM_ECC2 MEM_ECC1 MEM_ECC0
MEM_DM#8 MEM_DM#7 MEM_DM#6 MEM_DM#5 MEM_DM#4 MEM_DM#3 MEM_DM#2 MEM_DM#1 MEM_DM#0
MEM_DQS8 MEM_DQS7 MEM_DQS6 MEM_DQS5 MEM_DQS4 MEM_DQS3 MEM_DQS2 MEM_DQS1 MEM_DQS0
MEM_A_ADD13 MEM_A_ADD12 MEM_A_ADD11 MEM_A_ADD10 MEM_A_ADD9 MEM_A_ADD8 MEM_A_ADD7 MEM_A_ADD6 MEM_A_ADD5 MEM_A_ADD4 MEM_A_ADD3 MEM_A_ADD2 MEM_A_ADD1 MEM_A_ADD0
MEM_A_BA1 MEM_A_BA0
3
MEM_A2_CLK0 MEM_A2_CLK0#
MEM_A2_CLK1 MEM_A2_CLK1#
MEM_A2_CLK2 MEM_A2_CLK2#
MEM_A1_CLK0 MEM_A1_CLK0#
MEM_A1_CLK1 MEM_A1_CLK1#
MEM_A1_CLK2 MEM_A1_CLK2#
MEM_A_BA[1..0]
MEM_A_RAS# MEM_A_CAS# MEM_A_WE#
MEM_A1_CS1# MEM_A1_CS0#
MEM_A2_CS1# MEM_A2_CS0#
MEM_A1_CKE MEM_A2_CKE
MEM_ECC[7..0]
MEM_DM#[8..0]
MEM_DQS[8..0]
MEM_A_ADD[13..0]
MEM_ECC[7..0] 11,12,39
MEM_DM#[8..0] 11,12,39
MEM_DQS[8..0] 11,12,39
MEM_A2_CLK0 12,38 MEM_A2_CLK0# 12,38
MEM_A2_CLK1 12,38 MEM_A2_CLK1# 12,38
MEM_A2_CLK2 12,38 MEM_A2_CLK2# 12,38
MEM_A1_CLK0 11,38 MEM_A1_CLK0# 11,38
MEM_A1_CLK1 11,38 MEM_A1_CLK1# 11,38
MEM_A1_CLK2 11,38 MEM_A1_CLK2# 11,38
MEM_A_ADD[13..0] 11,12,38,39
MEM_A_BA[1..0] 11,12,38,39
MEM_A_RAS# 11,12,38,39 MEM_A_CAS# 11,12,38,39 MEM_A_WE# 11,12,38,39
MEM_A1_CS1# 11,38,39 MEM_A1_CS0# 11,38,39
MEM_A2_CS1# 12,38,39 MEM_A2_CS0# 12,38,39
MEM_A1_CKE 11,38,39 MEM_A2_CKE 12,38,39
2
Title
Title
Title
Athlon 64- 2 DDR -1
Athlon 64- 2 DDR -1
Athlon 64- 2 DDR -1
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
1
FOXCONN PCEG
FOXCONN PCEG
FOXCONN PCEG
C51GK8MB
C51GK8MB
C51GK8MB
738Tuesday, July 19, 2005
738Tuesday, July 19, 2005
738Tuesday, July 19, 2005
1
ACustom
ACustom
ACustom
of
of
of
5
D D
VTT_DDR_SUS
C262
C270
C270
100pF
100pF
*
*
C0603
C0603
50V, NPO, +/-5%
50V, NPO, +/-5%
PLACE CAPS NEXT TO PINS AG14,AK14,AJ14,AH14,A14
C C
LAYOUT: 5MIL TRACE 10 MIL SPACE LAYOUT: PLACE WITHIN 1 INCH OF CPU
+2.6V_SUS
R210
R210
34.8
34.8
R0603
B B
A A
R0603
R211
R211
34.8
34.8
R0603
R0603
C262
C263
C263
100pF
100pF
*
*
C0603
C0603
+/-1%
+/-1%
+/-1%
+/-1%
*
*
5
1nF
1nF
*
*
C0603
C0603
CPU_MEMZN CPU_MEMZP
C280
C280
1nF
1nF
C0603
C0603
*
*
C267
C267
1nF
1nF
C0603
C0603
50V, NPO, +/-5%
50V, NPO, +/-5%
MEM_DATA[127..64]11,12,39
C268
C268
100pF
100pF
*
*
C0603
C0603
MEM_DATA[127..64]
+2.6V_SUS
R202
R202 15
15
R0603
R0603
R198
R198 15
15
R0603
R0603
4
VTT_DDR_SUS
B14 C14 D14 E14
AG14
AK14 AJ14 AH14
MEM_DATA127
AJ15
MEM_DATA126
AL16
MEM_DATA125
AL18
MEM_DATA124
AL19
MEM_DATA123
AL15
MEM_DATA122
AK15
MEM_DATA121
AK17
MEM_DATA120
AJ17
MEM_DATA119
AH19
MEM_DATA118
AL21
MEM_DATA117
AJ23
MEM_DATA116
AL25
MEM_DATA115
AK19
MEM_DATA114
AJ19
MEM_DATA113
AL24
MEM_DATA112
AK25
MEM_DATA111
AJ25
MEM_DATA110
AL26
MEM_DATA109
AG29
MEM_DATA108
AF31
MEM_DATA107
AH25
MEM_DATA106
AL27
MEM_DATA105
AJ31
MEM_DATA104
AG31
MEM_DATA103
AE31
MEM_DATA102
AD31
MEM_DATA101
AB31
MEM_DATA100
AA29
MEM_DATA99
AE29
MEM_DATA98
AC28
MEM_DATA97
AC31
MEM_DATA96
AA30
MEM_DATA95
M31
MEM_DATA94
L30
MEM_DATA93
H31
MEM_DATA92
G31
MEM_DATA91
L31
MEM_DATA90
L29
MEM_DATA89
J28
MEM_DATA88
G30
MEM_DATA87
E30
MEM_DATA86
C31
MEM_DATA85
C27
MEM_DATA84
D25
MEM_DATA83
E31
MEM_DATA82
C30
MEM_DATA81
B27
MEM_DATA80
A27
MEM_DATA79
C23
MEM_DATA78
B23
MEM_DATA77
A20
MEM_DATA76
B19
MEM_DATA75
A25
MEM_DATA74
A24
MEM_DATA73
C19
MEM_DATA72
A19
MEM_DATA71
D17
MEM_DATA70
B17
MEM_DATA69
C15
MEM_DATA68
A15
MEM_DATA67
A18
MEM_DATA66
C17
MEM_DATA65
D15
MEM_DATA64
CPU_MEMZN
C272
C272
10nF
10nF
*
*
+/-1%
+/-1%
C0603
C0603
C264
C264
10nF
10nF
*
*
+/-1%
+/-1%
C0603
C0603
4
CPU_MEMZP
CPU_MEM_VREF
C269
C269
*
*
0.1uF
0.1uF
C0603
C0603
B15
AF15 AE15
F15
3
U16D
U16D
SOCKET_AMD_K8_939
SOCKET_AMD_K8_939
SEC 4 OF 6
SEC 4 OF 6
VTT VTT VTT VTT VTT VTT VTT VTT
MEMDATA<127> MEMDATA<126> MEMDATA<125> MEMDATA<124> MEMDATA<123> MEMDATA<122> MEMDATA<121> MEMDATA<120> MEMDATA<119> MEMDATA<118> MEMDATA<117> MEMDATA<116> MEMDATA<115> MEMDATA<114> MEMDATA<113> MEMDATA<112> MEMDATA<111> MEMDATA<110> MEMDATA<109> MEMDATA<108> MEMDATA<107> MEMDATA<106> MEMDATA<105> MEMDATA<104> MEMDATA<103> MEMDATA<102> MEMDATA<101> MEMDATA<100> MEMDATA<99> MEMDATA<98> MEMDATA<97> MEMDATA<96> MEMDATA<95> MEMDATA<94> MEMDATA<93> MEMDATA<92> MEMDATA<91> MEMDATA<90> MEMDATA<89> MEMDATA<88> MEMDATA<87> MEMDATA<86> MEMDATA<85> MEMDATA<84> MEMDATA<83> MEMDATA<82> MEMDATA<81> MEMDATA<80> MEMDATA<79> MEMDATA<78> MEMDATA<77> MEMDATA<76> MEMDATA<75> MEMDATA<74> MEMDATA<73> MEMDATA<72> MEMDATA<71> MEMDATA<70> MEMDATA<69> MEMDATA<68> MEMDATA<67> MEMDATA<66> MEMDATA<65> MEMDATA<64>
MEMZN MEMZP
MEMVREF
I138
I138
3
SOCKET_939
SOCKET_939
MEMCHECK<15> MEMCHECK<14> MEMCHECK<13> MEMCHECK<12> MEMCHECK<11> MEMCHECK<10>
MEMCHECK<9> MEMCHECK<8>
MEMDM<17>* MEMDM<16>* MEMDM<15>* MEMDM<14>* MEMDM<13>* MEMDM<12>* MEMDM<11>* MEMDM<10>*
MEMDM<9>*
MEMDQS<17> MEMDQS<16> MEMDQS<15> MEMDQS<14> MEMDQS<13> MEMDQS<12> MEMDQS<11> MEMDQS<10>
MEMDQS<9>
MEMCLK2_H<0> MEMCLK2_H<0>*
MEMCLK2_H<1> MEMCLK2_H<1>*
MEMCLK2_H<2> MEMCLK2_H<2>*
MEMCLK1_H<0> MEMCLK1_H<0>*
MEMCLK1_H<1> MEMCLK1_H<1>*
MEMCLK1_H<2> MEMCLK1_H<2>*
MEMADDB<13> MEMADDB<12> MEMADDB<11> MEMADDB<10>
MEMADDB<9> MEMADDB<8> MEMADDB<7> MEMADDB<6> MEMADDB<5> MEMADDB<4> MEMADDB<3> MEMADDB<2> MEMADDB<1> MEMADDB<0>
MEMBANKB<1> MEMBANKB<0>
MEMRASB* MEMCASB* MEMWEB*
MEMRESET*
MEMCS_1H<1>* MEMCS_1H<0>*
MEMCS_2H<1>* MEMCS_2H<0>*
MEMCKEC MEMCKED
VTT_SENSE
AA31 W29 N31 N29 W28 W31 R29 P31
V31 AL17 AK21 AK27 AC29 J30 B29 B21 A16
U30 AH15 AL20 AJ27 AC30 J29 A28 A21 A17
T31 U31
C21 D21
AJ21 AH21
R31 R30
A22 A23
AL22 AL23
AK23 A26 A29 W30 C29 E29 D31 G29 F31 J31 K31 N28 N30 U29
Y31 AE30
AG30 AK29 AH31
D19 AL29
AJ29 AL28
AJ30 B25
C25 AF13
MEM_ECC15 MEM_ECC14 MEM_ECC13 MEM_ECC12 MEM_ECC11 MEM_ECC10 MEM_ECC9 MEM_ECC8
MEM_DM#17 MEM_DM#16 MEM_DM#15 MEM_DM#14 MEM_DM#13 MEM_DM#12 MEM_DM#11 MEM_DM#10 MEM_DM#9
MEM_DQS17 MEM_DQS16 MEM_DQS15 MEM_DQS14 MEM_DQS13 MEM_DQS12 MEM_DQS11 MEM_DQS10 MEM_DQS9
MEM_B_ADD13 MEM_B_ADD12 MEM_B_ADD11 MEM_B_ADD10 MEM_B_ADD9 MEM_B_ADD8 MEM_B_ADD7 MEM_B_ADD6 MEM_B_ADD5 MEM_B_ADD4 MEM_B_ADD3 MEM_B_ADD2 MEM_B_ADD1 MEM_B_ADD0
MEM_B_BA1 MEM_B_BA0
MEM_ECC[15..8]
MEM_DM#[17..9]
MEM_DQS[17..9]
MEM_B2_CLK0 MEM_B2_CLK0#
MEM_B2_CLK1 MEM_B2_CLK1#
MEM_B2_CLK2 MEM_B2_CLK2#
MEM_B1_CLK0 MEM_B1_CLK0#
MEM_B1_CLK1 MEM_B1_CLK1#
MEM_B1_CLK2 MEM_B1_CLK2#
MEM_B_ADD[13..0]
MEM_B_BA[1..0]
MEM_B_RAS# MEM_B_CAS# MEM_B_WE#
TP_MEM_RESET# MEM_B1_CS1#
MEM_B1_CS0# MEM_B2_CS1#
MEM_B2_CS0# MEM_B1_CKE
MEM_B2_CKE
TP_CPU_VTT_SENSE
2
MEM_B2_CLK0 12,38 MEM_B2_CLK0# 12,38
MEM_B2_CLK1 12,38 MEM_B2_CLK1# 12,38
MEM_B2_CLK2 12,38 MEM_B2_CLK2# 12,38
MEM_B1_CLK0 11,38 MEM_B1_CLK0# 11,38
MEM_B1_CLK1 11,38 MEM_B1_CLK1# 11,38
MEM_B1_CLK2 11,38 MEM_B1_CLK2# 11,38
MEM_B_BA[1..0] 11,12,38,39
MEM_B_RAS# 11,12,38,39 MEM_B_CAS# 11,12,38,39 MEM_B_WE# 11,12,38,39
1
MEM_B1_CS1# 11,38,39 MEM_B1_CS0# 11,38,39
MEM_B2_CS1# 12,38,39 MEM_B2_CS0# 12,38,39
MEM_B1_CKE 11,38,39 MEM_B2_CKE 12,38,39
1
2
MEM_ECC[15..8] 11,12,39
MEM_DM#[17..9] 11,12,39
MEM_DQS[17..9] 11,12,39
MEM_B_ADD[13..0] 11,12,38,39
TP30TP30
TP29TP29
1
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Athlon 64- 2 DDR -2
Athlon 64- 2 DDR -2
Athlon 64- 2 DDR -2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
FOXCONN PCEG
C51GK8MB
C51GK8MB
C51GK8MB
838Tuesday, July 19, 2005
838Tuesday, July 19, 2005
838Tuesday, July 19, 2005
1
ACustom
ACustom
ACustom
5
D D
+1.2V_HT
R160 44.2
R160 44.2
R0603
R0603
+/-1%
+/-1%
R149
R149
44.2
44.2
+/-1%
+/-1%
R0603
R0603
PLACE WITHIN 1 INCH 5MIL TRACE 10MIL SPACE
*
*
CPU_CLK
C244
CPU_CLK*
R177
R177 200
200
+/-1%
+/-1%
R0603
R0603
dummy
dummy
C244
3.9nF
3.9nF
50V, X7R, +/-10%
50V, X7R, +/-10%
C0603
C0603
*
*
C243
C243
3.9nF
3.9nF
50V, X7R, +/-10%
50V, X7R, +/-10%
C0603
C0603
R176
R176 200
200
+/-1%
+/-1%
R0603
R0603
dummy
dummy
R183
R183 169
169
R0603
R0603
+/-1%
+/-1%
+1.2V_HT
C C
LAYOUT: PLACE 169 OHM WITHIN 0.5INCH OF CPU
ROUTE AS DIF 5/5/5/20
B B
A A
CPU_CLK14
CPU_CLK*14
+2.6V_SUS
R148
R148
49.9
49.9
R0603
R0603
+/-1%
+/-1%
ROUTE AS DIFF PAIR
10/5/10 10
R203 820
R203 820
R0603 +/-5%
R0603 +/-5%
+2.5V
4
+2.5V
C229
C229
10uF
10uF
*
*
*
*
C0805
C0805
HTCPU_RST*14
HTCPU_PWRGD14
HTCPU_STOP*14
CPU_CORE_FB+32 CPU_CORE_FB-32
Modify R206 Vaule to 680R
R206 680R0603 +/-5%R206 680R0603 +/-5% R205 680R0603 +/-5%R205 680R0603 +/-5%
R161
R161
49.9
49.9
R0603
R0603
+/-1%
+/-1%
CP17
CP17
L18
L18 X_FB L0805 200 Ohm
X_FB L0805 200 Ohm
dummy
dummy
C235
C235
0.1uF
0.1uF
C0603
C0603
HTCPU_RST* HTCPU_PWRGD HTCPU_STOP*
CPU_CORE_FB+ CPU_CORE_FB-
TP17TP17 TP31TP31
TP32TP32 TP27TP27
R190 820
R190 820
R0603 +/-5%
R0603 +/-5%
TP25TP25 TP18TP18
TP15TP15 TP23TP23 TP20TP20
X_COPPER
X_COPPER
21
C234
C234
0.1uF
0.1uF
*
*
C0603
C0603
L0_REF1 L0_REF0
TP_CPU_CORESENSE
1
TP_CPU_VDDIOFB
1
TP_CPU_VDDIOFB#
1
TP_CPU_VDDIOSENSE
1
CPUCLKIN CPUCLKIN#
STRAP_HI_E11 STRAP_LO_F11#
TP10TP10
TP11TP11
1 1
1 1 1
STRAP_HI_AJ12 STRAP_HI_AF12
STRAP_HI_T3 STRAP_LO_T4#
TP6TP6 TP7TP7 TP4TP4 TP3TP3 TP14TP14 TP13TP13 TP21TP21 TP16TP16
*
*
C206
C206
X_470pF
X_470pF
C0603
C0603
*
*
1 1
CPU_DBRDY CPU_TMS
CPU_TCK CPU_TRST# CPU_TDI
1 1 1 1 1 1 1 1
C233
C233
10nF
10nF
C0603
C0603
*
*
TP_CPU_C5 TP_CPU_A5
TP_CPU_A4 TP_CPU_D4 TP_CPU_B4 TP_CPU_C4 TP_CPU_C7 TP_CPU_C6 TP_CPU_AL8 TP_CPU_AL7
C205
C205
X_470pF
X_470pF
C0603
C0603
3
+2.5V
U16B
U16B
SOCKET_AMD_K8_939
SOCKET_AMD_K8_939
SEC 2 OF 6
C3 B3 A3
F8 E8 B6
D1 C1
E5 E6 E7
Y24 AA24 AE13
A8 B8
E11
F11
C5 A5
B11
AG6 AG7
AF8
AJ9
AJ12 AF12
T3 T4
A4 D4 B4 C4 C7
C6 AL8 AL7
AE22 AG22
AH8
AH29
AJ4 AJ5 AJ6 AJ7 AJ8
AJ22 AJ28
AK3 AK4 AK6 AK8
AK10 AK12
AL3 AL4 AL5 AL6
SEC 2 OF 6
VDDA VDDA VDDA
RESET* PWROK LDTSTOP*
L0_REF1 L0_REF0
COREFB COREFB* CORESENSE
VDDIOFB VDDIOFB* VDDIOSENSE
CLKIN CLKIN*
STRAP_HI_E11 STRAP_LO_F11*
NC_C5 NC_A5
DBRDY
TMS TCK TRST* TDI
STRAP_HI_AJ12 STRAP_HI_AF12
STRAP_HI_T3 STRAP_LO_T4*
NC_A4 NC_D4 NC_B4 NC_C4 NC_C7 NC_C6 NC_AL8 NC_AL7
FREE FREE FREE FREE FREE FREE FREE FREE FREE FREE FREE FREE FREE FREE FREE FREE FREE FREE FREE FREE FREE
I1
I1
SOCKET_939
SOCKET_939
RN16
RN16
*
*
1 3 5 7 8
680
680
+/-5%
+/-5%
8P4R0603
8P4R0603
THERMTRIP*
THERMDA THERMDC
STRAP_LO_B13* STRAP_LO_C10*
FBCLKOUT
FBCLKOUT*
STRAP_LO_AG9*
STRAP_LO_AH6* STRAP_LO_AF10* STRAP_LO_AH10* STRAP_LO_AJ10*
VTT_AL14
VTT_A14
2 4 6
VID<4> VID<3> VID<2> VID<1> VID<0>
NC_C13
NC_E9
DBREQ*
NC_V5 NC_U5
FREE FREE FREE FREE FREE FREE FREE FREE FREE FREE FREE FREE FREE FREE FREE FREE FREE FREE FREE FREE
TDO
CPU_THERMTRIP* HTCPU_STOP* HTCPU_PWRGD HTCPU_RST*
AG10 AJ2
AJ1 A13
A12 C12 A11 A10
C13 E9
B13 C10
F13 E13
LAYOUT: ROUTE 80 OHM DIFF IMPEDENCE LAYOUT: PLACE WITHIN 0.5 INCH OF CPU
CPU_DBREQ#
A6
STRAP_LO_AG9#
AG9
STRAP_LO_AH6#
AH6
STRAP_LO_AF10#
AF10
STRAP_LO_AH10#
AH10
STRAP_LO_AJ10#
AJ10
CPU_TDO
AG8
TP_CPU_V5
V5
TP_CPU_U5
U5 AL14
A14 AL9
AL10 AL11 AL12 C22 C28 D8 D11 D12 D29 E21 E22 G15 N27 T25 T29 U28 C11 AG15 AH12
CPU_THERMTRIP*
CPU_THERMDA CPU_THERMDC
K8_VID4 26 K8_VID3 26 K8_VID2 26 K8_VID1 26 K8_VID0 26
TP_CPU_C13 TP_CPU_E9
STRAP_LO_B13# STRAP_LO_C10#
FBCLKOUT
FBCLKOUT#
2
1 1
1 1
1 1 1
1 1
1
*
*
CPU_THERMTRIP* 17 CPU_THERMDA 26
CPU_THERMDC 26
TP28TP28
R197 1K R0603 +/-5%R197 1K R0603 +/-5%
TP24TP24
R194
R194
80.6
80.6
R0603
R0603
+/-1%
+/-1%
TP12TP12 TP22TP22
TP1TP1 TP26TP26 TP2TP2
TP19TP19 TP9TP9
+2.6V_SUS
TP5TP5
C271
C271
0.1uF
0.1uF
50V, Y5V, +80%/-20%
50V, Y5V, +80%/-20%
C0603
C0603
STRAP_LO_AH10# STRAP_LO_AF10# STRAP_LO_AG9# STRAP_LO_AH6#
8/5/8/20
R187
R187
1K
1K
R0603
R0603
+/-5%
+/-5%
RN21
RN21
1
*
*
3 5 7 8
1K
1K
+/-5%
+/-5%
8P4R0603
8P4R0603
ROUTING 10/10/10
R201
R201
1K
1K
R0603
R0603
+/-5%
+/-5%
2 4 6
1
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Athlon 64- 3 MISC
Athlon 64- 3 MISC
Athlon 64- 3 MISC
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet
FOXCONN PCEG
C51GK8MB
C51GK8MB
C51GK8MB
1
ACustom
ACustom
ACustom
of
938Wednesday, July 20, 2005
938Wednesday, July 20, 2005
938Wednesday, July 20, 2005
5
4
+2.6V_SUS+V_CPU
3
2
1
D D
C C
U16F
U16F
I76
I76
B B
10V, X7R, +/-10%
10V, X7R, +/-10%
A A
R19
R17
R15
R13
R11
VDD
VDD
VDD
VDD
VDD
U16E
U16E
VDD
VDD
VDD
VDD
VDD
SEC 5 OF 6
SEC 5 OF 6
I75
I75
AA9
AA7
AA4
AA13
AA11
H23
J12
J14
J16
H26
H28
J10
GND
GND
GND
GND
GND
GNDJ6GNDJ8GND
GND
SEC 6 OF 6
SEC 6 OF 6
GND
GND
GND
GND
GND
GND
GNDA9GNDA7GND
AA8
AA6
AA18
AA16
AA14
AA12
AA10
+2.6V_SUS
PLACE TOP SIDE UNDER CPU HEATSINK NEXT TO MEM CLKS
C419
C419
C422
C422
0.22uF
0.22uF
0.22uF
0.22uF
*
*
*
*
C0603
C0603
C0603
C0603
10V, X7R, +/-10%
10V, X7R, +/-10%
10V, X7R, +/-10%
10V, X7R, +/-10%
+1.2V_HT
C164
C164
0.22uF
0.22uF
*
*
C0603
C0603
10V, X7R, +/-10%
10V, X7R, +/-10%
10V, X7R, +/-10%
10V, X7R, +/-10%
R21
VDD
VDD
VDD
AA19
AA17
AA15
J18
J20
J22
GND
GND
GND
GND
AB2
AA22
AA20
*
*
*
*
T12
T10
VDD
VDDT8VDDT6VDDT2VDD
VDD
VDD
VDD
VDD
AB8
AB6
AA21
J24
GND
GND
GND
GND
GND
GND
AB9
AB7
AB11
C418
C418
0.22uF
0.22uF
*
*
C0603
C0603
10V, X7R, +/-10%
10V, X7R, +/-10%
C198
C198
0.22uF
0.22uF
*
*
C0603
C0603
10V, X7R, +/-10%
10V, X7R, +/-10%
T18
T16
T14
VDD
VDD
VDD
VDD
VDD
VDD
AB14
AB12
AB10
K13
K11
GND
GNDK9GNDK7GNDK2GND
GND
GND
GND
AB17
AB15
AB13
C420
C420
0.22uF
0.22uF
C0603
C0603
10V, X7R, +/-10%
10V, X7R, +/-10%
C157
C157
0.22uF
0.22uF
C0603
C0603
T20
VDD
VDD
VDD
VDD
VDD
AC9
AB20
AB18
AB16
K21
K19
K17
K15
GND
GND
GND
GND
GND
GND
GND
GND
AB26
AB23
AB21
AB19
C285
C285
0.22uF
0.22uF
*
*
C0603
C0603
U19
U17
U15
U13
U11
VDD
VDD
VDD
VDD
VDDU9VDDU7VDDU4VDD
VDD
VDD
VDD
VDD
VDD
AC19
AC17
AC15
AC13
AC11
K28
K26
K23
GND
GND
GND
GND
GND
GND
GND
GND
AC6
AC4
AB28
AC12
AC10
C311
C311
0.22uF
0.22uF
*
*
C0603
C0603
10V, X7R, +/-10%
10V, X7R, +/-10%
10V, X7R, +/-10%
10V, X7R, +/-10%
U21
VDD
VDD
AD2
GND
AC14
VDD
VDD
AD8
AD6
L12
L10
GND
GNDL8GNDL6GNDL4GND
GND
GND
AC18
AC16
*
*
V12
V10
VDD
VDDV8VDDV6VDD
VDD
VDD
AD12
AD10
L16
L14
GND
GND
GND
GND
AC22
AC20
C468
C468
0.22uF
0.22uF
C0603
C0603
10V, X7R, +/-10%
10V, X7R, +/-10%
V20
V18
V16
V14
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
AE7
AE4
AD18
AD16
AD14
L24
L22
L20
L18
GND
GND
GND
GND
GND
GND
GND
GND
GND
AD9
AD7
AD13
AD11
AC24
C273
C273
0.22uF
0.22uF
*
*
C0603
C0603
10V, X7R, +/-10%
10V, X7R, +/-10%
+V_CPU
C634
C634
0.22uF
0.22uF
*
*
C0603
C0603
10V, X7R, +/-10%
10V, X7R, +/-10%
W15
W13
W11
VDD
VDD
VDDW9VDDW7VDD
VDD
VDD
VDD
VDD
AK5
AE9
AJ11
AE11
M15
M13
M11
GND
GND
GNDM9GNDM7GND
GND
GND
GND
GND
AD21
AD19
AD17
AD15
*
*
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
C653
C653
0.22uF
0.22uF
*
*
C0603
C0603
W17
VDD
VDD
AK7
M17
GND
GND
AD23
C314
C314
4.7uF
4.7uF
C0805
C0805
10V, X7R, +/-10%
10V, X7R, +/-10%
W21
W19
VDD
VDD
VDD
VDDB5VDD
VDD
VDD
B12
B10
AK9
AK11
M28
M26
M23
M21
M19
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AE8
AE6
AE10
AD28
AD26
C308
C308
4.7uF
4.7uF
*
*
C0805
C0805
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
C648
C648
0.22uF
0.22uF
*
*
C0603
C0603
10V, X7R, +/-10%
10V, X7R, +/-10%
Y18
Y16
Y14
Y12
Y10
VDD
VDD
VDD
VDD
VDDY8VDDY6VDDY2VDD
VDD
VDDG9VDDG7VDD
VDD
D10
G13
G11
N14
N12
N10
GND
GND
GNDN8GNDN6GND
GND
GND
GND
GND
GND
AF7
AF6
AF2
AE14
AE12
C312
C312
4.7uF
4.7uF
*
*
C0805
C0805
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
C638
C638
0.22uF
0.22uF
*
*
C0603
C0603
10V, X7R, +/-10%
10V, X7R, +/-10%
AB30
AB24
AB22
AA23
Y20
VDD
VDDIO
VDDIO
VDDIO
VDDIO
VDD
VDD
VDDH8VDDH6VDDH2VDD
H14
H12
H10
N24
N22
N20
N18
N16
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AF9
AF22
AF20
AF16
AF14
AF11
C283
C283
4.7uF
4.7uF
*
*
C0805
C0805
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
C631
C631
0.22uF
0.22uF
*
*
C0603
C0603
10V, X7R, +/-10%
10V, X7R, +/-10%
AD22
AD20
AC23
AC21
VDDIO
VDDIO
VDDIO
VDDIO
VDD
VDD
H18
H16
P13
P11
GND
GNDP9GNDP7GNDP2GND
GND
GND
GND
GND
AG5
AF28
AF26
AF24
C649
C649
0.22uF
0.22uF
*
*
C0603
C0603
AK26
AK24
AK22
AK20
AK18
AK16
AH30
AF30
AD30
AD24
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDK8VDDK6VDD
VDD
VDD
VDD
VDD
VDDJ9VDDJ7VDDJ4VDD
J19
J17
J15
J13
J11
K12
K10
P28
P26
P23
P21
P19
P17
P15
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AH9
AH7
AH5
AH4
AH3
AH2
AH1
AG12
AG13
AG11
B16
AK30
AK28
VDDIO
VDDIO
VDDIO
VDDIO
VDD
VDD
VDD
VDD
K18
K16
K14
R14
R12
R10
GND
GND
GNDR8GNDR6GNDR4GND
GND
GND
GND
GND
AH16
AH13
AH11
B30
B28
B26
B24
B22
B20
B18
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDD
VDD
VDD
VDDL9VDDL7VDD
VDD
L17
L15
L13
L11
K20
R24
R22
R20
R18
R16
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AJ3
AH28
AH26
AH24
AH22
AH20
AH18
PLACE TO LEFT OF CPU
+1.2V_HT
*
*
H20
F30
D30
VDDIO
VDDIO
VDDIO
VDD
VDD
L21
L19
T15
T13
T11
GND
GND
GNDT9GNDT7GND
GND
GND
GND
AJ13
AL13
AK13
C209
C209
0.1uF
0.1uF
*
*
C060350V, Y5V, +80%/-20%
C060350V, Y5V, +80%/-20%
J23
J21
H30
H24
H22
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDD
VDD
VDDM8VDDM6VDDM2VDD
M14
M12
M10
T26
T23
T21
T19
T17
GND
GND
GND
GND
GND
C208
C208
0.1uF
0.1uF
C0603
C0603
50V, Y5V, +80%/-20%
50V, Y5V, +80%/-20%
K24
K22
VDDIO
VDDIO
VDD
VDD
M18
M16
T28
GND
R23
P30
P24
P22
N23
M30
M24
M22
L23
K30
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDD
VDD
VDD
VDD
VDD
VDDN9VDDN7VDDN4VDD
VDD
N21
N19
N17
N15
N13
N11
M20
U24
U22
U20
U18
U16
U14
U12
U10
GND
GND
GND
GND
GND
GND
GND
GNDU8GNDU6GND
GND
GND
GND
GND
GND
GNDD9GNDD7GNDD6GNDD5GNDD3GNDD2GNDC9GNDC8GNDC2GNDB9GNDB7GND
D24
D22
D20
D18
D16
D13
PLACE BACK SIDE CENTER CAVITY OF CPU
+2.6V_SUS
C656
C656
0.22uF
0.22uF
*
*
C0603
C0603
10V, X7R, +/-10%
10V, X7R, +/-10%
10V, X7R, +/-10%
10V, X7R, +/-10%
PLACE NEAR CPU ON EITHER SIDE
VTT_DDR_SUS
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
U23
T30
T24
T22
VDDIO
VDDIO
VDDIO
VDDIO
VDD
VDDP8VDDP6VDD
P12
P10
V13
V11
GND
GNDV9GNDV7GNDV2GND
GND
GND
D28
D26
C657
C657
0.22uF
0.22uF
*
*
C0603
C0603
10V, X7R, +/-10%
10V, X7R, +/-10%
C305
C305
4.7uF
4.7uF
*
*
C0805
C0805
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
V24
V22
VDDIO
VDD
P16
P14
V17
V15
GND
GNDE4GNDE3GND
E12
E10
*
*
W23
V30
VDDIO
VDDIO
VDDIO
VDD
VDD
VDD
P20
P18
V21
V19
GND
GND
GND
GND
GND
G12
*
*
C265
C265
4.7uF
4.7uF
C0805
C0805
Y30
Y22
VDDIO
VDDIO
VDDR7VDD
R9
V28
V26
V23
GND
GND
GND
GND
GNDF9GNDF7GNDF6GNDF5GND
F12
F10
C654
C654
0.22uF
0.22uF
*
*
C0603
C0603
10V, X7R, +/-10%
10V, X7R, +/-10%
+2.6V_SUS
C291
C291
4.7uF
4.7uF
*
*
C0805
C0805
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
W14
W12
W10
GND
GND
GNDW8GNDW6GNDW4GND
GND
GND
GND
GND
F22
F18
F16
F14
C655
C655
0.22uF
0.22uF
*
*
C0603
C0603
10V, X7R, +/-10%
10V, X7R, +/-10%
C510
C510
4.7uF
4.7uF
*
*
C0805
C0805
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
W16
GND
GND
GND
GND
GND
GND
GND
GND
F28
F26
F24
C471
C471
0.22uF
0.22uF
C0603
C0603
GND
GND
GND
GND
GND
GND
GND
GND
GNDY9GNDY7GND
GND
GND
GND
GND
GND
GNDH9GNDH7GND
GND
GNDG8GNDG6GNDG4GND
H21
H19
H17
H15
H13
H11
G14
G10
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Athlon 64- 4 Power
Athlon 64- 4 Power
Athlon 64- 4 Power
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
FOXCONN PCEG
C51GK8MB
C51GK8MB
C51GK8MB
ACustom
ACustom
ACustom
10 38Monday, June 20, 2005
10 38Monday, June 20, 2005
10 38Monday, June 20, 2005
of
of
of
Y28
Y26
Y23
Y21
Y19
Y17
Y15
Y13
Y11
W24
W22
W20
W18
5
4
3
2
1
5
MEM_A_BA[1..0]
MEM_A_BA[1..0]7,12,38,39
MEM_A1_CKE
MEM_A1_CKE7,38,39
MEM_A1_CS1#
MEM_A1_CS1#7,38,39
MEM_A1_CS0#
MEM_A1_CS0#7,38,39
MEM_A_CAS#
MEM_A_CAS#7,12,38,39
MEM_A_RAS#
MEM_A_RAS#7,12,38,39
D D
MEM_A_ADD[13..0]7,12,38,39
MEM_A_WE#
MEM_A_WE#7,12,38,39
MEM_ECC[7..0]
MEM_ECC[7..0]7,12,39
MEM_DQS[8..0]
MEM_DQS[8..0]7,12,39
MEM_DM#[8..0]
MEM_DM#[8..0]7,12,39
MEM_A_ADD[13..0]
4
DIMM 1
CLOSEST DIMM TO CPU
3
SMB_MEM BUS ADDRESS
DIMM 0
1010 000
DIMM 1
1010 001 1010 010
DIMM 2
1010 011
DIMM 3
SMB_MEM_SDA SMB_MEM_SCL
SMB_MEM_SDA 12,19 SMB_MEM_SCL 12,19
2
1
+2.6V_SUS
MEM_A_ADD0
MEM_A_ADD2
MEM_A_ADD3
MEM_A_ADD1
MEM_A_ADD4
MEM_A_ADD5
MEM_A_ADD7
MEM_A_ADD10
MEM_A_ADD9
MEM_A_ADD8
MEM_A_ADD6
MEM_DM#2
MEM_A_ADD12
MEM_DM#0
MEM_A_ADD13
MEM_A_ADD11
MEM_DM#1
MEM_DM#4
MEM_DM#5
MEM_DM#7
MEM_DM#6
MEM_DM#3
MEM_DM#8
MEM_DQS2
MEM_DQS0
MEM_DQS3
MEM_DQS1
MEM_DQS6
MEM_DQS4
MEM_ECC0
MEM_DQS7
MEM_DQS5
MEM_DQS8
MEM_ECC2
MEM_ECC3
MEM_ECC4
MEM_ECC1
MEM_ECC5
MEM_ECC7
14
272829
37
414243
130
A1
A1
A2
A2
A0
A0
+2.6V_SUS
C417
C417
0.1uF
C C
*
*
50V, Y5V, +80%/-20%
50V, Y5V, +80%/-20%
MEM_DATA[63..0]7,12,39
0.1uF
C0603
C0603
MEM_DATA[63..0]
2.5V
2.5V
<PART_NAME>
<PART_NAME>
DQ2
DQ2
DQ1
DQ0
DQ1
DQ0
DIMM1
DIMM1
2345678
MEM_DATA0
MEM_DATA1
MEM_DATA2
A4A3A6A7A8
A4A3A6A7A8
A5
A5
DQ3
DQ4
DQ3
DQ4
94
MEM_DATA4
MEM_DATA3
97
115
118
122
125
141
167
A11
A12A9A13
DM0
A11
A12A9A13
DM0
A10
A10
DQ6
DQ6
DQ5
DQ9
DQ12
DQ5
DQ9
DQ12
DQ11
DQ10
DQ7
DQ8
DQ11
DQ10
DQ7
DQ8
DQ14
DQ13
DQ14
DQ13
12
13
19
20
95
98
99
105
106
109
MEM_DATA5
MEM_DATA6
MEM_DATA7
MEM_DATA8
MEM_DATA10
MEM_DATA11
MEM_DATA12
MEM_DATA13
MEM_DATA9
MEM_DATA14
25
119
DM2
DM2
DQ16
DQ16
23
MEM_DATA16
129
149
159
DM3
DM4
DM3
DM4
DQ17
DQ18
DQ17
DQ18
24
3132333435
MEM_DATA17
MEM_DATA18
MEM_DATA19
36
140
169
177
DM5
DM6
DM7
DM5
DM6
DM7
DQS3
DQS2
DQS1
DQS0
DQS3
DQS2
DQS1
DQS0
NC/DM8
NC/DM8
DQ21
DQ21
DQ24
DQ23
DQ22
DQ26
DQ24
DQ23
DQ22
DQ26
DQ27
DQ25
DQ20
DQ19
DQ27
DQ25
DQ20
DQ19
39
40
114
117
121
123
126
MEM_DATA20
MEM_DATA21
MEM_DATA22
MEM_DATA23
MEM_DATA24
MEM_DATA25
MEM_DATA26
MEM_DATA27
MEM_DATA28
107
DM1
DM1
DQ15
DQ15
110
MEM_DATA15
MEM_ECC6
44
45464748495051
67
78
86
DQS4
DQS4
DQS7
DQS5
DQS7
DQS5
DQS6
DQS6
NC/DQS8
NC/DQS8
DQ30
DQ30
DQ32
DQ32
DQ28
DQ29
DQ31
DQ28
DQ29
DQ31
5354555657
127
131
133
MEM_DATA29
MEM_DATA30
MEM_DATA31
MEM_DATA32
MEM_DATA33
636465
134
135
142
144
WE*
WE*
NC/CB7
NC/CB6
NC/CB4
NC/CB5
NC/CB3
NC/CB2
NC/CB1
NC/CB0
NC/CB7
NC/CB6
NC/CB4
NC/CB5
NC/CB3
NC/CB2
NC/CB1
NC/CB0
DQ44
DQ43
DQ42
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ44
DQ43
DQ42
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ33
DQ35
DQ34
DQ33
DQ35
DQ34
60
61
68
69
146
147
150
151
153
MEM_DATA34
MEM_DATA35
MEM_DATA36
MEM_DATA37
MEM_DATA38
MEM_DATA39
MEM_DATA40
MEM_DATA41
MEM_DATA42
MEM_DATA43
MEM_DATA44
MEM_A_BA0
MEM_A_BA1
21
71
154155
157
158
163
CAS*
RAS*
CAS*
RAS*
S<3>*
S<2>*
S<3>*
S<2>*
S<1>*
S<0>*
S<1>*
S<0>*
CKE<0>
CKE<0>
DQ52
DQ51
DQ53
DQ52
DQ51
DQ53
DQ46
DQ45
DQ48
DQ49
DQ50
DQ47
DQ46
DQ45
DQ48
DQ49
DQ50
DQ47
72
73
79
80
161
162
165
166
MEM_DATA45
MEM_DATA46
MEM_DATA47
MEM_DATA48
MEM_DATA49
MEM_DATA50
MEM_DATA51
MEM_DATA52
MEM_DATA53
MEM_DATA54
10
52
59
111
113
181
BA<2>
BA<1>
BA<2>
BA<1>
BA<0>
BA<0>
SA<0>
SA<0>
CKE<1>
CKE<1>
DQ57
DQ56
DQ55
DQ54
DQ58
DQ60
DQ59
DQ57
DQ56
DQ55
DQ54
DQ58
DQ60
DQ59
83
84
87
88
170
171
174
MEM_DATA55
MEM_DATA56
MEM_DATA57
MEM_DATA58
MEM_DATA59
MEM_DATA60
82
909192
103
182
183
184
NC
NC
NC
NC
SCL
SDA
SCL
SDA
VDDID
FETEN
SA<2>
VDDID
FETEN
SA<2>
SA<1>
SA<1>
VDDSPD
VDDSPD
DQ62
DQ63
DQ61
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQ62
DQ63
DQ61
VSS
VSS
VSS
VSS
VSS
VSS
VSS
11
18
26
175
178
179
MEM_DATA61
MEM_DATA62
MEM_DATA63
15
22
30
38
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
58
66
74
81
62
70
VDD
VDD
VSS
VSS
89
77
85
VDD
VDD
VSS
VSS
93
96
108
VDD
VDD
VSS
VSS
100
104
120
VDD
VDD
VSS
VSS
116
112
128
136137
148
168
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
124
132
139
143
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
CK0*
CK0
NC
VSS
VSS
VSS
VSSNCNC
NC
CK0*
CK0
NC
VSS
VSS
VSS
VSSNCNC
NC
9
101
102
138
145
152
160
173
176
DDR_VREF1
1
156
164
172
180
*
*
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREF
VDDQ
VREF
DDR184
DDR184
CK1
CK1*
CK2
CK2*
CK1
CK1*
CK2
CK2*
16
17
75
76
MEM_A1_CLK2# MEM_A1_CLK2 MEM_A1_CLK1# MEM_A1_CLK1 MEM_A1_CLK0# MEM_A1_CLK0
C423
C423
0.1uF
0.1uF
50V, Y5V, +80%/-20%
50V, Y5V, +80%/-20%
C0603
C0603
DDR_VREF1 12
+2.6V_SUS
R380
R380 15
15
R0603
R0603
+/-1%
+/-1%
R375
R375 15
15
R0603
R0603
+/-1%
+/-1%
MEM_A1_CLK2# 7,38 MEM_A1_CLK2 7,38 MEM_A1_CLK1# 7,38 MEM_A1_CLK1 7,38 MEM_A1_CLK0# 7,38 MEM_A1_CLK0 7,38
DIMM 2
MEM_B_BA[1..0]
MEM_B_BA[1..0]8,12,38,39
MEM_B1_CKE
MEM_B1_CKE8,38,39
MEM_B1_CS1#
MEM_B1_CS1#8,38,39
MEM_B1_CS0#
MEM_B1_CS0#8,38,39
MEM_B_CAS#
MEM_B_CAS#8,12,38,39
MEM_B_RAS#
MEM_B_RAS#8,12,38,39
MEM_B_WE#
MEM_DATA[127..64]8,12,39
5
MEM_B_WE#8,12,38,39
MEM_ECC[15..8]8,12,39 MEM_DQS[17..9]8,12,39 MEM_DM#[17..9]8,12,39
MEM_B_ADD[13..0]8,12,38,39
+2.6V_SUS
C466
C466
0.1uF
0.1uF
*
*
C0603
C0603
50V, Y5V, +80%/-20%
50V, Y5V, +80%/-20%
C297
C297
0.1uF
0.1uF
*
*
C0603
C0603
50V, Y5V, +80%/-20%
50V, Y5V, +80%/-20%
MEM_DATA[127..64]
MEM_ECC[15..8] MEM_DQS[17..9] MEM_DM#[17..9] MEM_B_ADD[13..0]
MEM_B_ADD0
MEM_B_ADD1
MEM_B_ADD2
MEM_B_ADD3
MEM_B_ADD4
MEM_B_ADD5
MEM_B_ADD6
MEM_B_ADD7
MEM_B_ADD8
MEM_B_ADD9
MEM_B_ADD10
MEM_B_ADD11
MEM_B_ADD12
MEM_B_ADD13
MEM_DM#9
MEM_DM#10
MEM_DM#11
MEM_DM#12
MEM_DM#13
MEM_DM#14
MEM_DM#15
MEM_DM#16
MEM_DM#17
MEM_DQS9
MEM_DQS10
MEM_DQS11
MEM_DQS12
MEM_DQS13
MEM_DQS14
MEM_DQS15
MEM_DQS16
MEM_DQS17
MEM_ECC8
MEM_ECC9
MEM_ECC10
MEM_ECC11
MEM_ECC12
MEM_ECC13
MEM_ECC15
14
272829
37
414243
130
A1
A1
A2
A2
A0
A0
2.5V
2.5V
<PART_NAME>
<PART_NAME>
DQ2
DQ2
DQ1
DQ0
DQ1
DQ0
DIMM2
DIMM2
2345678
MEM_DATA64
MEM_DATA65
MEM_DATA66
MEM_DATA67
125
A4A3A6A7A8
A4A3A6A7A8
A5
A5
DQ3
DQ4
DQ3
DQ4
94
95
MEM_DATA68
MEM_DATA69
97
115
118
122
141
167
A11
A12A9A13
DM0
A11
A12A9A13
DM0
A10
A10
DQ5
DQ6
DQ5
DQ6
DQ11
DQ10
DQ7
DQ8
DQ11
DQ10
DQ7
DQ8
DQ9
DQ12
DQ14
DQ13
DQ9
DQ12
DQ14
DQ13
12
13
19
20
98
99
105
106
109
MEM_DATA70
MEM_DATA71
MEM_DATA72
MEM_DATA74
MEM_DATA75
MEM_DATA76
MEM_DATA77
MEM_DATA73
MEM_DATA78
25
119
DM2
DM2
DQ16
DQ16
23
MEM_DATA80
4
129
149
DM3
DM4
DM3
DM4
DQ17
DQ18
DQ17
DQ18
24
MEM_DATA81
MEM_DATA82
140
159
169
177
DM5
DM6
DM7
DM5
DM6
DM7
NC/DM8
NC/DM8
DQ22
DQ21
DQ22
DQ21
DQ20
DQ19
DQ20
DQ19
3132333435
114
117
121
MEM_DATA84
MEM_DATA85
MEM_DATA86
MEM_DATA83
36
DQS3
DQS2
DQS1
DQS0
DQS3
DQS2
DQS1
DQS0
DQ24
DQ23
DQ24
DQ23
DQ26
DQ27
DQ25
DQ26
DQ27
DQ25
39
40
123
126
MEM_DATA87
MEM_DATA88
MEM_DATA89
MEM_DATA90
MEM_DATA91
MEM_DATA92
107
DM1
DM1
DQ15
DQ15
110
MEM_DATA79
MEM_ECC14
44
45464748495051
67
78
86
DQS7
DQS4
DQS7
DQS4
DQS5
DQS6
DQS5
DQS6
NC/DQS8
NC/DQS8
DQ30
DQ30
DQ32
DQ28
DQ29
DQ31
DQ32
DQ28
DQ29
DQ31
5354555657
127
131
133
MEM_DATA93
MEM_DATA94
MEM_DATA95
MEM_DATA96
636465
134
135
142
144
154155
WE*
WE*
CAS*
RAS*
CAS*
RAS*
NC/CB7
NC/CB6
NC/CB4
NC/CB5
NC/CB3
NC/CB2
NC/CB1
NC/CB0
NC/CB7
NC/CB6
NC/CB4
NC/CB5
NC/CB3
NC/CB2
NC/CB1
NC/CB0
DQ46
DQ45
DQ44
DQ43
DQ42
DQ46
DQ45
DQ44
DQ43
DQ42
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ33
DQ35
DQ34
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ33
DQ35
DQ34
60
61
68
69
146
147
150
151
153
161
MEM_DATA97
MEM_DATA98
MEM_DATA99
MEM_DATA100
MEM_DATA101
MEM_DATA109
MEM_DATA110
MEM_DATA102
MEM_DATA103
MEM_DATA104
MEM_DATA105
MEM_DATA106
MEM_DATA107
MEM_DATA108
B B
A A
+2.6V_SUS
MEM_B_BA0
MEM_B_BA1
21
71
157
158
163
S<3>*
S<2>*
S<3>*
S<2>*
S<1>*
S<0>*
S<1>*
S<0>*
CKE<0>
CKE<0>
DQ48
DQ49
DQ50
DQ52
DQ51
DQ53
DQ48
DQ49
DQ50
DQ52
DQ51
DQ53
DQ47
DQ47
72
73
79
80
162
165
166
MEM_DATA111
MEM_DATA112
MEM_DATA113
MEM_DATA114
MEM_DATA115
MEM_DATA116
MEM_DATA117
10
52
59
909192
111
CKE<1>
CKE<1>
DQ54
DQ54
170
MEM_DATA118
103
113
181
182
183
NC
NC
NC
NC
BA<2>
BA<1>
BA<2>
BA<1>
FETEN
SA<2>
SA<1>
SA<0>
FETEN
SA<2>
SA<1>
SA<0>
BA<0>
BA<0>
DQ57
DQ56
DQ55
DQ58
DQ62
DQ63
DQ60
DQ59
DQ61
VSS
DQ57
DQ56
DQ55
DQ58
DQ62
DQ63
DQ60
DQ59
DQ61
VSS
83
84
87
88
171
174
175
178
179
MEM_DATA119
MEM_DATA120
MEM_DATA121
MEM_DATA122
MEM_DATA123
MEM_DATA124
MEM_DATA125
MEM_DATA126
MEM_DATA127
3
SMB_MEM BUS ADDRESS
DIMM 0 DIMM 1 DIMM 2 DIMM 3
SMB_MEM_SDA SMB_MEM_SCL
1010 000 1010 001 1010 010 1010 011
SMB_MEM_SDA 12,19 SMB_MEM_SCL 12,19
+2.6V_SUS
DDR_VREF1
DDR_VREF1 12
C502
C502
0.1uF
0.1uF
*
*
50V, Y5V, +80%/-20%
50V, Y5V, +80%/-20%
15
22
30
38
82
184
VDD
VDD
VDD
VDD
VDD
VDD
SCL
SDA
SCL
SDA
VDDID
VDDID
VDDSPD
VDDSPD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
11
18
26
58
66
74
81
62
70
VDD
VDD
VSS
VSS
89
77
85
108
120
148
168
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSNCNC
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSNCNC
9
93
100
116
124
132
139
145
152
160
176
1
96
104
112
128
136137
143
156
164
172
180
C0603
C0603
VDDQ
VREF
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREF
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DDR184
DDR184
CK0*
CK1
CK1*
CK2
CK2*
CK0
NC
CK0*
CK1
CK1*
CK2
CK2*
CK0
NC
16
17
75
76
101
102
138
173
2
MEM_B1_CLK2# MEM_B1_CLK2 MEM_B1_CLK1# MEM_B1_CLK1 MEM_B1_CLK0# MEM_B1_CLK0
MEM_B1_CLK2# 8,38 MEM_B1_CLK2 8,38 MEM_B1_CLK1# 8,38 MEM_B1_CLK1 8,38 MEM_B1_CLK0# 8,38 MEM_B1_CLK0 8,38
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
FOXCONN PCEG
DDR SDRAM DIMM 1 - 2
DDR SDRAM DIMM 1 - 2
DDR SDRAM DIMM 1 - 2
C51GK8MB
C51GK8MB
C51GK8MB
1
11 38Thursday, August 11, 2005
11 38Thursday, August 11, 2005
11 38Thursday, August 11, 2005
of
of
of
ACustom
ACustom
ACustom
5
4
3
2
1
MEM_A_BA[1..0]
MEM_A_BA[1..0]7,11,38,39
D D
MEM_A_ADD[13..0]7,11,38,39
C C
MEM_DATA[63..0]7,11,39
B B
A A
MEM_DATA[127..64]8,11,39
5
MEM_A2_CKE
MEM_A2_CKE7,38,39
MEM_A2_CS1#
MEM_A2_CS1#7,38,39
MEM_A2_CS0#
MEM_A2_CS0#7,38,39
MEM_A_CAS#
MEM_A_CAS#7,11,38,39
MEM_A_RAS#
MEM_A_RAS#7,11,38,39
MEM_A_WE#
MEM_A_WE#7,11,38,39
MEM_ECC[7..0]
MEM_ECC[7..0]7,11,39
MEM_DQS[8..0]
MEM_DQS[8..0]7,11,39
MEM_DM#[8..0]
MEM_DM#[8..0]7,11,39
MEM_A_ADD[13..0]
MEM_A_ADD12
MEM_A_ADD13
MEM_A_ADD4
MEM_A_ADD5
37
A4A3A6A7A8
A5
A4A3A6A7A8
A5
DQ3
DQ4
DQ3
DQ4
94
MEM_DATA3
MEM_DATA4
MEM_B_ADD1
MEM_B_ADD2
414243
A1
A1
A2
A2
2.5V
2.5V
DQ1
DQ0
DQ1
DQ0
2345678
MEM_DATA64
MEM_DATA65
MEM_A_ADD6
125
95
MEM_DATA5
MEM_B_ADD3
130
MEM_DATA66
MEM_A_ADD7
DQ5
DQ5
98
MEM_DATA6
MEM_B_ADD4
37
DQ2
DQ2
MEM_DATA67
MEM_A_ADD8
MEM_A_ADD9
272829
122
DQ7
DQ7
DQ6
DQ6
12
99
MEM_DATA7
MEM_DATA8
MEM_B_ADD5
MEM_B_ADD6
125
A5
A5
A4A3A6A7A8
A4A3A6A7A8
DQ3
DQ4
DQ3
DQ4
94
95
MEM_DATA68
MEM_DATA69
MEM_DM#0
MEM_A_ADD10
MEM_A_ADD11
97
115
118
141
167
A11
A12A9A13
DM0
A10
A11
A12A9A13
DM0
A10
DQ14
DQ13
DQ14
DQ13
DQ11
DQ10
DQ8
DQ11
DQ10
DQ8
DQ9
DQ12
DQ9
DQ12
13
19
20
105
106
109
MEM_DATA9
MEM_DATA10
MEM_DATA11
MEM_DATA12
MEM_DATA13
MEM_DATA14
MEM_B_ADD7
MEM_B_ADD8
MEM_B_ADD9
MEM_B_ADD10
MEM_B_ADD11
MEM_B_ADD12
272829
115
118
122
141
A10
A10
A11
A12A9A13
A11
A12A9A13
DQ5
DQ9
DQ5
DQ9
DQ11
DQ10
DQ7
DQ8
DQ11
DQ10
DQ7
DQ8
DQ6
DQ6
12
13
19
20
98
99
MEM_DATA70
MEM_DATA71
MEM_DATA72
MEM_DATA74
MEM_DATA75
MEM_DATA73
MEM_A_ADD0
MEM_A_ADD1
MEM_A_ADD3
MEM_A_ADD2
414243
130
A1
A0
A1
A0
A2
A2
2.5V
2.5V
<PART_NAME>
<PART_NAME>
DQ1
DQ0
DQ1
DQ0
DQ2
DQ2
DIMM3
DIMM3
2345678
MEM_DATA0
MEM_DATA1
MEM_B_BA[1..0]
MEM_B2_CKE
MEM_B2_CS1# MEM_B2_CS0# MEM_B_CAS# MEM_B_RAS# MEM_B_WE#
MEM_ECC[15..8] MEM_DQS[17..9]
MEM_B_ADD[13..0]
MEM_DATA2
MEM_DATA[63..0]
MEM_B_BA[1..0]8,11,38,39
MEM_B2_CKE8,38,39
MEM_B2_CS1#8,38,39 MEM_B2_CS0#8,38,39 MEM_B_CAS#8,11,38,39 MEM_B_RAS#8,11,38,39 MEM_B_WE#8,11,38,39
MEM_ECC[15..8]8,11,39 MEM_DQS[17..9]8,11,39
MEM_DM#[17..9]
MEM_DM#[17..9]8,11,39
MEM_B_ADD[13..0]8,11,38,39
MEM_B_ADD0
A0
A0
+2.6V_SUS
*
*
50V, Y5V, +80%/-20%
50V, Y5V, +80%/-20%
<PART_NAME>
<PART_NAME>
C295
C295
0.1uF
0.1uF
DIMM4
DIMM4
C0603
C0603
MEM_DATA[127..64]
MEM_DQS2
MEM_DQS3
MEM_DQS4
MEM_DQS5
MEM_DQS6
MEM_DQS7
MEM_DQS8
MEM_ECC0
MEM_ECC1
MEM_ECC2
MEM_ECC3
MEM_ECC4
MEM_ECC6
MEM_ECC5
MEM_DM#1
MEM_DM#2
MEM_DM#3
MEM_DM#4
MEM_DM#5
MEM_DM#6
MEM_DM#7
MEM_DM#8
14
25
36
149
159
169
DM4
DM5
DM6
DM4
DM5
DM6
DQ20
DQ19
DQ18
DQ20
DQ19
DQ18
3132333435
114
MEM_DATA20
MEM_DATA18
MEM_DATA19
MEM_DM#10
MEM_DM#11
MEM_DM#12
107
119
129
DM1
DM2
DM1
DM2
DM3
DM3
DQ17
DQ17
DQ16
DQ16
DQ15
DQ15
23
24
110
MEM_DATA79
MEM_DATA80
MEM_DATA81
4
140
177
DM7
DM7
NC/DM8
NC/DM8
DQ23
DQ22
DQ23
DQ22
DQ21
DQ21
117
121
123
MEM_DATA21
MEM_DATA22
MEM_DATA23
MEM_DM#13
MEM_DM#14
MEM_DM#15
149
159
169
DM4
DM5
DM6
DM4
DM5
DM6
DQ18
DQ18
DQ20
DQ19
DQ20
DQ19
3132333435
114
MEM_DATA84
MEM_DATA82
MEM_DATA83
67
DQS3
DQS2
DQS1
DQS0
DQS3
DQS2
DQS1
DQS0
DQS4
DQS5
DQS4
DQS5
DQ24
DQ27
DQ25
DQ28
DQ29
DQ24
DQ27
DQ25
DQ28
DQ29
DQ26
DQ26
39
40
126
127
MEM_DATA24 MEM_DQS0
MEM_DATA25 MEM_DQS1
MEM_DATA26
MEM_DATA27
MEM_DATA28
MEM_DATA29
MEM_DM#16
MEM_DM#17
MEM_DQS9
MEM_DQS10
MEM_DQS11
14
25
140
177
DM7
DM7
DQS2
DQS1
DQS0
DQS2
DQS1
DQS0
NC/DM8
NC/DM8
DQ25
DQ25
DQ24
DQ23
DQ22
DQ26
DQ24
DQ23
DQ22
DQ26
DQ21
DQ21
39
117
121
123
MEM_DATA85
MEM_DATA86
MEM_DATA87
MEM_DATA88
MEM_DATA89
MEM_DATA90
107
119
129
DM1
DM2
DM1
DM2
DM3
DM3
DQ16
DQ17
DQ16
DQ17
DQ15
DQ15
23
24
110
MEM_DATA15
MEM_DATA16
MEM_DATA17
MEM_B_ADD13
MEM_DM#9
97
167
DM0
DM0
DQ14
DQ13
DQ14
DQ13
DQ12
DQ12
105
106
109
MEM_DATA76
MEM_DATA77
MEM_DATA78
44
45464748495051
78
86
134
135
142
DQS7
DQS6
DQS7
DQS6
NC/CB6
NC/CB4
NC/CB5
NC/CB3
NC/CB2
NC/CB1
NC/CB0
NC/CB6
NC/CB4
NC/CB5
NC/CB3
NC/CB2
NC/CB1
NC/CB0
NC/DQS8
NC/DQS8
DQ30
DQ33
DQ35
DQ34
DQ32
DQ31
DQ30
DQ33
DQ35
DQ34
DQ32
DQ31
DQ36
DQ37
DQ38
DQ39
DQ40
DQ36
DQ37
DQ38
DQ39
DQ40
5354555657
60
61
131
133
146
147
150
151
MEM_DATA30
MEM_DATA31
MEM_DATA32
MEM_DATA33
MEM_DATA34
MEM_DATA35
MEM_DATA36
MEM_DATA37
MEM_DATA38
MEM_DATA39
MEM_DATA40
DIMM 4
MEM_DQS12
MEM_DQS13
MEM_DQS14
MEM_DQS15
MEM_DQS16
MEM_DQS17
MEM_ECC8
MEM_ECC9
MEM_ECC10
MEM_ECC11
36
44
45464748495051
67
78
86
DQS6
DQS6
DQS3
DQS7
DQS5
DQS3
DQS7
DQS5
DQS4
DQS4
NC/CB3
NC/CB2
NC/CB1
NC/CB0
NC/CB3
NC/CB2
NC/CB1
NC/CB0
NC/DQS8
NC/DQS8
DQ28
DQ29
DQ31
DQ28
DQ29
DQ31
DQ33
DQ35
DQ34
DQ32
DQ27
DQ33
DQ35
DQ34
DQ32
DQ27
DQ30
DQ36
DQ37
DQ30
DQ36
DQ37
40
5354555657
60
126
127
131
133
146
147
MEM_DATA91
MEM_DATA92
MEM_DATA93
MEM_DATA94
MEM_DATA95
MEM_DATA96
MEM_DATA97
MEM_DATA98
MEM_DATA99
MEM_DATA100
MEM_DATA101
MEM_ECC7
144
NC/CB7
NC/CB7
DQ42
DQ42
DQ41
DQ41
68
69
MEM_DATA41
MEM_DATA42
MEM_DATA43
MEM_ECC12
MEM_ECC13
MEM_ECC14
134
135
142
NC/CB4
NC/CB5
NC/CB4
NC/CB5
DQ38
DQ39
DQ38
DQ39
61
150
151
MEM_DATA102
MEM_DATA103
MEM_DATA104
636465
154155
157
WE*
WE*
CAS*
RAS*
CAS*
RAS*
DQ46
DQ45
DQ44
DQ43
DQ46
DQ45
DQ44
DQ43
DQ47
DQ47
72
153
161
162
MEM_DATA45
MEM_DATA46
MEM_DATA47
MEM_DATA48
MEM_DATA44
FURTHEST DIMM TO CPU
MEM_ECC15
636465
144
154155
WE*
WE*
NC/CB7
NC/CB6
NC/CB7
NC/CB6
DQ44
DQ43
DQ42
DQ40
DQ41
DQ44
DQ43
DQ42
DQ40
DQ41
68
69
153
MEM_DATA109
MEM_DATA105
MEM_DATA106
MEM_DATA107
MEM_DATA108
S<0>*
S<0>*
DQ48
DQ48
RAS*
RAS*
DQ45
DQ45
+2.6V_SUS
MEM_A_BA1
MEM_A_BA0
21
71
158
163
S<3>*
S<2>*
S<3>*
S<2>*
S<1>*
S<1>*
CKE<0>
CKE<0>
DQ49
DQ50
DQ49
DQ50
DQ52
DQ51
DQ53
DQ52
DQ51
DQ53
73
79
80
165
166
MEM_DATA49
MEM_DATA50
MEM_DATA51
MEM_DATA52
MEM_DATA53
MEM_DATA54
10
52
59
909192
111
113
181
182
183
NC
NC
NC
NC
BA<2>
BA<1>
SA<1>
SA<0>
BA<2>
BA<1>
SA<1>
SA<0>
SA<2>
BA<0>
SA<2>
BA<0>
CKE<1>
CKE<1>
DQ57
DQ56
DQ55
DQ54
DQ58
DQ62
DQ63
DQ60
DQ59
DQ61
DQ57
DQ56
DQ55
DQ54
DQ58
DQ62
DQ63
DQ60
DQ59
DQ61
83
84
87
88
170
171
174
175
178
179
MEM_DATA55
MEM_DATA56
MEM_DATA57
MEM_DATA58
MEM_DATA59
MEM_DATA60
MEM_DATA61
MEM_DATA62
MEM_DATA63
+2.6V_SUS
MEM_B_BA0
MEM_B_BA1
SMB_MEM BUS ADDRESS
DIMM 0
1010 000 1010 001
DIMM 1
1010 010
DIMM 2
1010 011
DIMM 3
SMB_MEM_SDA SMB_MEM_SCL
SMB_MEM_SDA 11,19 SMB_MEM_SCL 11,19
+2.6V_SUS
DDR_VREF1
DDR_VREF1
15
22
30
38
82
103
184
VDD
VDD
VDD
VDD
SCL
SDA
VDD
VDD
SCL
SDA
VDDID
VDDID
FETEN
FETEN
VDDSPD
VDDSPD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
11
18
26
58
66
74
81
SMB_MEM BUS ADDRESS
70
85
108
120
148
168
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSNCNC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSNCNC
VSS
VSS
VSS
VSS
89
93
100
116
124
132
139
145
152
160
176
DIMM 0 DIMM 1 DIMM 2 DIMM 3 1010 011
SMB_MEM_SDA SMB_MEM_SCL
62
77
96
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
9
101
1010 000 1010 001 1010 010
1
104
112
128
136137
143
156
164
172
180
*
*
VDDQ
VREF
VDDQ
VDDQ
VREF
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DDR184
DDR184
CK0*
CK1
CK1*
CK2
CK2*
CK0
NC
CK0*
CK1
CK1*
CK2
CK2*
CK0
NC
16
17
75
76
102
138
173
MEM_A2_CLK2# MEM_A2_CLK2 MEM_A2_CLK1# MEM_A2_CLK1 MEM_A2_CLK0# MEM_A2_CLK0
SMB_MEM_SDA 11,19 SMB_MEM_SCL 11,19
C467
C467
0.1uF
0.1uF
50V, Y5V, +80%/-20%
50V, Y5V, +80%/-20%
C0603
C0603
DDR_VREF1 11
MEM_A2_CLK2# 7,38 MEM_A2_CLK2 7,38 MEM_A2_CLK1# 7,38 MEM_A2_CLK1 7,38 MEM_A2_CLK0# 7,38 MEM_A2_CLK0 7,38
+2.6V_SUS
DDR_VREF1
21
71
157
158
163
CAS*
CAS*
S<1>*
S<0>*
S<1>*
S<0>*
S<3>*
S<2>*
S<3>*
S<2>*
CKE<0>
CKE<0>
DQ46
DQ48
DQ49
DQ50
DQ47
DQ46
DQ48
DQ49
DQ50
DQ47
DQ52
DQ51
DQ53
DQ52
DQ51
DQ53
72
73
79
80
161
162
165
166
MEM_DATA110
MEM_DATA111
MEM_DATA112
MEM_DATA113
MEM_DATA114
MEM_DATA115
MEM_DATA116
MEM_DATA117
10
52
59
111
113
181
SA<0>
SA<0>
BA<0>
BA<0>
BA<2>
BA<1>
BA<2>
BA<1>
CKE<1>
CKE<1>
DQ57
DQ56
DQ55
DQ54
DQ58
DQ60
DQ59
DQ57
DQ56
DQ55
DQ54
DQ58
DQ60
DQ59
83
84
87
88
170
171
174
MEM_DATA118
MEM_DATA119
MEM_DATA120
MEM_DATA121
MEM_DATA122
MEM_DATA123
MEM_DATA124
3
82
909192
103
182
183
184
NC
NC
NC
NC
SCL
SDA
SCL
SDA
SA<1>
SA<1>
VDDID
FETEN
SA<2>
VDDID
FETEN
SA<2>
VDDSPD
VDDSPD
DQ62
DQ63
DQ61
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQ62
DQ63
DQ61
VSS
VSS
VSS
VSS
VSS
VSS
VSS
11
18
26
175
178
179
MEM_DATA125
MEM_DATA126
MEM_DATA127
15
22
30
38
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
58
66
74
81
62
70
VDD
VDD
VSS
VSS
89
77
85
108
120
148
168
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VSS
VSS
VSS
VSS
VSS
VSSNCNC
NC
VSS
VSS
VSS
VSS
VSS
VSSNCNC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
9
93
100
116
124
132
139
145
152
160
176
1
96
104
112
128
136137
143
156
164
172
180
VDDQ
VREF
VDDQ
VDDQ
VREF
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DDR184
DDR184
CK0*
CK1
CK1*
CK2
CK2*
CK0
NC
CK0*
CK1
CK1*
CK2
CK2*
CK0
NC
16
17
75
76
101
102
138
173
2
MEM_B2_CLK2# MEM_B2_CLK2 MEM_B2_CLK1# MEM_B2_CLK1 MEM_B2_CLK0# MEM_B2_CLK0
DDR_VREF1 11
MEM_B2_CLK2# 8,38 MEM_B2_CLK2 8,38 MEM_B2_CLK1# 8,38 MEM_B2_CLK1 8,38 MEM_B2_CLK0# 8,38 MEM_B2_CLK0 8,38
VTT_DDR_SUS
*
*
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
for EMI
C415
C415
0.1uF
0.1uF
*
*
50V, Y5V, +80%/-20%
50V, Y5V, +80%/-20%
C0603
C0603
FOXCONN PCEG
FOXCONN PCEG
FOXCONN PCEG
DDR SDRAM DIMM 3 - 4
DDR SDRAM DIMM 3 - 4
DDR SDRAM DIMM 3 - 4
C51GK8MB
C51GK8MB
C51GK8MB
1
C437
C437
0.1uF
0.1uF
50V, Y5V, +80%/-20%
50V, Y5V, +80%/-20%
C0603
C0603
12 38Tuesday, July 19, 2005
12 38Tuesday, July 19, 2005
12 38Tuesday, July 19, 2005
of
of
of
DIMM 3
ACustom
ACustom
ACustom
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