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Foxconn
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A76GMV
Schematics
41 pgs5.63 Mb0
User Manual
56 pgs1.83 Mb0
User Manual
56 pgs1.75 Mb0

Foxconn A76GMV Schematics

E-CT
5
Foxconn Confidential Document,please keep it secret. M1
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Foxconn Tsingtao
D D
Fab :1.0
AMD RS740&SB700 Chipset for AMD AM3 CPU
TABLE OF CONTENTS
P01: COVER P02: BLOCK DIAGRAM
C C
P03: POWER DELIVERY CHART P04: CLOCK DISTRIBUTION P05: CPU HT & DEBUG P06: CPU MEMORY P07: CPU CONTROL & MISC P08: CPU PWR & GND P09: DDR2 DIMM A CHANNEL P10: DDR2 DIMM B CHANNEL P11: DDR2 DIMM POWER P12: DDR2 DIMM TERMINATIONS P13: RS740/RX780/RS780 HT LINK I/F P14: RS740/RX780/RS780 PCIE I/F P15: RS740/RX780/RS780 SYSTEM I/F P16: RS740/RX780/RS780 SPMEM/STRAPS P17: RS740/RX780/RS780 POWER
B B
P18: EXTERNAL CLOCK GENERATOR P41: NB/SB +1.1V/+1.2V POWER P19: SB700 PCIE/PCI/CPU/LPC/CLK P20: SB700 ACPI/GPIO/USB/AUDIO P21: SB700 SATA/IDE/HWM/SPI P22: SB700 PWR & DECOUPLING P23: SB700 STRAPS
P24: CRT & TVOUT P25: DVI & HDMI P26: PCIE x16 & x4 CONNECTORS P27: PCIE x1 & PCI SLOT 2 P28: PCI SLOT 0 & 1 P29: USB 2.0 PORTS 2,3,6,7,10,11 P30: USB 2.0 PORTS 1,4,5,8,9; USB 1.1 PORT 12 P31: PCIE GIGABIT ETHERNET P32: SIO-SCH5524 P33: FLASH I/F & CIR & HDR P34: LPC BIOS, TPM & FPD P35: SERIAL PORT, KBD & MOUSE P36: DESKTOP ATHLON64 PWR1 P37: DESKTOP ATHLON64 PWR2 P38: DDRII MEMORY POWER P39: NB CORE PWR P40: +1.8V & +1.5V POWER
P42: ATX CONN & PWR P43: RESET, FAN, SPKR, ENABLES P44: DEBUG-POST LEDS P45:AUDIO AD1984
UnRegistered
A A
FOXCONN PCEG
FOXCONN PCEG
FOXCONN PCEG
TABLE OF CONTENTS
TABLE OF CONTENTS
TABLE OF CONTENTS
RS780M09
RS780M09
RS780M09
1 41Monday, November 07, 2011
1 41Monday, November 07, 2011
1 41Monday, November 07, 2011
1
5
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
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RS740/RX780/RS780 + SB700
33
31
UNBUFFERED DDRII DIMM3
UNBUFFERED DDRII DIMM4
2121
9,11,12
10,11,1210,11,12
eSATA x1
21
D D
AMD AM3
Clock Generator ICS9LPR472
DVI CON
VGA CON
C C
USB-7
29
USB-8
B B
USB-9
30
USB-5
USB-11USB-10
18
27
24
292930
PCI BUS
29 2929 30 30
USB-2USB-6 USB-3USB-4
SPI ROM
21
2CH TMDS
USB 2.0
SPI I/F
HyperTransport Link
AM3 SOCKET
OUT
IN
5,6,7,8
16x16
RS740/RX780/RS780
HyperTransport LINK0 CPU I/F DX10 IGP( RS780) LVDS/TVOUT/TMDS(RS780/740) DISPLAY PORT X2 (RS780) Side Port Memory(RS780/740) 1 X16 PCIE I/F 1 X4 PCIE I/F WITH SB 6 X1 PCIE I/F (4 X1 for RS740)
13,14,15,16,17
4X PCIE
SB700
USB2.0 (12)+ 1.1(2) SATA II (6 PORTS) AZALIA HD AUDIO ATA 66/100/133 SPI I/F LPC I/F(S5) ACPI 1.1 INT RTC HW MONITOR PCI/PCI BDGE
19, 20, 21, 22, 23
DDRII 400,533,667,800
128bit
DDRII 400,533,667,800
Side port
I2C I/F
16X
PCIE GPP[3:0] X4
26
HD AUDIO I/F
SATA II I/F
HW MONITOR I/F
FRAME BUFFER
DDR3 512MBIT
BOOTSTRAPS ROM(NB)
PCIE SLOT
6 1X PCIE INTERFACE
PCIE GPP4 X1
27
UNBUFFERED DDRII DIMM1
UNBUFFERED DDRII DIMM2
DDRII FIRST LOGICAL DIMM DDRII SECOND LOGICAL DIMM
16
16
16X
26
PCIE GPP5 GIGABIT BCM5761/5755
HD AUDIO HDR
SATA#0
HW MONITOR
33
21 21
21
SATA#1
9,11,12
USB-0
31
(5761)
HD AUDIO REAR CON
SATA#2 SATA#3
PCI SLOT #1
DESKTOP AM2/AM2g2 POWER
A A
DDR2 MEMORY POWER
5
36,37
+1.1V, +1.2V
38
POWER
PCI SLOT
28
41
28
#2
UnRegistered
SMSC 5524
KBD MOUSE COM
4
FLOPPY
35 34
3
32
LPC I/F
TPM 1.2
LPC BIOS
34
34
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
FOXCONN PCEG
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
RS780M09
RS780M09
RS780M09
2 41Monday, November 07, 2011
2 41Monday, November 07, 2011
2 41Monday, November 07, 2011
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ATX P/S WITH 1A STBY CURRENT
5V
5VSB +/-5%
D D
C C
+/-5%
3.3V +/-5%
12V +/-5%
-12V +/-5%
CPU PW 12V +/-5%
VCC 1.1V SW REGULATOR
+3.3VSB REGULATOR ACPI CONTROLLER
+5VDUAL_MEM (S0,S5)
+3.3VSB (S0, S1, S3, S4, S5)
+3.3VDUAL (S0, S1, S3, S4, S5)
+5VDUAL (S0, S1, S3, S4, S5)
2.5V SHUNT REGULATOR
VRM SW REGULATOR
1.8V VDD SW REGULATOR
0.9V VTT_DDR REGULATOR
+1.1V RX780/RS780; +1.2V RS740 (S0, S1)
1.2V LINEAR REGULATOR
+1.8V(S0, S1)
+1.2VSB (S5)
1.8V LINEAR REGULATOR
1.2V STB LDO REGULATOR
VDD_CPUCORE_RUN (S0, S1)/VDD_CPUNB_RUN (S0, S1)
DDRII DIMMs
VTT_DDR 2A
VDD MEM 12A
1.5V LINEAR REGULATOR
+1.5V(S0, S1)
+1.2V(S0, S1)
CPU_VDDA_RUN(S0, S1)
CPU_VTT_SUS (S0,S1,S3)
CPU_VDDIO_SUS(S0,S1,S3)
AM2
VDDA 2.5V 0.2A
VDDCORE
0.8-1.55V 110A
DDRII MEM I/F VTT 2A, VDD 10A
VLDT 1.2V 0.5A
RS780
VDDHT/RX 1.1V 1.2A VDDHTTX 1.2V 0.5A VDDPCIE 1.1V 2A NB CORE VDDC
1.1V 7A
VDDA18PCIE 1.8V 0.9A PLLs 1.8V 0.1A VDD18/VDD18_MEM
1.8V 0.01A VDD_MEM 1.8V/1.5V 0.5A
AVDD 3.3V 0.135A
SB700
X4 PCI-E 0.8A ATA I/O 0.5A ATA PLL 0.01A PCI-E PVDD 80mA SB CORE 0.6A CLOCK
1.2V S5 PW 0.22A
3.3V S5 PW 0.01A USB CORE I/O 0.2A
3.3V I/O 0.45A
AZALIA CODEC CON
B B
3.3V CORE 0.3A 5V ANALOG 0.1A 12V 0.1A
UnRegistered
PCI Slot (per slot)
5V
A A
+3.3VDUAL (S0, S1, S3)
5
3.3V 12V
3.3Vaux
-12V
5.0A
7.6A
0.5A
0.375A
0.1A
3.3Vaux 0.1A
4
0.5A
X16 PCIEX1 PCIE per
3.3V 12V12V
3.0A3.0A
5.5A
USB X6 RL
VDD 5VDual
3.0A
3
USB X2 FL 2XPS/2
VDD 3.3V 5VDual
1.0A
5VDual
1.0A
GBE
3.3V 0.5A (S0, S1)
3.3V 0.1A (S3)
2
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
FOXCONN PCEG
POWER DELIVERY CHART
POWER DELIVERY CHART
POWER DELIVERY CHART
RS780M09
RS780M09
RS780M09
3 41Monday, November 07, 2011
3 41Monday, November 07, 2011
3 41Monday, November 07, 2011
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DIMM3 DIMM4
1 PAIR CPU CLK
DIMM1 DIMM2
200MHZ HT ref clock 100MHZ DIFF(RX780/RS780)
HT REFCLK 66MHz SE(RS740)
14.318MHZ OSC
3 PAIR MEM CLK
3 PAIR MEM CLK
C C
AM2/AM2g2 CPU
AM2 SOCKET
B B
3 PAIR MEM CLK
3 PAIR MEM CLK
1 PAIR CPU CLK
200MHZ
EXTERNAL CLK GEN.
(RS740/RX780)
HT REFCLK
66MHz SE(RS740) 100MHz DIFF(RX780/RS780)
NB-OSCIN
14.318MHZ
NB ALINK PCIE CLK
100MHZ
SB ALINK PCIE CLK
100MHZ
NB GFX PCIE CLK
100MHZ
NB GPP PCIE CLK
100MHZ
(RX780)
PCIE GFX CLK
100MHZ
PCIE GPP CLK
100MHZ
PCIE GPP CLK
100MHZ
PCIE GPP CLK
100MHZ
USB CLK
48MHZ
SIO CLK
48MHZ
AMD NB RS740/RX780/RS780
NB PCIE Ref clock 100MHZ
PCIE GFX SLOT 1 - 16 LANES
PCIE GPP SLOT 1 - 1 LANE
PCIE GPP SLOT 2 - 4 LANES
PCIE GBE
25MHZ OSC INPUT
NB Disp clock
100MHZ DIFF(RS780)
GPP Ref clock 100MHZ
GFX Ref clock 100MHZ
GPP Ref clock
100MHZ GPP Ref clock
100MHZ
GPP Ref clock
100MHZ
25MHz
SATA
UnRegistered
CPU_HT_CLK
NB_HT_CLK
25M_48M_66M_OSC
AMD SB SB700
NB_DISP_CLK
GPP_CLK3
PCIE_RCLK/ NB_LNK_CLK
SLT_GFX_CLK
GPP_CLK0
GPP_CLK1
GPP_CLK2
USB_CLK
SB_BITCLK
48MHZ
PCI CLK0
33MHZ
PCI CLK1
33MHZ
PCI CLK2
33MHZ
LPC_CLK0
LPC CLK1
PCI CLK3
PCI CLK4
25MHz
32.768KHz
33MHZ
33MHZ
33MHZ
33MHZ
PCI SLOT 0
PCI SLOT 1
PCI SLOT 2
TPM
LPC BIOS
DEBUG POST
SUPER IO IT8716F
HD AUDIO CON
TPM (BCM5755/5761)
A A
External clock mode
Internal clock mode
5
14.31818MHz
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
FOXCONN PCEG
CLOCK DISTRIBUTION
CLOCK DISTRIBUTION
CLOCK DISTRIBUTION
RS780M09
RS780M09
RS780M09
4 41Monday, November 07, 2011
4 41Monday, November 07, 2011
4 41Monday, November 07, 2011
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HyperTransport
CPU HyperTransport and Debug
HT_CLKIN1_P13 HT_CLKOUT1_P 13 HT_CLKIN1_N13
A1
D D
AM3 Top View
AL1
U1IU1I
5
MTG1
6
MTG1
7
MTG1
8
MTG1
9
MTG1
10
MTG1
11
MTG1
12
MTG1
1
EMI
2
C C
CPUHS1
CPUHS1
HEATSINK_SOCKET_940_M2
HEATSINK_SOCKET_940_M2
Dummy
Dummy
B B
EMI
13
MTG2
14
MTG2
15
MTG2
16
MTG2
17
MTG2
18
MTG2
19
MTG2
20
MTG2
A31
AL31
21
MTG3
22
MTG3
23
MTG3
24
MTG3
25
MTG3
26
MTG3
27
MTG3
28
MTG3
3
EMI
4
EMI
29
MTG4
30
MTG4
31
MTG4
32
MTG4
33
MTG4
34
MTG4
35
MTG4
36
MTG4
1D2V_HT
R621 51.1Ohm+/-1% @RS740
R621 51.1Ohm+/-1% @RS740 R601 51.1Ohm+/-1% @RS740
R601 51.1Ohm+/-1% @RS740
*
* *
*
HT_CTLIN1_P HT_CTLIN1_N
CPU_DBREQ#7
CPU_DBRDY7
CPU_TCK7,33 CPU_TMS7,33 CPU_TDI7,33
CPU_TRST#7
CPU_TDO7
HT_CLKIN0_P13 HT_CLKIN0_N13
HT_CTLIN1_P13 HT_CTLIN1_N13 HT_CTLIN0_P13 HT_CTLIN0_N13
HT_CADIN15_P13 HT_CADIN15_N13 HT_CADIN14_P13 HT_CADIN14_N13 HT_CADIN13_P13 HT_CADIN13_N13 HT_CADIN12_P13 HT_CADIN12_N13 HT_CADIN11_P13 HT_CADIN11_N13 HT_CADIN10_P13 HT_CADIN10_N13 HT_CADIN9_P13 HT_CADIN9_N13 HT_CADIN8_P13 HT_CADIN8_N13
HT_CADIN7_P13 HT_CADIN7_N13 HT_CADIN6_P13 HT_CADIN6_N13 HT_CADIN5_P13 HT_CADIN5_N13 HT_CADIN4_P13 HT_CADIN4_N13 HT_CADIN3_P13 HT_CADIN3_N13 HT_CADIN2_P13 HT_CADIN2_N13 HT_CADIN1_P13 HT_CADIN1_N13 HT_CADIN0_P13 HT_CADIN0_N13
1D5V_STR
R611
R611
*
*
300
300
+/-5%
+/-5%
U1A
U1A
N6
L0_CLKIN_H1
P6
L0_CLKIN_L1
N3
L0_CLKIN_H0
N2
L0_CLKIN_L0
V4
L0_CTLIN_H1
V5
L0_CTLIN_L1
U1
L0_CTLIN_H0
V1
L0_CTLIN_L0
U6
L0_CADIN_H15
V6
L0_CADIN_L15
T4
L0_CADIN_H14
T5
L0_CADIN_L14
R6
L0_CADIN_H13
T6
L0_CADIN_L13
P4
L0_CADIN_H12
P5
L0_CADIN_L12
M4
L0_CADIN_H11
M5
L0_CADIN_L11
L6
L0_CADIN_H10
M6
L0_CADIN_L10
K4
L0_CADIN_H9
K5
L0_CADIN_L9
J6
L0_CADIN_H8
K6
L0_CADIN_L8
U3
L0_CADIN_H7
U2
L0_CADIN_L7
R1
L0_CADIN_H6
T1
L0_CADIN_L6
R3
L0_CADIN_H5
R2
L0_CADIN_L5
N1
L0_CADIN_H4
P1
L0_CADIN_L4
L1
L0_CADIN_H3
M1
L0_CADIN_L3
L3
L0_CADIN_H2
L2
L0_CADIN_L2
J1
L0_CADIN_H1
K1
L0_CADIN_L1
J3
L0_CADIN_H0
J2
L0_CADIN_L0
PZ94121-3126-01F
PZ94121-3126-01F
HDT Connector
HDT
HDT
2
C11C2
4
C33C4
6
C55C6
8
C77C8
10
C99C10
12
C1111C12
14
C1313C14
16
C1515C16
18
C1717C18
20
C1919C20
22
C2121C22
24
C2323C24
26
C26
X
X
Header_2X13_K25
Header_2X13_K25
Use buffered reset
Dummy
Dummy
L0_CLKOUT_H1 L0_CLKOUT_L1 L0_CLKOUT_H0 L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CADOUT_H15 L0_CADOUT_L15 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H10 L0_CADOUT_L10
L0_CADOUT_H9 L0_CADOUT_L9 L0_CADOUT_H8 L0_CADOUT_L8
L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H4
HT LINK
HT LINK
L0_CADOUT_L4 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H0 L0_CADOUT_L0
3D3V_SYS
R345
R345
*
*
4.7K
4.7K
+/-5%
+/-5%
MMBT3904-7-F
MMBT3904-7-F
Dummy
Dummy
R346 0
R346 0
AD5 AD4 AD1 AC1
Y6 W6 W2 W3
Y5 Y4 AB6 AA6 AB5 AB4 AD6 AC6 AF6 AE6 AF5 AF4 AH6 AG6 AH5 AH4
Y1 W1 AA2 AA3 AB1 AA1 AC2 AC3 AE2 AE3 AF1 AE1 AG2 AG3 AH1 AG1
1D8V_NB
*
*
B
E C
*
*
R342
R342 10K
10K
+/-5%
+/-5%
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Q46
Q46
+/-5%
+/-5%
HT_CLKOUT1_N 13 HT_CLKOUT0_P 13 HT_CLKOUT0_N 13
HT_CTLOUT1_P 13 HT_CTLOUT1_N 13 HT_CTLOUT0_P 13 HT_CTLOUT0_N 13
HT_CADOUT15_P 13 HT_CADOUT15_N 13 HT_CADOUT14_P 13 HT_CADOUT14_N 13 HT_CADOUT13_P 13 HT_CADOUT13_N 13 HT_CADOUT12_P 13 HT_CADOUT12_N 13 HT_CADOUT11_P 13 HT_CADOUT11_N 13 HT_CADOUT10_P 13 HT_CADOUT10_N 13 HT_CADOUT9_P 13 HT_CADOUT9_N 13 HT_CADOUT8_P 13 HT_CADOUT8_N 13
HT_CADOUT7_P 13 HT_CADOUT7_N 13 HT_CADOUT6_P 13 HT_CADOUT6_N 13 HT_CADOUT5_P 13 HT_CADOUT5_N 13 HT_CADOUT4_P 13 HT_CADOUT4_N 13 HT_CADOUT3_P 13 HT_CADOUT3_N 13 HT_CADOUT2_P 13 HT_CADOUT2_N 13 HT_CADOUT1_P 13 HT_CADOUT1_N 13 HT_CADOUT0_P 13 HT_CADOUT0_N 13
LDT_RST# 7,19
HDT Header
UnRegistered
A A
FOXCONN PCEG
FOXCONN PCEG
FOXCONN PCEG
CPU HT & HDT HEADER
CPU HT & HDT HEADER
CPU HT & HDT HEADER
RS780M09
RS780M09
RS780M09
1
5
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
A
A
5 41Monday, November 07, 2011
5 41Monday, November 07, 2011
5 41Monday, November 07, 2011
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Foxconn Confidential Document,please keep it secret. M1
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C
D
E
DDR3 Memory Interface A DDR3 Memory Interface B
CPU Memory
U1B
U1B
AG21
MA_CLK_H7
AG20
MA_CLK_L7
AE20
MA_CLK_H6
AE19
MA_CLK_L6
U27
MA_CLK_H5
U26
AC25 AA24
AE28 AC28
AD27 AA25
AE27 AC27
AB25 AB27 AA26
AA27
AC26
AD15 AE15 AG18 AG19 AG24 AG25 AG27 AG28
AF15 AF19
AH29
V27 W27 W26 W25
U24
V24
G19
H19
G20
G21
E20
N25
Y27
L27
M25
M27
N24
N26
P25
Y25
N27
R24
P27
R25
R26
R27
T25
U25
T27 W24
D29
C29
C25
D25
E19
F19
F15
G15
AJ25
B29
E24
E18
H15
MA_CLK_L5 MA_CLK_H4 MA_CLK_L4 MA_CLK_H3 MA_CLK_L3 MA_CLK_H2 MA_CLK_L2 MA_CLK_H1 MA_CLK_L1 MA_CLK_H0 MA_CLK_L0
MA0_CS_L1 MA0_CS_L0
MA0_ODT1 MA0_ODT0
MA1_CS_L1 MA1_CS_L0
MA1_ODT1 MA1_ODT0
MA_RESET_L MA_CAS_L
MA_WE_L MA_RAS_L
MA_BANK2 MA_BANK1 MA_BANK0
MA_CKE1 MA_CKE0
MA_ADD15 MA_ADD14 MA_ADD13 MA_ADD12 MA_ADD11 MA_ADD10 MA_ADD9 MA_ADD8 MA_ADD7 MA_ADD6 MA_ADD5 MA_ADD4 MA_ADD3 MA_ADD2 MA_ADD1 MA_ADD0
MA_DQS_H7 MA_DQS_L7 MA_DQS_H6 MA_DQS_L6 MA_DQS_H5 MA_DQS_L5 MA_DQS_H4 MA_DQS_L4 MA_DQS_H3 MA_DQS_L3 MA_DQS_H2 MA_DQS_L2 MA_DQS_H1 MA_DQS_L1 MA_DQS_H0 MA_DQS_L0
MA_DM7 MA_DM6 MA_DM5 MA_DM4 MA_DM3 MA_DM2 MA_DM1 MA_DM0
MEM CHA
MEM CHA
PZ94121-3126-01F
PZ94121-3126-01F
4 4
3 3
2 2
MEM_MA0_CLK0_P9 MEM_MA0_CLK0_N9
MEM_MA0_CLK1_P9 MEM_MA0_CLK1_N9
MEM_MA0_CS_L19 MEM_MA0_CS_L09
MEM_MA0_ODT19 MEM_MA0_ODT09
MEM_MA_RESET#9
MEM_MA_CAS#9 MEM_MA_WE#9 MEM_MA_RAS#9
MEM_MA_BANK29 MEM_MA_BANK19 MEM_MA_BANK09
MEM_MA_CKE19 MEM_MA_CKE09
MEM_MA_ADD[15..0]9 MEM_MB_ADD[15..0]10
MEM_MA_DQS7_P9 MEM_MA_DQS7_N9 MEM_MA_DQS6_P9 MEM_MA_DQS6_N9 MEM_MA_DQS5_P9 MEM_MA_DQS5_N9 MEM_MA_DQS4_P9 MEM_MA_DQS4_N9 MEM_MA_DQS3_P9 MEM_MA_DQS3_N9 MEM_MA_DQS2_P9 MEM_MA_DQS2_N9 MEM_MA_DQS1_P9 MEM_MA_DQS1_N9 MEM_MA_DQS0_P9 MEM_MA_DQS0_N9
MEM_MA_DM[7..0]9 MEM_MB_DM[7..0]10
MEM_MA_ADD15 MEM_MA_ADD14 MEM_MA_ADD13 MEM_MA_ADD12 MEM_MA_ADD11 MEM_MA_ADD10 MEM_MA_ADD9 MEM_MA_ADD8 MEM_MA_ADD7 MEM_MA_ADD6 MEM_MA_ADD5 MEM_MA_ADD4 MEM_MA_ADD3 MEM_MA_ADD2 MEM_MA_ADD1 MEM_MA_ADD0
MEM_MA_DM7 MEM_MA_DM6 MEM_MA_DM5 MEM_MA_DM4 MEM_MA_DM3 MEM_MA_DM2 MEM_MA_DM1 MEM_MA_DM0
MA0 & MA_CKE0
CPU
1 1
TO DIMMA0
A0
MA_DATA63 MA_DATA62 MA_DATA61 MA_DATA60 MA_DATA59 MA_DATA58 MA_DATA57 MA_DATA56 MA_DATA55 MA_DATA54 MA_DATA53 MA_DATA52 MA_DATA51 MA_DATA50 MA_DATA49 MA_DATA48 MA_DATA47 MA_DATA46 MA_DATA45 MA_DATA44 MA_DATA43 MA_DATA42 MA_DATA41 MA_DATA40 MA_DATA39 MA_DATA38 MA_DATA37 MA_DATA36 MA_DATA35 MA_DATA34 MA_DATA33 MA_DATA32 MA_DATA31 MA_DATA30 MA_DATA29 MA_DATA28 MA_DATA27 MA_DATA26 MA_DATA25 MA_DATA24 MA_DATA23 MA_DATA22 MA_DATA21 MA_DATA20 MA_DATA19 MA_DATA18 MA_DATA17 MA_DATA16 MA_DATA15 MA_DATA14 MA_DATA13 MA_DATA12 MA_DATA11 MA_DATA10
MA_DATA9 MA_DATA8 MA_DATA7 MA_DATA6 MA_DATA5 MA_DATA4 MA_DATA3 MA_DATA2 MA_DATA1 MA_DATA0
MA_DQS_H8 MA_DQS_L8
MA_DM8
MA_CHECK7 MA_CHECK6 MA_CHECK5 MA_CHECK4 MA_CHECK3 MA_CHECK2 MA_CHECK1 MA_CHECK0
MA_EVENT_L
AE14
MEM_MA_DATA63
AG14
MEM_MA_DATA62
AG16
MEM_MA_DATA61
AD17
MEM_MA_DATA60
AD13
MEM_MA_DATA59
AE13
MEM_MA_DATA58
AG15
MEM_MA_DATA57
AE16
MEM_MA_DATA56
AG17
MEM_MA_DATA55
AE18
MEM_MA_DATA54
AD21
MEM_MA_DATA53
AG22
MEM_MA_DATA52
AE17
MEM_MA_DATA51
AF17
MEM_MA_DATA50
AF21
MEM_MA_DATA49
AE21
MEM_MA_DATA48
AF23
MEM_MA_DATA47
AE23
MEM_MA_DATA46
AJ26
MEM_MA_DATA45
AG26
MEM_MA_DATA44
AE22
MEM_MA_DATA43
AG23
MEM_MA_DATA42
AH25
MEM_MA_DATA41
AF25
MEM_MA_DATA40
AJ28
MEM_MA_DATA39
AJ29
MEM_MA_DATA38
AF29
MEM_MA_DATA37
AE26
MEM_MA_DATA36
AJ27
MEM_MA_DATA35
AH27
MEM_MA_DATA34
AG29
MEM_MA_DATA33
AF27
MEM_MA_DATA32
E29
MEM_MA_DATA31
E28
MEM_MA_DATA30
D27
MEM_MA_DATA29
C27
MEM_MA_DATA28
G26
MEM_MA_DATA27
F27
MEM_MA_DATA26
C28
MEM_MA_DATA25
E27
MEM_MA_DATA24
F25
MEM_MA_DATA23
E25
MEM_MA_DATA22
E23
MEM_MA_DATA21
D23
MEM_MA_DATA20
E26
MEM_MA_DATA19
C26
MEM_MA_DATA18
G23
MEM_MA_DATA17
F23
MEM_MA_DATA16
E22
MEM_MA_DATA15
E21
MEM_MA_DATA14
F17
MEM_MA_DATA13
G17
MEM_MA_DATA12
G22
MEM_MA_DATA11
F21
MEM_MA_DATA10
G18
MEM_MA_DATA9
E17
MEM_MA_DATA8
G16
MEM_MA_DATA7
E15
MEM_MA_DATA6
G13
MEM_MA_DATA5
H13
MEM_MA_DATA4
H17
MEM_MA_DATA3
E16
MEM_MA_DATA2
E14
MEM_MA_DATA1
G14
MEM_MA_DATA0
J28 J27
J25 K25
MEM_MA_CHECK7
J26
MEM_MA_CHECK6
G28
MEM_MA_CHECK5
G27
MEM_MA_CHECK4
L24
MEM_MA_CHECK3
K27
MEM_MA_CHECK2
H29
MEM_MA_CHECK1
H27
MEM_MA_CHECK0
W30
1D5V_STR 1D5V_STR
R672
R672
*
*
1K +/-5%
1K +/-5%
MEMORY CLOCK TRANSLATION
DIMM
DDR3 Memory Signal
DIMM A0
MEM_MA0_CLK1 MEM_MA0_CLK0 MA_CLK4
DIMM A1
MEM_MA1_CLK1 MA_CLK5 MEM_MA1_CLK0 MA_CLK3
DIMM B0
MEM_MB0_CLK1 MB_CLK2 MEM_MB0_CLK0 MB_CLK4
DIMM B1
MEM_MB1_CLK1 MB_CLK5 MEM_MB1_CLK0 MB_CLK3
MEM_MA_DATA[63..0] 9 MEM_MB_DATA[63..0] 10
MEM CHA
MEM_MB0_CLK0_P10 MEM_MB0_CLK0_N10
MEM_MB0_CLK1_P10
MEM_MB0_CLK1_N10
CPU
MEM_MB0_CS_L110 MEM_MB0_CS_L010
MEM_MB0_ODT110
TO DIMMA0 & DIMMA1
MEM_MB0_ODT010
A0
MEM_MB_RESET#10
MEM_MB_CAS#10
MEM_MB_WE#10
MEM_MB_RAS#10
MEM CHB
CPU
TO DIMMB0 & DIMMB1
B0
MEM_MA_DQS8_P 9 MEM_MA_DQS8_N 9
MEM_MA_DM8 9 MEM_MA_CHECK[7..0] 9
MEM_MA_EVENT_L 9 MEM_MB_EVENT_L 10
Layout: Route as 60 ohms with 5/10 W/S from CPU pins.
MEM_MB_BANK210 MEM_MB_BANK110 MEM_MB_BANK010
MEM_MB_CKE110 MEM_MB_CKE010
MEM_MB_ADD15 MEM_MB_ADD14 MEM_MB_ADD13 MEM_MB_ADD12 MEM_MB_ADD11 MEM_MB_ADD10 MEM_MB_ADD9 MEM_MB_ADD8 MEM_MB_ADD7 MEM_MB_ADD6 MEM_MB_ADD5 MEM_MB_ADD4 MEM_MB_ADD3 MEM_MB_ADD2 MEM_MB_ADD1
MEM_MB_DQS7_P10 MEM_MB_DQS7_N10 MEM_MB_DQS6_P10 MEM_MB_DQS6_N10 MEM_MB_DQS5_P10 MEM_MB_DQS5_N10 MEM_MB_DQS4_P10 MEM_MB_DQS4_N10 MEM_MB_DQS3_P10 MEM_MB_DQS3_N10 MEM_MB_DQS2_P10 MEM_MB_DQS2_N10 MEM_MB_DQS1_P10 MEM_MB_DQS1_N10 MEM_MB_DQS0_P10 MEM_MB_DQS0_N10
MEM_MB_ADD0
MEM_MB_DM7 MEM_MB_DM6 MEM_MB_DM5 MEM_MB_DM4 MEM_MB_DM3 MEM_MB_DM2 MEM_MB_DM1 MEM_MB_DM0
MB0 & MB_CKE0
CPU Signal
MA_CLK2
UnRegistered
CPU
TO DIMMB0
U1C
U1C
AG31
AL19 AL18
AC31 AF31
AD29 AE29
AB31
AD31
AC29 AC30 AB29
AA31 AA28
AE31
AA29
AA30 AK13 AK17 AK23
AL23 AL28 AL29
AH17 AK29
AJ19 AK19
U31
U30 W29 W28
Y31
Y30
V31 W31
A18
A19
C19
D19
AE30
B19
N31
M31
M29
N28
N29
N30
P29
P31
R29
R28
R31
R30
T31
T29
U29
U28
AJ13 AJ17
D31
C31
C24
C23
D17
C17
C14
C13 AJ14 AJ23
C30
A23
B17
B13
MB_CLK_H7 MB_CLK_L7 MB_CLK_H6 MB_CLK_L6 MB_CLK_H5 MB_CLK_L5 MB_CLK_H4 MB_CLK_L4 MB_CLK_H3 MB_CLK_L3 MB_CLK_H2 MB_CLK_L2 MB_CLK_H1 MB_CLK_L1 MB_CLK_H0 MB_CLK_L0
MB0_CS_L1 MB0_CS_L0
MB0_ODT1 MB0_ODT0
MB1_CS_L1 MB1_CS_L0
MB1_ODT1 MB1_ODT0
MB_RESET_L MB_CAS_L
MB_WE_L MB_RAS_L
MB_BANK2 MB_BANK1 MB_BANK0
MB_CKE1 MB_CKE0
MB_ADD15 MB_ADD14 MB_ADD13 MB_ADD12 MB_ADD11 MB_ADD10 MB_ADD9 MB_ADD8 MB_ADD7 MB_ADD6 MB_ADD5 MB_ADD4 MB_ADD3 MB_ADD2 MB_ADD1 MB_ADD0
MB_DQS_H7 MB_DQS_L7 MB_DQS_H6 MB_DQS_L6 MB_DQS_H5 MB_DQS_L5 MB_DQS_H4 MB_DQS_L4 MB_DQS_H3 MB_DQS_L3 MB_DQS_H2 MB_DQS_L2 MB_DQS_H1 MB_DQS_L1 MB_DQS_H0 MB_DQS_L0
MB_DM7 MB_DM6 MB_DM5 MB_DM4 MB_DM3 MB_DM2 MB_DM1 MB_DM0
PZ94121-3126-01F
PZ94121-3126-01F
MEM CHB
MEM CHB
MB_DATA63 MB_DATA62 MB_DATA61 MB_DATA60 MB_DATA59 MB_DATA58 MB_DATA57 MB_DATA56 MB_DATA55 MB_DATA54 MB_DATA53 MB_DATA52 MB_DATA51 MB_DATA50 MB_DATA49 MB_DATA48 MB_DATA47 MB_DATA46 MB_DATA45 MB_DATA44 MB_DATA43 MB_DATA42 MB_DATA41 MB_DATA40 MB_DATA39 MB_DATA38 MB_DATA37 MB_DATA36 MB_DATA35 MB_DATA34 MB_DATA33 MB_DATA32 MB_DATA31 MB_DATA30 MB_DATA29 MB_DATA28 MB_DATA27 MB_DATA26 MB_DATA25 MB_DATA24 MB_DATA23 MB_DATA22 MB_DATA21 MB_DATA20 MB_DATA19 MB_DATA18 MB_DATA17 MB_DATA16 MB_DATA15 MB_DATA14 MB_DATA13 MB_DATA12 MB_DATA11 MB_DATA10
MB_DATA9 MB_DATA8 MB_DATA7 MB_DATA6 MB_DATA5 MB_DATA4 MB_DATA3 MB_DATA2 MB_DATA1 MB_DATA0
MB_DQS_H8 MB_DQS_L8
MB_DM8
MB_CHECK7 MB_CHECK6 MB_CHECK5 MB_CHECK4 MB_CHECK3 MB_CHECK2 MB_CHECK1 MB_CHECK0
MB_EVENT_L
AH13 AL13 AL15 AJ15 AF13 AG13 AL14 AK15 AL16 AL17 AK21 AL21 AH15 AJ16 AH19 AL20 AJ22 AL22 AL24 AK25 AJ21 AH21 AH23 AJ24 AL27 AK27 AH31 AG30 AL25 AL26 AJ30 AJ31 E31 E30 B27 A27 F29 F31 A29 A28 A25 A24 C22 D21 A26 B25 B23 A22 B21 A20 C16 D15 C21 A21 A17 A16 B15 A14 E13 F13 C15 A15 A13 D13
J31 J30
J29 K29
K31 G30 G29 L29 L28 H31 G31
V29
MEM_MB_DATA63 MEM_MB_DATA62 MEM_MB_DATA61 MEM_MB_DATA60 MEM_MB_DATA59 MEM_MB_DATA58 MEM_MB_DATA57 MEM_MB_DATA56 MEM_MB_DATA55 MEM_MB_DATA54 MEM_MB_DATA53 MEM_MB_DATA52 MEM_MB_DATA51 MEM_MB_DATA50 MEM_MB_DATA49 MEM_MB_DATA48 MEM_MB_DATA47 MEM_MB_DATA46 MEM_MB_DATA45 MEM_MB_DATA44 MEM_MB_DATA43 MEM_MB_DATA42 MEM_MB_DATA41 MEM_MB_DATA40 MEM_MB_DATA39 MEM_MB_DATA38 MEM_MB_DATA37 MEM_MB_DATA36 MEM_MB_DATA35 MEM_MB_DATA34 MEM_MB_DATA33 MEM_MB_DATA32 MEM_MB_DATA31 MEM_MB_DATA30 MEM_MB_DATA29 MEM_MB_DATA28 MEM_MB_DATA27 MEM_MB_DATA26 MEM_MB_DATA25 MEM_MB_DATA24 MEM_MB_DATA23 MEM_MB_DATA22 MEM_MB_DATA21 MEM_MB_DATA20 MEM_MB_DATA19 MEM_MB_DATA18 MEM_MB_DATA17 MEM_MB_DATA16 MEM_MB_DATA15 MEM_MB_DATA14 MEM_MB_DATA13 MEM_MB_DATA12 MEM_MB_DATA11 MEM_MB_DATA10
MEM_MB_DATA9 MEM_MB_DATA8 MEM_MB_DATA7 MEM_MB_DATA6 MEM_MB_DATA5 MEM_MB_DATA4 MEM_MB_DATA3 MEM_MB_DATA2 MEM_MB_DATA1 MEM_MB_DATA0
MEM_MB_CHECK7 MEM_MB_CHECK6 MEM_MB_CHECK5 MEM_MB_CHECK4 MEM_MB_CHECK3 MEM_MB_CHECK2 MEM_MB_CHECK1 MEM_MB_CHECK0
R677
R677
1K +/-5%
1K +/-5%
*
*
MEM_MB_DQS8_P 10 MEM_MB_DQS8_N 10
MEM_MB_DM8 10
MEM_MB_CHECK[7..0] 10
EVENT pins are for future AM3r2EVENT pins are for future AM3r2
Layout: Route as 60 ohms with 5/10 W/S from CPU pins.
B0
A
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
B
C
D
Date: Sheet
FOXCONN PCEG
CPU MEMORY
CPU MEMORY
CPU MEMORY
RS780M09
RS780M09
RS780M09
6 41Monday, November 07, 2011
6 41Monday, November 07, 2011
6 41Monday, November 07, 2011
E
A
A
A
of
of
of
E-CT
5
Foxconn Confidential Document,please keep it secret. M1
4
3
2
1
2D5V_VDDA
Layout: Keep trace to resistors
CPU_PWRGD19
LDT_STOP#15,19 LDT_RST#5,19
D D
Note: Update with new clock termination scheme, if necessary.
C C
B B
CPU_CLKP18
CPU_CLKN18
+/-5%
+/-5%
+/-5%
+/-5%
*
*
*
*
Dummy
Dummy
Dummy
Dummy
R311 300
R311 300
R325 300
R325 300
CPU_TEST12 CPU_TEST21_SCANEN CPU_TEST27 CPU_TEST22
CPU_THERMTRIP# CPU_TEST20 CPU_TEST24 CPU_TEST26_BURNIN_L
change R334,R330,R321 to RN33 _F
C238 3.9nF
C238 3.9nF
C237 3.9nF
C237 3.9nF
CPU_TEST15_BP1 CPU_TEST14_BP0
1D5V_STR
+/-10%
+/-10%
*
*
+/-10%
+/-10%
*
*
1D5V_STR
135
*
*
135
*
*
642
642
RN35
RN35
300
300
+/-5%
+/-5%
7 8
1D5V_STR
RN34
RN34
300
300
+/-5%
+/-5%
7 8
R323
R323
*
*
169 Ohm
169 Ohm
+/-1%
+/-1%
CPU_DBREQ#5
CPU_VDD_RUN_FB_H37 CPU_VDD_RUN_FB_L37
less than 1" from CPU pins.
CPU_TDI5,33
CPU_TRST#5
CPU_TCK5,33 CPU_TMS5,33
Layout: Keep trace to resistors less than 1" from CPU pins.
135
*
*
642
RN33
RN33
300
300
+/-5%
+/-5%
7 8
R551
R551 0 +/-5%
0 +/-5%
Dummy
Dummy
*
*
CPU_M_VREF_SUS
TP9TP9 TP14TP14
CPU_ALERT#
*
*
R309
R309 1K
1K
+/-5%
+/-5%
1D5V_STR
R315
R315
*
*
1K
1K
+/-5%
+/-5%
SA0_AM3
*
*
Dummy
Dummy
Dummy
Dummy
R319
R319 1K
1K
+/-5%
+/-5%
R313
R313
*
*
1K
1K
+/-5%
+/-5%
MMBT3904-7-F
MMBT3904-7-F
*
*
LDT_RST#
*
*
*
*
1D5V_STR
R343
R343
R338
R338
*
*
39.2
39.2
511
511
+/-1%
+/-1%
+/-1%
+/-1%
CPU_CLKIN_SC_P CPU_CLKIN_SC_N
CPU_PWRGD LDT_STOP#
CPU_SIC CPU_SID
CPU_ALERT# CPU_TDI
CPU_TRST# CPU_TCK CPU_TMS
CPU_DBREQ# CPU_VDD_FB_H
CPU_VDD_FB_L
CPU_M_ZN CPU_M_ZP
CPU_TEST25_H_BYPASSCLK_H CPU_TEST25_H_BYPASSCLK_L CPU_TEST19_PLLTEST0 CPU_TEST18_PLLTEST1
CPU_TEST17_BP3 CPU_TEST16_BP2 CPU_TEST15_BP1 CPU_TEST14_BP0 CPU_TEST12
R341
R341
R344
R344
*
*
511
511
39.2
39.2
+/-1%
+/-1%
+/-1%
+/-1%
1D5V_STR
*
*
B
Dummy
Dummy
E C
Q72
Q72
C229
C229
10uF
10uF
CPU_VDDA_RUN
TP10TP10 TP8TP8 TP12TP12 TP7TP7
R358
R358 10K
10K
Dummy
Dummy
L46
L46
FB 30Ohm
FB 30Ohm
TP18TP18
TALERT# 21
CPU_VDDA_RUN
21
C244
C244
*
*
4.7uF
4.7uF
Pin naming for VID pins indicate "Serial VID"/"Parallel VID" connections.
U1D
U1D
C10
VDDA_1
D10
VDDA_2
A8
CLKIN_H
B8
CLKIN_L
C9
PWROK
D8
LDTSTOP_L
C7
RESET_L
AL3
CPU_PRESENT_L
AL6
SIC
AK6
SID
AK4
SA0
AL4
ALERT_L
AL10
TDI
AJ10
TRST_L
AH10
TCK
AL9
TMS
A5
DBREQ_L
G2
VDD_FB_H
G1
VDD_FB_L
F3
M_VDDIO_PWRGD
E12
VDDR_SENSE
F12
M_VREF
AH11
M_ZN
AJ11
M_ZP
A10
TEST25_H
B10
TEST25_L
F10
TEST19
E9
TEST18
AJ7
TEST13
F6
TEST9
D6
TEST17
E7
TEST16
F8
TEST15
C5
TEST14
AH9
TEST12
E5
TEST7
AJ5
TEST6
AH7
TEST3
AJ6
TEST2
C18
RSVD1
C20
RSVD2
F2
RSVD3
G24
RSVD4
G25
RSVD5
H25
RSVD6
L25
RSVD7
L26
RSVD8
PZ94121-3126-01F
PZ94121-3126-01F
*
50V, X7R, +/-10%
50V, X7R, +/-10%
0.22uF
0.22uF
MISC.
MISC.
INT. MISC.
INT. MISC.
CPU_THERMTRIP#
C250
C250
3.3nF
3.3nF
C247
C247
*
*
*
CPU Control and Miscellaneous
Layout: Keep CPU_HTREF0 less than 1.5" from in length.
1D5V_STR
1D2V_HT
1D5V_STR
R318
R318
*
*
300
300
+/-5%
+/-5%
Dummy
Dummy
1 2
#REFDE62 X_COPPER#REFDE62 X_COPPER
CPU_TDO 5
TP17TP17 TP19TP19
R339
R339
80.6
80.6
+/-1%
+/-1%
modify 20090603
R171
R171
*
*
300
300
+/-5%
+/-5%
VID5 37 VID4 37 VID3 37 VID2 37 VID1 37 VID0 37
CPU_THERMDC 34 CPU_THERMDA 34
CPU_PROCHOT#_1D8 19
CPU_DBRDY 5
NB_VDD_RUN_FB_H 37
NB_VDD_RUN_FB_L 37
Layout: Route as 80 ohms diff impedance. Keep trace to resistor < 1" from CPU pins.
CORE_TYPE
SVC/VID3 SVD/VID2
PVIEN/VID1
THERMDC THERMDA
THERMTRIP_L
PROCHOT_L
DBRDY
VDDIO_FB_H
VDDIO_FB_L VDDNB_FB_H VDDNB_FB_L
PSI_L
HTREF1 HTREF0
TEST29_H TEST29_L
TEST24 TEST23 TEST22 TEST21 TEST20
TEST28_H
TEST28_L
TEST27 TEST26 TEST10
TEST8
RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16
MMBT3904-7-F
MMBT3904-7-F
G5 D2
VID5
D1
VID4
C1 E3 E2 E1
VID0
AG9 AG8 AK7 AL7
AK10
TDO
B6 AK11
AL11 G4 G3
F1 V8
V7
C11 D11
AK8 AH8 AJ9 AL8 AJ8
J10 H9 AK9 AK5 G7 D4
L30 L31 AD25 AE24 AE25 AJ18 AJ20 AK3
1D5V_STR
E C
CPU_CORE_TYPE CPU_VID5
VREG_VID4 VREG_VID3 VREG_VID2 VREG_VID1 VREG_VID0
CPU_THERMDC CPU_THERMDA CPU_THERMTRIP# CPU_PROCHOT#
CPU_TDO
CPU_DBRDY
TP3TP3
CPU_HTREF1 CPU_HTREF0
CPU_TEST29_H_FBCLKOUT_H CPU_TEST29_L_FBCLKOUT_L
CPU_TEST24
TP11TP11
CPU_TEST22 CPU_TEST21_SCANEN CPU_TEST20
TP16TP16 TP15TP15
CPU_TEST27 CPU_TEST26_BURNIN_L CPU_TEST10_ANALOGOUT CPU_TEST8_DIG_T
*
*
3D3V_DUAL
R327
R327 10K
10K
*
*
R337
R337
Dummy
Dummy
B
4.7K
4.7K
Q45
Q45
NB_VDD_FB_H
NB_VDD_FB_L
R307
R307
*
*
44.2Ohm
44.2Ohm
+/-1%
+/-1%
CPU_CORE_TYPE 37
R304
R304
*
*
44.2Ohm
44.2Ohm
+/-1%
+/-1%
THERMTRIP# 20
Layout: Keep CPU_HTREF0 less than 1.5" from in length.
TP13TP13 TP6TP6
1D5V_STR
RN36
RN36
642
300
300
+/-5%
+/-5%
135
7 8
*
CPU_CORE_TYPE CPU_TEST18_PLLTEST1 CPU_TEST19_PLLTEST0
A A
*
5
change R310,R317,R324,R328 to RN34 change R331,R336,R340,R333 to RN35 change R308,R329,R332 to RN36
-F
4
UnRegistered
CPU_M_VREF_SUS
1D5V_STR
CPU_M_VREF_SUS
R348
R348
*
*
15
15
+/-1%
+/-1%
C255
C255
1nF
R347
R347
*
*
15
15
+/-1%
+/-1%
3
1nF
*
*
*
*
25V, NPO, +/-5%
25V, NPO, +/-5%
C262
C262
0.1uF
0.1uF
Layout: Place within 500 mils of the CPU socket.
2
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
FOXCONN PCEG
CPU CONTROL & MISC
CPU CONTROL & MISC
CPU CONTROL & MISC
RS780M09
RS780M09
RS780M09
1
A
A
7 41Monday, November 07, 2011
7 41Monday, November 07, 2011
7 41Monday, November 07, 2011
A
of
of
of
E-CT
5
Foxconn Confidential Document,please keep it secret. M1
4
3
2
1
VCCP_CPU VCCP_CPU
U1E
U1E
B3
VDD_1
C2
VDD_2
C4
VDD_3
D3
VDD_4
D5
VDD_5
E4
VDD_6
E6
VDD_7
F5
VDD_8
F7
VDD_9
G6
D D
C C
B B
G8
H7 H11 H23
J8 J12 J14 J16 J18 J20 J22 J24
K7
K9
K11 K13 K15 K17 K19 K21 K23
L4
L5
L8
L10 L12 L14 L16 L18 L20 L22
M2 M3 M7 M9
M11 M13 M15 M17 M19 M21 M23
N8
N10 N12 N14 N16 N18 N20 N22
P7
P9
P11 P13 P15 P17 P19 P21 P23
R4 R5 R8
R10 R12 R14 R16 R18 R20 R22
T2
T3
T7
T9
T11 T13
VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23 VDD_24 VDD_25 VDD_26 VDD_27 VDD_28 VDD_29 VDD_30 VDD_31 VDD_32 VDD_33 VDD_34 VDD_35 VDD_36 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43 VDD_44 VDD_45 VDD_46 VDD_47 VDD_48 VDD_49 VDD_50 VDD_51 VDD_52 VDD_53 VDD_54 VDD_55 VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62 VDD_63 VDD_64 VDD_65 VDD_66 VDD_67 VDD_68 VDD_69 VDD_70 VDD_71 VDD_72 VDD_73 VDD_74 VDD_75 VDD_76 VDD_77 VDD_78 VDD_79 VDD_80 VDD_81 VDD_82 VDD_83 VDD_84 VDD_85
PZ94121-3126-01F
PZ94121-3126-01F
A3
VSS_1
A7
VSS_2
A9
VSS_3
A11
VSS_4
B4
VSS_5
B9
VSS_6
B11
VSS_7
B14
VSS_8
B16
VSS_9
B18
VSS_10
B20
VSS_11
B22
VSS_12
B24
VSS_13
B26
VSS_14
B28
VSS_15
B30
VSS_16
C3
VSS_17
D14
VSS_18
D16
VSS_19
D18
VSS_20
D20
VSS_21
D22
VSS_22
D24
VSS_23
D26
VSS_24
D28
VSS_25
D30
VSS_26
E11
VSS_27
F4
VSS_28
F14
VSS_29
F16
VSS_30
F18
VSS_31
F20
VSS_32
F22
VSS_33
F24
VSS_34
F26
VSS_35
F28
VSS_36
F30
VSS_37
G9
VSS_38
G11
VSS_39
H8
VSS_40
H10
VSS_41
H12
VSS_42
H14
VSS_43
H16
VSS_44
H18
VSS_45
H24
VSS_46
H26
VSS_47
H28
VSS_48
H30
VSS_49
J4
VSS_50
J5
POWER/GND1
POWER/GND1
VSS_51
J7
VSS_52
J9
VSS_53
J11
VSS_54
J13
VSS_55
J15
VSS_56
J17
VSS_57
J19
VSS_58
J21
VSS_59
J23
VSS_60
K2
VSS_61
K3
VSS_62
K8
VSS_63
K10
VSS_64
K12
VSS_65
K14
VSS_66
K16
VSS_67
K18
VSS_68
K20
VSS_69
K22
VSS_70
K24
VSS_71
K26
VSS_72
K28
VSS_73
K30
VSS_74
L7
VSS_75
L9
VSS_76
L11
VSS_77
L13
VSS_78
L15
VSS_79
L17
VSS_80
L19
VSS_81
L21
VSS_82
L23
VSS_83
M8
VSS_84
M10
VSS_85
AA10 AA12 AA14 AA16 AA18 AA20 AA22
AB11 AB13 AB15 AB17 AB19 AB21 AB23
AC10 AC12 AC14 AC16 AC18 AC20 AC22
AD11 AD23 AE10 AE12
AF11
T15 T17 T19 T21 T23
U8 U10 U12 U14 U16 U18 U20 U22
V9 V11 V13 V15 V17 V19 V21 V23 W4 W5 W8
W10 W12 W14 W16 W18 W20 W22
Y2
Y3
Y7
Y9 Y11 Y13 Y15 Y17 Y19 Y21 Y23 AA8
AB7 AB9
AC4 AC5 AC8
AD2 AD3 AD7 AD9
AF7 AF9
AG4 AG5 AG7
AH2 AH3
U1F
U1F
VDD_86 VDD_87 VDD_88 VDD_89 VDD_90 VDD_91 VDD_92 VDD_93 VDD_94 VDD_95 VDD_96 VDD_97 VDD_98 VDD_99 VDD_100 VDD_101 VDD_102 VDD_103 VDD_104 VDD_105 VDD_106 VDD_107 VDD_108 VDD_109 VDD_110 VDD_111 VDD_112 VDD_113 VDD_114 VDD_115 VDD_116 VDD_117 VDD_118 VDD_119 VDD_120 VDD_121 VDD_122 VDD_123 VDD_124 VDD_125 VDD_126 VDD_127 VDD_128 VDD_129 VDD_130 VDD_131 VDD_132 VDD_133 VDD_134 VDD_135 VDD_136 VDD_137 VDD_138 VDD_139 VDD_140 VDD_141 VDD_142 VDD_143 VDD_144 VDD_145 VDD_146 VDD_147 VDD_148 VDD_149 VDD_150 VDD_151 VDD_152 VDD_153 VDD_154 VDD_155 VDD_156 VDD_157 VDD_158 VDD_159 VDD_160 VDD_161 VDD_162 VDD_163 VDD_164 VDD_165 VDD_166 VDD_167 VDD_168 VDD_169 VDD_170
PZ94121-3126-01F
PZ94121-3126-01F
M12
VSS_86
M14
VSS_87
M16
VSS_88
M18
VSS_89
M20
VSS_90
M22
VSS_91
N4
VSS_92
N5
VSS_93
N7
VSS_94
N9
VSS_95
N11
VSS_96
N13
VSS_97
N15
VSS_98
N17
VSS_99
N19
VSS_100
N21
VSS_101
N23
VSS_102
P2
VSS_103
P3
VSS_104
P8
VSS_105
P10
VSS_106
P12
VSS_107
P14
VSS_108
P16
VSS_109
P18
VSS_110
P20
VSS_111
P22
VSS_112
R7
VSS_113
R9
VSS_114
R11
VSS_115
R13
VSS_116
R15
VSS_117
R17
VSS_118
R19
VSS_119
R21
VSS_120
R23
VSS_121
T8
VSS_122
T10
VSS_123
T12
VSS_124
T14
VSS_125
T16
VSS_126
T18
VSS_127
T20
VSS_128
T22
VSS_129
U4
VSS_130
U5
VSS_131
U7
VSS_132
U9
VSS_133
U11
VSS_134
U13
POWER/GND2
POWER/GND2
VSS_135
U15
VSS_136
U17
VSS_137
U19
VSS_138
U21
VSS_139
U23
VSS_140
V2
VSS_141
V3
VSS_142
V10
VSS_143
V12
VSS_144
V14
VSS_145
V16
VSS_146
V18
VSS_147
V20
VSS_148
V22
VSS_149
W7
VSS_150
W9
VSS_151
W11
VSS_152
W13
VSS_153
W15
VSS_154
W17
VSS_155
W19
VSS_156
W21
VSS_157
W23
VSS_158
Y8
VSS_159
Y10
VSS_160
Y12
VSS_161
Y14
VSS_162
Y16
VSS_163
Y18
VSS_164
Y20
VSS_165
Y22
VSS_166
AA4
VSS_167
AA5
VSS_168
AA7
VSS_169
AA9
VSS_170
VCCP_NB
A4
VDDNB_1
A6
VDDNB_2
B5
VDDNB_3
B7
VDDNB_4
C6
VDDNB_5
C8
VDDNB_6
D7
VDDNB_7
D9
VDDNB_8
E8
VDDNB_9
E10
VDDNB_10
F9
VDDNB_11
F11
VDDNB_12
G10
VDDNB_13
G12
VDDNB_14
B2
NP/RSVD
H20
NP/VSS1
AE7
NP/VSS2
VCCP_NB
Bottom Side Decoupling
1D5V_STR
C675
C675
C672
C672
10nF
10nF
10nF
10nF
*
*
*
*
*
*
*
10uF
10uF
10uF
10uF
10uF
C670
C670
VCCP_CPU
C655
C655
22uF
22uF
*
*
VCCP_CPU
*
*
C630
A A
C630
VCCP_NB
*
*
C193
C193
10uF
C667
C667
C669
C669
Dummy
Dummy
C654
C654
C661
C661
22uF
22uF
22uF
22uF
*
*
*
*
Dummy
Dummy
*
*
*
*
10uF
10uF
10uF
10uF
10uF
10uF
C645
C645
C653
C653
C576
C576
10nF
10nF
*
*
*
*
Dummy
Dummy
22uF
22uF
22uF
22uF
C195
C195
Dummy
Dummy
5
*
*
*
10uF
10uF
C668
C668
Dummy
Dummy
25V, X7R, +/-10%
25V, X7R, +/-10%
Dummy
Dummy
25V, X7R, +/-10%
25V, X7R, +/-10%
C647
C647
C662
C662
C650
C650
22uF
22uF
22uF
22uF
22uF
22uF
*
*
*
*
*
*
*
*
10uF
10uF
C639
C639
VCCP_CPU
C571
C571
10nF
10nF
C666 2.2uF
*
*
C666 2.2uF
C671 2.2uF
C671 2.2uF
*
*
*
*
Dummy
Dummy
*
* *
*
C664
C664
22uF
22uF
*
*
C674
C674
Dummy
Dummy
*
*
Dummy
Dummy
*
*
C640
C640
1D5V_STR
+/-10%
+/-10%
+/-10%
+/-10%
0.22uF
0.22uF
C665
C665
22uF
22uF
4.7uF
4.7uF
*
*
C673
C673
50V, NPO, +/-5%
50V, NPO, +/-5%
C651
C651
22uF
22uF
*
*
Dummy
Dummy
*
*
C638
C638
EMC
0.22uF
0.22uF
4.7uF
4.7uF
Dummy
Dummy
*
*
C676
C676
*
*
Dummy
Dummy
*
*
C659
C659
180pF
180pF
C646
C646
22uF
22uF
C660
C660
10nF
10nF
*
*
10uF
10uF
25V, X7R, +/-10%
25V, X7R, +/-10%
25V, X7R, +/-10%
25V, X7R, +/-10%
C196
C196
C649
C649
C663
C663
10nF
10nF
*
*
Dummy
Dummy
50V, NPO, +/-5%
50V, NPO, +/-5%
2.2uF
2.2uF
*
*
UnRegistered
VCCP_CPU
1D2V_HT
*
*
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
C656
C656
0.22uF
0.22uF
0.22uF
0.22uF
Dummy
Dummy
*
*
C631
C631
180pF
180pF
VCCP_NBVCCP_CPU
4
Processor Power and Ground
CHANGE CPU SCOKET VCCP_NB TO VCCP_CPU
-F
U1G
U1G
PZ94121-3126-01F
PZ94121-3126-01F
POWER/GND3
POWER/GND3
VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214
AA11 AA13 AA15 AA17 AA19 AA21 AA23 AB2 AB3 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC7 AC9 AC11 AC13 AC15 AC17 AC19 AC21 AC23 AD8 AD10 AD12 AD14 AD16 AD20 AD22 AD24 AE4 AE5 AE11 AF2 AF3 AF8 AF10 AF12 AF14 AF16
VCCP_NB
C183
C183
C182
C182
10uF
10uF
10uF
*
*
Dummy
Dummy
10uF
+/-10%
+/-10%
*
*
+/-10%
+/-10%
C198
C198
*
*
C197
C197
Dummy
4.7uF
4.7uF
Dummy
10nF
10nF
C200
C200
C204
C204
0.22uF
0.22uF
0.22uF
0.22uF
A1
AL1
C258
C232
C232
4.7uF
4.7uF
C258
*
*
C233
C233
Dummy
4.7uF
4.7uF
0.22uF
0.22uF
Dummy
C234
C234
180pF
180pF
180pF
180pF
C249
C249
C254
C254
0.22uF
0.22uF
*
*
Dummy
Dummy
VLDT_HT3_RUN VTT_DDR
C614
C614
C615
0.1uF
0.1uF
C615
*
*
0.1uF
0.1uF
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
C616
C616
*
*
0.1uF
0.1uF
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
EMC place close NB
3
1D2V_HT
U1H
U1H
AJ1
VLDT_A_1
AJ2
VLDT_A_2
AJ3
VLDT_A_3
AJ4
VLDT_A_4
A12
VDDR_L VDDR_R
VDDR_1
B12
VDDR_2
C12
VDDR_3
D12
AB24 AB26 AB28 AB30 AC24 AD26 AD28 AD30 AF30
M24 M26 M28 M30 P24 P26 P28 P30 T24 T26 T28 T30 V25 V26 V28 V30 Y24 Y26 Y28 Y29
VDDR_4
VDDIO_1 VDDIO_2 VDDIO_3 VDDIO_4 VDDIO_5 VDDIO_6 VDDIO_7 VDDIO_8 VDDIO_9 VDDIO_10 VDDIO_11 VDDIO_12 VDDIO_13 VDDIO_14 VDDIO_15 VDDIO_16 VDDIO_17 VDDIO_18 VDDIO_19 VDDIO_20 VDDIO_21 VDDIO_22 VDDIO_23 VDDIO_24 VDDIO_25 VDDIO_26 VDDIO_27 VDDIO_28 VDDIO_29
PZ94121-3126-01F
PZ94121-3126-01F
1D5V_STR
VLDT_B_1 VLDT_B_2 VLDT_B_3 VLDT_B_4
VDDR_5 VDDR_6 VDDR_7 VDDR_8 VDDR_9
VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230
POWER/GND4
POWER/GND4
VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242
VDDR_R
VDDR_R
*
*
C493
C493
AM3
Top View
*
*
10uF
10uF
A31
C253
C253
4.7uF
4.7uF
*
*
C248
C248
4.7uF
4.7uF
C251
C251
C252
C252
0.22uF
0.22uF
1D5V_STR
1D5V_STR
*
*
Dummy
Dummy
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
1D5V_STR
*
*
Dummy
Dummy
C490
C490
C267
C267
0.22uF
0.22uF
0.22uF
0.22uF
C424
C424
C381
C381
2.2uF
2.2uF
2.2uF
2.2uF
*
*
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
C364
C364
C402
C402
2.2uF
2.2uF
2.2uF
2.2uF
*
*
Dummy
Dummy
0.22uF
0.22uF
180pF
180pF
C425
C425
180pF
180pF
C427
C427
AL31
Layout: Place across each VDDIO-GND plane split.
VDDR_L
*
*
*
*
C259
C259
4.7uF
4.7uF
C260
C260
4.7uF
4.7uF
C435
C435
C445
C445
10uF
10uF
0.22uF
0.22uF
C268
C268
*
*
*
*
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
10nF
10nF
c0805h14
c0805h14
4.7uF
4.7uF
C658
Dummy
Dummy
C658
H1 H2 H5 H6
AG12 AH12 AJ12 AK12 AL12
AF18 AF20 AF22 AF24 AF26 AF28 AG10 AG11 AH14 AH16 AH18 AH20 AH22 AH24 AH26 AH28 AH30 AK2 AK14 AK16 AK18 AK20 AK22 AK24 AK26 AK28 AK30 AL5
2
VLDT_HT3_RUN_B
DIMMs
CP18
CP18
12
X_COPPER
X_COPPER
CP19
CP19
12
X_COPPER
X_COPPER
1D2V_HT
*
*
C225
C225
4.7uF
4.7uF
Layout: Place as close as possible to CPU socket.
CPU
VTT_DDR
VTT_DDR
Dummy
Dummy
*
*
*
*
*
*
C488
C488
100pF
100pF
Layout: Place behind the DIMMs, evenly spaced on VTT fill.
DUMMY C491,C259,C488,C487,C253,C490
-F
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
C489
C489
4.7uF
4.7uF
Dummy
Dummy
C480
C480
4.7uF
4.7uF
*
*
Dummy
Dummy
C487
C487
4.7uF
4.7uF
FOXCONN PCEG
FOXCONN PCEG
FOXCONN PCEG
CPU PWR & GND
CPU PWR & GND
CPU PWR & GND
RS780M09
RS780M09
RS780M09
1
A
A
8 41Monday, November 07, 2011
8 41Monday, November 07, 2011
8 41Monday, November 07, 2011
A
of
of
of
E-CT
5
Foxconn Confidential Document,please keep it secret. M1
D D
MEM_VREFDQ_SUS
R674
R674
*
*
15
15
*
*
+/-1%
+/-1%
R673
R673
*
*
*
*
15
15
+/-1%
+/-1%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
Layout: Place within 500 mils of the DIMMB1 socket.
MEM_VREFCA_SUS
C C
R676
R676
*
*
15
15
*
*
+/-1%
+/-1%
R675
R675
*
*
*
*
15
15
+/-1%
+/-1%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
R460 0 +/-5%
R460 0 +/-5%
*
3D3V_SYS
B B
A A
SMBus Addressing
SMBus 0
Device 8-bit Address (hex) DIMMA0 DIMMB0 DIMMA1 DIMMB1
A0 A2 A4 A6
5
*
MEM_MA_BANK[2..0]6
MEM_MA_ADD[15..0]6
4
MEM_MA_EVENT_L6
MEM_VREFDQ_SUS1D5V_STR
C832
C832
0.1uF
0.1uF
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
Dummy
Dummy
C836
C836
1nF
1nF
C831
C831
*
*
50V, X7R, +/-10%
50V, X7R, +/-10%
0.1uF
0.1uF
MEM_VREFCA_SUS1D5V_STR
C834
C834
0.1uF
0.1uF
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
Dummy
Dummy
C835
C835
1nF
1nF
C833
C833
*
*
50V, X7R, +/-10%
50V, X7R, +/-10%
0.1uF
0.1uF
Layout: Place within 500 mils of the DIMMB1 socket.
VDD_SPD
VDD_SPD 10
MEM_MA_BANK[2..0]
MEM_MA0_CS_L16 MEM_MA0_CS_L06
MEM_MA_ADD[15..0]
4
SDATA010,18,20,34,37
MEM_MA_CKE16 MEM_MA_CKE06
MEM_MA0_CLK1_N6
MEM_MA0_CLK1_P6
MEM_MA0_CLK0_N6
MEM_MA0_CLK0_P6
MEM_MA_RESET#6 MEM_MA_CAS#6 MEM_MA_RAS#6
MEM_MA_WE#6
VTT_DDR
MEM_VREFCA_SUS MEM_VREFDQ_SUS
SCLK010,18,20,34,37
MEM_MA_BANK2 MEM_MA_BANK1 MEM_MA_BANK0
MEM_MA_ADD0 MEM_MA_ADD1 MEM_MA_ADD2 MEM_MA_ADD3 MEM_MA_ADD4 MEM_MA_ADD5 MEM_MA_ADD6 MEM_MA_ADD7 MEM_MA_ADD8 MEM_MA_ADD9 MEM_MA_ADD10 MEM_MA_ADD11 MEM_MA_ADD12 MEM_MA_ADD13 MEM_MA_ADD14 MEM_MA_ADD15
NC/PAR_IN
NC/ERR_OUT
NC/TEST4
DQS*<0>
DQS*<1>
DQS*<2>
DQS*<3>
DQS*<4>
DQS*<5>
DQS*<6>
DQS*<7>
DQS*<8>
DM0/DQS9
DM1/DQS10
DM2/DQS11
DM3/DQS12
DM4/DQS13
DM5/DQS14
DM6/DQS15
DM7/DQS16
NC/DQS16*
DM8/DQS17
DDRIII
DDRIII
RSVD ODT1 ODT0
CB<0> CB<1> CB<2> CB<3> CB<4> CB<5> CB<6> CB<7>
DQS<0>
DQS<1>
DQS<2>
DQS<3>
DQS<4>
DQS<5>
DQS<6>
DQS<7>
DQS<8>
DQS9*
DQS10*
DQS11*
DQS12*
DQS13*
DQS14*
DQS15*
DQS17*
DQ<0> DQ<1> DQ<2> DQ<3> DQ<4> DQ<5> DQ<6> DQ<7> DQ<8>
DQ<9> DQ<10> DQ<11> DQ<12> DQ<13> DQ<14> DQ<15> DQ<16> DQ<17> DQ<18> DQ<19> DQ<20> DQ<21> DQ<22> DQ<23> DQ<24> DQ<25> DQ<26> DQ<27> DQ<28> DQ<29> DQ<30> DQ<31> DQ<32> DQ<33> DQ<34> DQ<35> DQ<36> DQ<37> DQ<38> DQ<39> DQ<40> DQ<41> DQ<42> DQ<43> DQ<44> DQ<45> DQ<46> DQ<47> DQ<48> DQ<49> DQ<50> DQ<51> DQ<52> DQ<53> DQ<54> DQ<55> DQ<56> DQ<57> DQ<58> DQ<59> DQ<60> DQ<61> DQ<62> DQ<63>
3
79 77 195
68 53 167
39 40 45 46 158 159 164 165
7 6
16 15
25 24
34 33
85 84
94 93
103 102
112 111
43 42
125 126
134 135
143 144
152 153
203 204
212 213
221 222
230 231
161 162
3 4 9 10 122 123 128 129 12 13 18 19 131 132 137 138 21 22 27 28 140 141 146 147 30 31 36 37 149 150 155 156 81 82 87 88 200 201 206 207 90 91 96 97 209 210 215 216 99 100 105 106 218 219 224 225 108 109 114 115 227 228 233 234
3
MEM_MA_CHECK0 MEM_MA_CHECK1 MEM_MA_CHECK2 MEM_MA_CHECK3 MEM_MA_CHECK4 MEM_MA_CHECK5 MEM_MA_CHECK6 MEM_MA_CHECK7
MEM_MA_DQS0_P 6
MEM_MA_DQS0_N 6
MEM_MA_DQS1_P 6
MEM_MA_DQS1_N 6
MEM_MA_DQS2_P 6
MEM_MA_DQS2_N 6
MEM_MA_DQS3_P 6
MEM_MA_DQS3_N 6
MEM_MA_DQS4_P 6
MEM_MA_DQS4_N 6
MEM_MA_DQS5_P 6
MEM_MA_DQS5_N 6
MEM_MA_DQS6_P 6
MEM_MA_DQS6_N 6
MEM_MA_DQS7_P 6
MEM_MA_DQS7_N 6
MEM_MA_DQS8_P 6
MEM_MA_DQS8_N 6
MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7
MEM_MA_DM8
MEM_MA_DATA0 MEM_MA_DATA1 MEM_MA_DATA2 MEM_MA_DATA3 MEM_MA_DATA4 MEM_MA_DATA5 MEM_MA_DATA6 MEM_MA_DATA7 MEM_MA_DATA8 MEM_MA_DATA9 MEM_MA_DATA10 MEM_MA_DATA11 MEM_MA_DATA12 MEM_MA_DATA13 MEM_MA_DATA14 MEM_MA_DATA15 MEM_MA_DATA16 MEM_MA_DATA17 MEM_MA_DATA18 MEM_MA_DATA19 MEM_MA_DATA20 MEM_MA_DATA21 MEM_MA_DATA22 MEM_MA_DATA23 MEM_MA_DATA24 MEM_MA_DATA25 MEM_MA_DATA26 MEM_MA_DATA27 MEM_MA_DATA28 MEM_MA_DATA29 MEM_MA_DATA30 MEM_MA_DATA31 MEM_MA_DATA32 MEM_MA_DATA33 MEM_MA_DATA34 MEM_MA_DATA35 MEM_MA_DATA36 MEM_MA_DATA37 MEM_MA_DATA38 MEM_MA_DATA39 MEM_MA_DATA40 MEM_MA_DATA41 MEM_MA_DATA42 MEM_MA_DATA43 MEM_MA_DATA44 MEM_MA_DATA45 MEM_MA_DATA46 MEM_MA_DATA47 MEM_MA_DATA48 MEM_MA_DATA49 MEM_MA_DATA50 MEM_MA_DATA51 MEM_MA_DATA52 MEM_MA_DATA53 MEM_MA_DATA54 MEM_MA_DATA55 MEM_MA_DATA56 MEM_MA_DATA57 MEM_MA_DATA58 MEM_MA_DATA59 MEM_MA_DATA60 MEM_MA_DATA61 MEM_MA_DATA62 MEM_MA_DATA63
MEM_MA0_ODT1 6 MEM_MA0_ODT0 6
MEM_MA_DM[7..0]
MEM_MA_DM8 6
MEM_MA_DATA[63..0]
MEM_MA_CHECK[7..0] 6
MEM_MA_DM[7..0] 6
MEM_MA_DATA[63..0] 6
DIMM1
DIMM1
198
FREE4
187
FREE3
49
FREE2
48
FREE1
240
VTT
120
VTT
239
VSS
235
VSS
232
VSS
229
VSS
226
VSS
223
VSS
220
VSS
217
VSS
214
VSS
211
VSS
208
VSS
205
VSS
202
VSS
199
VSS
166
VSS
163
VSS
160
VSS
157
VSS
154
VSS
151
VSS
148
VSS
145
VSS
142
VSS
139
VSS
136
VSS
133
VSS
130
VSS
127
VSS
124
VSS
121
VSS
119
VSS
116
VSS
113
VSS
110
VSS
107
VSS
104
VSS
101
VSS
98
VSS
95
VSS
92
VSS
89
VSS
86
VSS
83
VSS
80
VSS
47
VSS
44
VSS
41
VSS
38
VSS
35
VSS
32
VSS
29
VSS
26
VSS
23
VSS
20
VSS
17
VSS
14
VSS
11
VSS
8
VSS
5
VSS
2
1D5V_STR
VDD_SPD
VSS
197
VDDQ
194
VDDQ
191
VDDQ
189
VDDQ
186
VDDQ
183
VDDQ
182
VDDQ
179
VDDQ
176
VDDQ
173
VDDQ
170
VDDQ
78
VDD
75
VDD
72
VDD
69
VDD
66
VDD
65
VDD
62
VDD
60
VDD
57
VDD
54
VDD
51
VDD
236
VDDSPD
67
VREFCA
1
VREFDQ
118
SCL
238
SDA
237
SA1
117
SA0
52
BA2
190
BA1
71
BA0
169
CKE1
50
CKE0
76
S1*
193
S0*
UnRegistered
64
CK1/NU*
63
CK1/NU
185
CK0*
184
CK0
188
A0
181
A1
61
A2
180
A3
59
A4
58
A5
178
A6
56
A7
177
A8
175
A9
70
A10/AP
55
A11
174
A12
196
A13
172
A14
171
A15
168
RESET*
74
CAS*
192
RAS*
73
WE*
DDR III
DDR III
2
2
1
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
FOXCONN PCEG
DDR2 DIMM A CHANNEL
DDR2 DIMM A CHANNEL
DDR2 DIMM A CHANNEL
RS780M09
RS780M09
RS780M09
1
A
A
9 41Monday, November 07, 2011
9 41Monday, November 07, 2011
9 41Monday, November 07, 2011
A
of
of
of
E-CT
5
Foxconn Confidential Document,please keep it secret. M1
D D
C C
B B
MEM_MB_ADD[15..0]6
A A
5
VDD_SPD9
4
MEM_MB_BANK[2..0]6
MEM_MB_ADD[15..0]
VDD_SPD
4
MEM_MB_EVENT_L6
MEM_VREFDQ_SUS
MEM_VREFCA_SUS
MEM_MB_BANK[2..0]
MEM_MB0_CS_L16 MEM_MB0_CS_L06
MEM_MB0_CLK1_N6
MEM_MB0_CLK1_P6
MEM_MB0_CLK0_N6
MEM_MB0_CLK0_P6
3
DIMM2
DIMM2
198
FREE4
187
FREE3
49
FREE2
48
VTT_DDR
1D5V_STR
VDD_SPD
MEM_VREFCA_SUS MEM_VREFDQ_SUS
SCLK09,18,20,34,37
SDATA09,18,20,34,37
3D3V_SYS
MEM_MB_BANK2 MEM_MB_BANK1 MEM_MB_BANK0
MEM_MB_CKE16 MEM_MB_CKE06
UnRegistered
MEM_MB_ADD0 MEM_MB_ADD1 MEM_MB_ADD2 MEM_MB_ADD3 MEM_MB_ADD4 MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7 MEM_MB_ADD8 MEM_MB_ADD9 MEM_MB_ADD10 MEM_MB_ADD11 MEM_MB_ADD12 MEM_MB_ADD13 MEM_MB_ADD14 MEM_MB_ADD15
MEM_MB_RESET#6 MEM_MB_CAS#6 MEM_MB_RAS#6
MEM_MB_WE#6
FREE1
240
VTT
120
VTT
239
VSS
235
VSS
232
VSS
229
VSS
226
VSS
223
VSS
220
VSS
217
VSS
214
VSS
211
VSS
208
VSS
205
VSS
202
VSS
199
VSS
166
VSS
163
VSS
160
VSS
157
VSS
154
VSS
151
VSS
148
VSS
145
VSS
142
VSS
139
VSS
136
VSS
133
VSS
130
VSS
127
VSS
124
VSS
121
VSS
119
VSS
116
VSS
113
VSS
110
VSS
107
VSS
104
VSS
101
VSS
98
VSS
95
VSS
92
VSS
89
VSS
86
VSS
83
VSS
80
VSS
47
VSS
44
VSS
41
VSS
38
VSS
35
VSS
32
VSS
29
VSS
26
VSS
23
VSS
20
VSS
17
VSS
14
VSS
11
VSS
8
VSS
5
VSS
2
VSS
197
VDDQ
194
VDDQ
191
VDDQ
189
VDDQ
186
VDDQ
183
VDDQ
182
VDDQ
179
VDDQ
176
VDDQ
173
VDDQ
170
VDDQ
78
VDD
75
VDD
72
VDD
69
VDD
66
VDD
65
VDD
62
VDD
60
VDD
57
VDD
54
VDD
51
VDD
236
VDDSPD
67
VREFCA
1
VREFDQ
118
SCL
238
SDA
237
SA1
117
SA0
52
BA2
190
BA1
71
BA0
169
CKE1
50
CKE0
76
S1*
193
S0*
64
CK1/NU*
63
CK1/NU
185
CK0*
184
CK0
188
A0
181
A1
61
A2
180
A3
59
A4
58
A5
178
A6
56
A7
177
A8
175
A9
70
A10/AP
55
A11
174
A12
196
A13
172
A14
171
A15
168
RESET*
74
CAS*
192
RAS*
73
WE*
DDR III
DDR III
3
NC/PAR_IN
NC/ERR_OUT
NC/TEST4
DQS*<0>
DQS*<1>
DQS*<2>
DQS*<3>
DQS*<4>
DQS*<5>
DQS*<6>
DQS*<7>
DQS*<8>
DM0/DQS9
DM1/DQS10
DM2/DQS11
DM3/DQS12
DM4/DQS13
DM5/DQS14
DM6/DQS15
DM7/DQS16
NC/DQS16*
DM8/DQS17
DDRIII
DDRIII
RSVD ODT1 ODT0
CB<0> CB<1> CB<2> CB<3> CB<4> CB<5> CB<6> CB<7>
DQS<0>
DQS<1>
DQS<2>
DQS<3>
DQS<4>
DQS<5>
DQS<6>
DQS<7>
DQS<8>
DQS9*
DQS10*
DQS11*
DQS12*
DQS13*
DQS14*
DQS15*
DQS17*
DQ<0> DQ<1> DQ<2> DQ<3> DQ<4> DQ<5> DQ<6> DQ<7> DQ<8>
DQ<9> DQ<10> DQ<11> DQ<12> DQ<13> DQ<14> DQ<15> DQ<16> DQ<17> DQ<18> DQ<19> DQ<20> DQ<21> DQ<22> DQ<23> DQ<24> DQ<25> DQ<26> DQ<27> DQ<28> DQ<29> DQ<30> DQ<31> DQ<32> DQ<33> DQ<34> DQ<35> DQ<36> DQ<37> DQ<38> DQ<39> DQ<40> DQ<41> DQ<42> DQ<43> DQ<44> DQ<45> DQ<46> DQ<47> DQ<48> DQ<49> DQ<50> DQ<51> DQ<52> DQ<53> DQ<54> DQ<55> DQ<56> DQ<57> DQ<58> DQ<59> DQ<60> DQ<61> DQ<62> DQ<63>
79 77 195
68 53 167
39
MEM_MB_CHECK0
40
MEM_MB_CHECK1
45
MEM_MB_CHECK2
46
MEM_MB_CHECK3
158
MEM_MB_CHECK4
159
MEM_MB_CHECK5
164
MEM_MB_CHECK6
165
MEM_MB_CHECK7
7 6
16 15
25 24
34 33
85 84
94 93
103 102
112 111
43 42
125 126
134 135
143 144
152 153
203 204
212 213
221 222
230 231
161 162
3
MEM_MB_DATA0
4
MEM_MB_DATA1
9
MEM_MB_DATA2
10
MEM_MB_DATA3
122
MEM_MB_DATA4
123
MEM_MB_DATA5
128
MEM_MB_DATA6
129
MEM_MB_DATA7
12
MEM_MB_DATA8
13
MEM_MB_DATA9
18
MEM_MB_DATA10
19
MEM_MB_DATA11
131
MEM_MB_DATA12
132
MEM_MB_DATA13
137
MEM_MB_DATA14
138
MEM_MB_DATA15
21
MEM_MB_DATA16
22
MEM_MB_DATA17
27
MEM_MB_DATA18
28
MEM_MB_DATA19
140
MEM_MB_DATA20
141
MEM_MB_DATA21
146
MEM_MB_DATA22
147
MEM_MB_DATA23
30
MEM_MB_DATA24
31
MEM_MB_DATA25
36
MEM_MB_DATA26
37
MEM_MB_DATA27
149
MEM_MB_DATA28
150
MEM_MB_DATA29
155
MEM_MB_DATA30
156
MEM_MB_DATA31
81
MEM_MB_DATA32
82
MEM_MB_DATA33
87
MEM_MB_DATA34
88
MEM_MB_DATA35
200
MEM_MB_DATA36
201
MEM_MB_DATA37
206
MEM_MB_DATA38
207
MEM_MB_DATA39
90
MEM_MB_DATA40
91
MEM_MB_DATA41
96
MEM_MB_DATA42
97
MEM_MB_DATA43
209
MEM_MB_DATA44
210
MEM_MB_DATA45
215
MEM_MB_DATA46
216
MEM_MB_DATA47
99
MEM_MB_DATA48
100
MEM_MB_DATA49
105
MEM_MB_DATA50
106
MEM_MB_DATA51
218
MEM_MB_DATA52
219
MEM_MB_DATA53
224
MEM_MB_DATA54
225
MEM_MB_DATA55
108
MEM_MB_DATA56
109
MEM_MB_DATA57
114
MEM_MB_DATA58
115
MEM_MB_DATA59
227
MEM_MB_DATA60
228
MEM_MB_DATA61
233
MEM_MB_DATA62
234
MEM_MB_DATA63
MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7
MEM_MB_DM8
MEM_MB0_ODT1 6 MEM_MB0_ODT0 6
MEM_MB_DQS0_P 6 MEM_MB_DQS0_N 6
MEM_MB_DQS1_P 6 MEM_MB_DQS1_N 6
MEM_MB_DQS2_P 6 MEM_MB_DQS2_N 6
MEM_MB_DQS3_P 6 MEM_MB_DQS3_N 6
MEM_MB_DQS4_P 6 MEM_MB_DQS4_N 6
MEM_MB_DQS5_P 6 MEM_MB_DQS5_N 6
MEM_MB_DQS6_P 6 MEM_MB_DQS6_N 6
MEM_MB_DQS7_P 6 MEM_MB_DQS7_N 6
MEM_MB_DQS8_P 6 MEM_MB_DQS8_N 6
MEM_MB_DM8 6
MEM_MB_DATA[63..0]
MEM_MB_CHECK[7..0] 6
MEM_MB_DM[7..0]
MEM_MB_DATA[63..0] 6
2
MEM_MB_DM[7..0] 6
2
1
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
FOXCONN PCEG
DDR2 DIMM B CHANNEL
DDR2 DIMM B CHANNEL
DDR2 DIMM B CHANNEL
RS780M09
RS780M09
RS780M09
1
A
A
10 41Monday, November 07, 2011
10 41Monday, November 07, 2011
10 41Monday, November 07, 2011
A
of
of
of
E-CT
5
Foxconn Confidential Document,please keep it secret. M1
D D
EMI decoupling cap, place evenly around 1D8V_STR
C C
4
C623 10nF
C623 10nF C626 0.1uF
C626 0.1uF C618 0.1uF
C618 0.1uF C621 0.1uF
C621 0.1uF C629 1uF
C629 1uF C604 1uF
C604 1uF C642 1uF
C642 1uF C617 1uF
C617 1uF C641 1uF
C641 1uF C622 1uF
C622 1uF C635 1uF
C635 1uF C644 1uF
C644 1uF
*
*
12
*
* *
* *
* *
*
*
*
Dummy
Dummy
*
*
*
*
Dummy
Dummy
*
*
Dummy
DummyDummy
*
*
Dummy
Dummy
*
*
Dummy
Dummy
*
*
Dummy
Dummy
3
*
*
C610 1uF
1D5V_STR VTT_DDR
C610 1uF
*
*
C612 1uF
C612 1uF
2
1
B B
UnRegistered
A A
FOXCONN PCEG
FOXCONN PCEG
FOXCONN PCEG
DDR2 DIMM POWER
DDR2 DIMM POWER
DDR2 DIMM POWER
RS780M09
RS780M09
RS780M09
11 41Monday, November 07, 2011
11 41Monday, November 07, 2011
11 41Monday, November 07, 2011
1
5
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
A
A
A
of
of
of
E-CT
5
Foxconn Confidential Document,please keep it secret. M1
D D
C C
4
3
2
1
B B
UnRegistered
A A
FOXCONN PCEG
FOXCONN PCEG
FOXCONN PCEG
DDR2 DIMM TERMINATIONS
DDR2 DIMM TERMINATIONS
DDR2 DIMM TERMINATIONS
RS780M09
RS780M09
RS780M09
12 41Monday, November 07, 2011
12 41Monday, November 07, 2011
12 41Monday, November 07, 2011
1
5
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
A
A
A
of
of
of
E-CT
5
Foxconn Confidential Document,please keep it secret. M1
D D
RX780/RS740/RS780 difference table (HT LINK)
C C
SIGNALS HT_RXCALP HT_RXCALN HT_TXCALP HT_TXCALN
RS740 RX780
49.9R (GND)
49.9R (VDDHT)
1.21K
1.21K100R
RS780
301R
301R
HT_CADOUT0_P5 HT_CADOUT0_N5 HT_CADOUT1_P5 HT_CADOUT1_N5 HT_CADOUT2_P5 HT_CADOUT2_N5 HT_CADOUT3_P5 HT_CADOUT3_N5 HT_CADOUT4_P5 HT_CADOUT4_N5 HT_CADOUT5_P5 HT_CADOUT5_N5 HT_CADOUT6_P5 HT_CADOUT6_N5 HT_CADOUT7_P5 HT_CADOUT7_N5
HT_CADOUT8_P5 HT_CADOUT8_N5 HT_CADOUT9_P5 HT_CADOUT9_N5 HT_CADOUT10_P5 HT_CADOUT10_N5 HT_CADOUT11_P5 HT_CADOUT11_N5 HT_CADOUT12_P5 HT_CADOUT12_N5 HT_CADOUT13_P5 HT_CADOUT13_N5 HT_CADOUT14_P5 HT_CADOUT14_N5 HT_CADOUT15_P5 HT_CADOUT15_N5
HT_CLKOUT0_P5 HT_CLKOUT0_N5 HT_CLKOUT1_P5 HT_CLKOUT1_N5
HT_CTLOUT0_P5 HT_CTLOUT0_N5 HT_CTLOUT1_P5 HT_CTLOUT1_N5
4
HT_RXCALN
HT_RXCALP
R656
R656
49.9
49.9 R655
R655
49.9
49.9
R320
R320 301
301
*
*
+/-1%
+/-1%
@RS780L
@RS780L
+/-1%
+/-1%
*
*
@RS740
@RS740
+/-1%
+/-1%
*
*
@RS740
@RS740
HT_RXCALP
1D1V_CORE
U18A
U18A
Y25
HT_RXCAD0P
Y24
HT_RXCAD0N
V22
HT_RXCAD1P
V23
HT_RXCAD1N
V25
HT_RXCAD2P
V24
HT_RXCAD2N
U24
HT_RXCAD3P
U25
HT_RXCAD3N
T25
HT_RXCAD4P
T24
HT_RXCAD4N
P22
HT_RXCAD5P
P23
HT_RXCAD5N
P25
HT_RXCAD6P
P24
HT_RXCAD6N
N24
HT_RXCAD7P
N25
HT_RXCAD7N
AC24
HT_RXCAD8P
AC25
HT_RXCAD8N
AB25
HT_RXCAD9P
AB24
HT_RXCAD9N
AA24
HT_RXCAD10P
AA25
HT_RXCAD10N
Y22
HT_RXCAD11P
Y23
HT_RXCAD11N
W21
HT_RXCAD12P
W20
HT_RXCAD12N
V21
HT_RXCAD13P
V20
HT_RXCAD13N
U20
HT_RXCAD14P
U21
HT_RXCAD14N
U19
HT_RXCAD15P
U18
HT_RXCAD15N
T22
HT_RXCLK0P
T23
HT_RXCLK0N
AB23
HT_RXCLK1P
AA22
HT_RXCLK1N
M22
HT_RXCTL0P
M23
HT_RXCTL0N
R21
HT_RXCTL1P
R20
HT_RXCTL1N
C23
HT_RXCALP
A24
HT_RXCALN
RS780(RX780)
RS780(RX780)
#U46#U47#U49
#U46#U47#U49
3
PART 1 OF 6
PART 1 OF 6
HYPER TRANSPORT CPU I/F
HYPER TRANSPORT CPU I/F
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
HT_TXCTL0P HT_TXCTL0N HT_TXCTL1P HT_TXCTL1N
HT_TXCALP HT_TXCALN
D24 D25 E24 E25 F24 F25 F23 F22 H23 H22 J25 J24 K24 K25 K23 K22
F21 G21 G20 H21 J20 J21 J18 K17 L19 J19 M19 L18 M21 P21 P18 M18
H24 H25 L21 L20
M24 M25 P19 R18
B24 B25
HT_TXCALP
HT_TXCALNHT_RXCALN
VR11
VR11
301
301
*
*
+/-1%
+/-1%
@RS780L
@RS780L
R306
R306 301
301
*
*
+/-1%
+/-1%
#VR11#VR12
#VR11#VR12
VR12
VR12
HT_CADIN0_P 5 HT_CADIN0_N 5 HT_CADIN1_P 5 HT_CADIN1_N 5 HT_CADIN2_P 5 HT_CADIN2_N 5 HT_CADIN3_P 5 HT_CADIN3_N 5 HT_CADIN4_P 5 HT_CADIN4_N 5 HT_CADIN5_P 5 HT_CADIN5_N 5 HT_CADIN6_P 5 HT_CADIN6_N 5 HT_CADIN7_P 5 HT_CADIN7_N 5
HT_CADIN8_P 5 HT_CADIN8_N 5 HT_CADIN9_P 5 HT_CADIN9_N 5 HT_CADIN10_P 5 HT_CADIN10_N 5 HT_CADIN11_P 5 HT_CADIN11_N 5 HT_CADIN12_P 5 HT_CADIN12_N 5 HT_CADIN13_P 5 HT_CADIN13_N 5 HT_CADIN14_P 5 HT_CADIN14_N 5 HT_CADIN15_P 5 HT_CADIN15_N 5
HT_CLKIN0_P 5 HT_CLKIN0_N 5 HT_CLKIN1_P 5 HT_CLKIN1_N 5
HT_CTLIN0_P 5 HT_CTLIN0_N 5 HT_CTLIN1_P 5 HT_CTLIN1_N 5
100 Ohm
100 Ohm
*
*
+/-1%
+/-1%
@RS740
@RS740
2
1
U47
U46
U18_1
B B
1
U18_1
1
AMD
AMD
Heatsink_NB
Heatsink_NB
2
2
U46
Dummy
Dummy
RS780C
RS780C
U47
RS740
RS740
215RVA6BVA11FG
215RVA6BVA11FG
@RS740
@RS740
U49
@RS780LU49
@RS780L
215-0674058
215-0674058
UnRegistered
A A
FOXCONN PCEG
FOXCONN PCEG
FOXCONN PCEG
RS740/RX780/RS780-HT LINK I/F
RS740/RX780/RS780-HT LINK I/F
RS740/RX780/RS780-HT LINK I/F
RS780M09
RS780M09
RS780M09
13 41Monday, November 07, 2011
13 41Monday, November 07, 2011
13 41Monday, November 07, 2011
1
5
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
A
A
A
of
of
of
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