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MCP61M07
Schematics
37 pgs3.58 Mb0

Foxcon MCP61M07 Schematics

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Foxconn MCP61M07
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1
D D
Fab :A
nVIDIA MCP61 Chipset for AMD AM3 CPU
(12/04/2010)
PAGE PAGECONTENT CONTENT
1 2 3
C C
4 5 6 7 8
9 10 11 12 13
B B
14 15 16 17 18 19 20 21 22
A A
23 24
01. COVER
02. BLOCK DIAGRAM
03. RESET MAP
04. CLOCK DISTRIBUTION
05. PCI DEVICE / VID TABLE
06. AM3-1 Hyper Transport
07. AM3-2 DDRII -1
08. AM3-2 DDRII -2
09. AM3-3 MISC
10. AM3-4 Power
11. DDRIII SDRAM DIMM1-2
12. DDRIII Terminator
13. MCP61_HT
14. MCP61_PCI-E_RGM_VGA
15. MCP61_POWER
16. MCP61_PCI
17. MCP61_SATA_IDE
18. MCP61_HDA_USB
19. PCI_E X16 Slot
20. PCI SLOT 1 2 3
21. SIO IT8728F
22. IDE / Floppy / PS2
23. PLT / COM
24. FAN / HARDWARE MONITOR /VID
25. USB CONNECTORS
25
26. LAN
26
27. PWR CONN / FNT PNL / VBAT
27
28. ACPI VREG
28
29. MCP61 CORE POWER
29
30. VRM
30
31. LAN CONN
31
32. AUDIO ALC662
32
33. Power Map
33
34. Modify List
34
35. Optional Part
35
LEADTEK RESEARCH INC. ASSUMES NO RESPONSIBILITY FOR ANY ERRORS IN DRAWING THESE SCHEMATICS. THESE SCHEMATICS ARE SUBJECT TO CHANGE AT ANY TIME WITHOUT NOTICE. COPYRIGHT 2002 LEADTEK RESEARCH INC. .
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FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Cover
Cover
Cover
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
FOXCONN PCEG
MCP61M07
MCP61M07
MCP61M07
1
1 35Wednesday, December 08, 2010
1 35Wednesday, December 08, 2010
1 35Wednesday, December 08, 2010
of
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AC
AC
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www.vinaļ¬x.vn
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MCP61M07 Block Diagram
POWER
SUPPLY CONNECTOR 2*12 = 24 pin 2*2 = 4 pin (12V)
C C
PCI Express X16
PCI Express X1
VREG -> RT8855 => 3 +1 phase
60 Amp
PCI EXPRESS Lane * 16
PCI EXPRESS Lane * 1
SOCKET AM3
HT 16X16 2GT/S
NFORCE
MCP61
DDRIII Memory CH:A
DDRIII Memory CH:B
PCI V2.3 / 33MHZ
64-BIT 1600/1333/1066MHZ
PCI SLOT 1
PCI SLOT 2
DDRIII SDRAM CONN 1
DDRIII SDRAM CONN 2
PCI_RESET0*
S I/OPWRBTN#
CPU_VLD
HT_VLD
SB ACPIPS_ON#
SLP_S5* SLP_S3*
VRM_EN
VRM
PWM_GD
SWPANSWHJ
PS_OUT#
PWRGD_PS
ATX POWER
692 Ball BGA
HDA
SIO
ITE IT8728F/CX
INTEGRATED SATA
LPC BUS V1.0 / 33MHZ
4MB FLASH
X8 USB ( V2.0 EHCI / V1.1 OHCI )
RGMII/MII
B B
PS2/KB CONN
PARALLEL CONN
SERIAL CONN (COM1)
SATA-II CONN * 4
Azalia / ALC662 (5.1 Audio)
BACK PANEL CONN => 4 Port
USB2 PORTS 0,7
USB2 PORTS 1,6 10/100Mb (Giga-Bit )LAN PHY
FRONT PANEL Header * 2 => 4 Port
USB2 PORTS 2,4
USB2 PORTS 3,5
RTL8201EL/RTL8211CL
A A
FOXCONN PCEG
FOXCONN PCEG
FOXCONN PCEG
MCP61M07
MCP61M07
MCP61M07
1
2 35Wednesday, December 08, 2010
2 35Wednesday, December 08, 2010
2 35Wednesday, December 08, 2010
AC
AC
AC
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Title
Title
Title
Block Diagram
Block Diagram
Block Diagram
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
3
2
Date: Sheet
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1
RESET MAP
D D
Socket AM3
CPU RST*
CPU PWRGD
MCP61
AUDIO_PHY
RESET*
PSON#
HT_CPU_PWRGD
HT_CPU_RST*
PCIRST_SLOT1*
PCIRST_SLOT2*
PCIRST_SLOT3*
PCIRST_IDE*
LPCRST_FLASH*
LPCRST_SIO*
ATX
Power Supply
PWRGD_PS
PWRGD_PS
PWR_OK
(46)
MCP61
PWRGDPWROK
SEC IDE
TIGER ONE
ALL_PWR_OK
HT_VLD
(1)
HT_VLD
ALL_PWROK
PWM_GD
(8)
VRM_EN
(9)
PWM_GD
VRM_EN
CPU
PWROK
PGOOD
(35)
ENLL (37)
PCI SLOT 1PCI SLOT 2VT6307PRI IDEFLASHSIO
VRM
PE_RESET*
PEX X16
PEX X1
PWR CONN
C C
B B
PS ON
PWR GOOD
PWRGD SB
CIRCUIT
PWR SWTCH
PWRBTN*
SLP_S3*
POWER_GOOD
PWRGD_SB
PWR BUTTON
SLP S3*
PWRGD
PWRGD_SB
GPIO_AUX*
LAN_PHY
RESET*
HT CPU PWRGD
HT CPU RST*
PCI RST0*
PCI RST1*
PCI RST2*
PCI RST3*
LPC_RST*
AC_RESET*
POWER ON SCHEME
MCP61
SLP_S3#
PWBTN#
SLP_S5#
PWRBTN#
Power button input
PANSWHJ
PWRON#
(72)
PANSWH#
IT8728F
PSIN
(71)
PSON#
TIGER ONE
PS_ON_IN#
(6)(75) (76)
PS_ON_OUT#
(7)
A A
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Reset Map
Reset Map
Reset Map
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
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2
Date: Sheet
FOXCONN PCEG
MCP61M07
MCP61M07
MCP61M07
1
AC
AC
AC
of
of
of
3 35Wednesday, December 08, 2010
3 35Wednesday, December 08, 2010
3 35Wednesday, December 08, 2010
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D D
HT_CPU_TXCLK0
HT_CPU_TXCLK0*
HT_CPU_RXCLK0 HT_CPU_RXCLK0*
HT_CPU_TXCLK1 HT_CPU_TXCLK1*
HT_CPU_RXCLK1 HT_CPU_RXCLK1*
CPUCLK_IN*
CPUCLK_IN
AM3 CPU
MEMCLK_L[0,5,7] MEMCLK_H[0,5,7]
MEMCLK_L[2,3] MEMCLK_H[2,3]
MEMCLK_L[1,4,6] MEMCLK_H[1,4,6]
NC
CHANNEL A1 0-63
CHANNEL B1 0~63
DIMM 0
DIMM 1
MCP61
CLKOUT_200MHZ CLKOUT_200MHZ*
HT_CPU_RXCLK1*
HT_CPU_RXCLK1
HT_CPU_TXCLK1*
C C
32.768 KHZ
B B
25 MHZ
HT_CPU_TXCLK1
HT_CPU_RXCLK0* HT_CPU_RXCLK0
HT_CPU_TXCLK0* HT_CPU_TXCLK0
RTC_XTAL
XTAL_IN
XTAL_OUT
PE0_REFCLK PE0_REFCLK*
PE1_REFCLK PE1_REFCLK*
PE2_REFCLK PE2_REFCLK*
LPC_CLK0
PCI_CLK0 PCI_CLK1 PCI_CLK2 PCI_CLK3 PCI_CLK4
PCI_CLK_FB
LPC_CLK1
AC_BITCLK
BUF_25MHZ
BUF_SIO
SUSCLK
14MHZ OR 24MHZ
SIO
AZALIA CODEC
PEX X16
PEX X1
FLASH
LPC
HEADER
PCI SLOT 1
PCI SLOT 2
PCI SLOT 3
LAN PHY
A A
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Clock Distribution
Clock Distribution
Clock Distribution
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
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Date: Sheet
FOXCONN PCEG
MCP61M07
MCP61M07
MCP61M07
1
4 35Wednesday, December 08, 2010
4 35Wednesday, December 08, 2010
4 35Wednesday, December 08, 2010
AC
AC
AC
of
of
of
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D D
VID [4..0]
0X00000
0X00001
0X00010
0X00011
0X00100
0X00101
0X00110
0X00111
0X01000
0X01001
0X01010
0X01011
0X01100
0X01101
0X01110
C C
B B
0X01111
CPU VID TABLE
VDD
1.550V
1.525V
1.500V
1.475V
1.450V
1.425V
1.400V
1.375V
1.350V
1.325V
1.300V
1.275V
1.250V
1.225V
1.200V
1.175V 0X11111
SMBUS ADDRESS MAP
DEVICE
DIMM 0 0
DIMM 1 0
DIMM 2
DIMM 3
SIO
PCI SLOT 1
PCI SLOT 2
1394
DDC BUS
DDC BUS
SMBUS #
VID [4..0]
0X10000
0X10001
0X10010
0X10011
0X10100
0X10101
0X10110
0X10111
0X11000
0X11001
0X11010
0X11011
0X11100
0X11101
0X11110
VDD
1.150V
1.125V
1.100V
1.075V
1.050V
1.025V
1.000V
0.975V
0.950V
0.925V
0.900V
0.875V
0.850V
0.825V
0.800V
OFF
ADDRESS
1010 000 = 0X50
1010 001 = 0X51
0
1010 010 = 0X52
0
1010 011 = 0X53
1
0101 101 = 0X2D
ARP
1
ARP
1
1
ARP
A
?
B
?
BACK PANEL
SLOT
VT6308
PCI 1
PCI DEVICE MAP
DEVICE
MCP 61
MAC /MAC
PCI-PCI BRIDGE
SATA1 X8 0
SATA0 0 X8 0
IDE X6
MODEM CODEC 0
AUDIO CODEC X4 0
USB 2.0 X2
USB 1.1 0 X2 0
SHAPE TRIM
LDT 0 X0 0
SMBUS2
LEGACY SLAVE
LPC
LOGICAL PCI BUS
PCI SLOT 1
PCI SLOT 2
PCI SLOT 3
PCI SLOT 4
PCI SLOT 5
PCI BUS# DEVICE# IDSEL PIN PCI SLOT PCI SLOT
PCI INTERRUPT/IDSEL MAP
P_INTZ*
DEVICE#
0X01-0X0F
22
P_INTW*
23
P_INTX* P_INTW*
24
FUNCTION
XA
X9
X4
X1
X1
?
X1
?
0
0
1
1
2
1
?
0
?
01
01PCI 2
0X06
0X08
PCI BUS#
MCP51 LOGICAL PCI BUS 0
0
00
0
0
0
0
0
0
0
0
1
DEVICE ID
0X56/57
0X005C
0X0055
0X0054
0X0053
0X0058
0X0059
0X005B
0X005A
0X005F
0X005E
0X0052
0X00D3
0X0050/51
?
P_INTX*
P_INTY*
----
INTC*INTB*INTA*
P_INTY*
P_INTZ*
PCI SLOTPCI SLOT
INTD*
SOT23
1
SOT23-6
6
12
REQ/GNT
1/1
2/2P_INTZ*
3/301 0X09
SOT23-5/SC70
SOT89-5
3
2
45
3
21
SOT223
45
3
4
321
A A
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
PCI Device / VID Table
PCI Device / VID Table
PCI Device / VID Table
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
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Date: Sheet
FOXCONN PCEG
MCP61M07
MCP61M07
MCP61M07
1
5 35Saturday, December 04, 2010
5 35Saturday, December 04, 2010
5 35Saturday, December 04, 2010
AC
AC
AC
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HyperTransport
U206A
D D
C C
CPU HyperTransport and Debug
A1
AM3 Top View
AL1
U206IU206I
5
MTG1
6
MTG1
7
MTG1
8
MTG1
9
MTG1
10
MTG1
11
MTG1
12
MTG1
1
EMI
2
EMI
13
MTG2
14
MTG2
15
MTG2
16
MTG2
17
MTG2
18
MTG2
19
MTG2
20
MTG2
A31
AL31
21
MTG3
22
MTG3
23
MTG3
24
MTG3
25
MTG3
26
MTG3
27
MTG3
28
MTG3
3
EMI
4
EMI
29
MTG4
30
MTG4
31
MTG4
32
MTG4
33
MTG4
34
MTG4
35
MTG4
36
MTG4
+1.2V_HT
HT_RC_CPU_CAD_H[15..0]13 HT_RC_CPU_CAD_L[15..0]13
HT_RC_CPU_CLK_H113 HT_RC_CPU_CLK_L113 HT_RC_CPU_CLK_H013 HT_RC_CPU_CLK_L013
R150 49.9 +/-1%
R150 49.9 +/-1%
*
*
R149 49.9 +/-1%
R149 49.9 +/-1%
*
*
HT_RC_CPU_CTL_H013 HT_RC_CPU_CTL_L013
HT_CPU_CTLIN_H1 HT_CPU_CTLIN_L1
HT_RC_CPU_CAD_H15 HT_RC_CPU_CAD_L15 HT_RC_CPU_CAD_H14 HT_RC_CPU_CAD_L14 HT_RC_CPU_CAD_H13 HT_RC_CPU_CAD_L13 HT_RC_CPU_CAD_H12 HT_RC_CPU_CAD_L12 HT_RC_CPU_CAD_H11 HT_RC_CPU_CAD_L11 HT_RC_CPU_CAD_H10 HT_RC_CPU_CAD_L10 HT_RC_CPU_CAD_H9 HT_RC_CPU_CAD_L9 HT_RC_CPU_CAD_H8 HT_RC_CPU_CAD_L8
HT_RC_CPU_CAD_H7 HT_RC_CPU_CAD_L7 HT_RC_CPU_CAD_H6 HT_RC_CPU_CAD_L6 HT_RC_CPU_CAD_H5 HT_RC_CPU_CAD_L5 HT_RC_CPU_CAD_H4 HT_RC_CPU_CAD_L4 HT_RC_CPU_CAD_H3 HT_RC_CPU_CAD_L3 HT_RC_CPU_CAD_H2 HT_RC_CPU_CAD_L2 HT_RC_CPU_CAD_H1 HT_RC_CPU_CAD_L1 HT_RC_CPU_CAD_H0 HT_RC_CPU_CAD_L0
U206A
N6
L0_CLKIN_H1
P6
L0_CLKIN_L1
N3
L0_CLKIN_H0
N2
L0_CLKIN_L0
V4
L0_CTLIN_H1
V5
L0_CTLIN_L1
U1
L0_CTLIN_H0
V1
L0_CTLIN_L0
U6
L0_CADIN_H15
V6
L0_CADIN_L15
T4
L0_CADIN_H14
T5
L0_CADIN_L14
R6
L0_CADIN_H13
T6
L0_CADIN_L13
P4
L0_CADIN_H12
P5
L0_CADIN_L12
M4
L0_CADIN_H11
M5
L0_CADIN_L11
L6
L0_CADIN_H10
M6
L0_CADIN_L10
K4
L0_CADIN_H9
K5
L0_CADIN_L9
J6
L0_CADIN_H8
K6
L0_CADIN_L8
U3
L0_CADIN_H7
U2
L0_CADIN_L7
R1
L0_CADIN_H6
T1
L0_CADIN_L6
R3
L0_CADIN_H5
R2
L0_CADIN_L5
N1
L0_CADIN_H4
P1
L0_CADIN_L4
L1
L0_CADIN_H3
M1
L0_CADIN_L3
L3
L0_CADIN_H2
L2
L0_CADIN_L2
J1
L0_CADIN_H1
K1
L0_CADIN_L1
J3
L0_CADIN_H0
J2
L0_CADIN_L0
PZ94121-3126-01F
PZ94121-3126-01F
L0_CLKOUT_H1 L0_CLKOUT_L1 L0_CLKOUT_H0 L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9 L0_CADOUT_L9 L0_CADOUT_H8 L0_CADOUT_L8
L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H4
HT LINK
HT LINK
L0_CADOUT_L4 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H0 L0_CADOUT_L0
AD5 AD4 AD1 AC1
Y6 W6 W2 W3
Y5 Y4 AB6 AA6 AB5 AB4 AD6 AC6 AF6 AE6 AF5 AF4 AH6 AG6 AH5 AH4
Y1 W1 AA2 AA3 AB1 AA1 AC2 AC3 AE2 AE3 AF1 AE1 AG2 AG3 AH1 AG1
HT_CPU_CTLOUT_H1 HT_CPU_CTLOUT_L1
HT_CPU_RC_CAD_H15 HT_CPU_RC_CAD_L15 HT_CPU_RC_CAD_H14 HT_CPU_RC_CAD_L14 HT_CPU_RC_CAD_H13 HT_CPU_RC_CAD_L13 HT_CPU_RC_CAD_H12 HT_CPU_RC_CAD_L12 HT_CPU_RC_CAD_H11 HT_CPU_RC_CAD_L11 HT_CPU_RC_CAD_H10 HT_CPU_RC_CAD_L10 HT_CPU_RC_CAD_H9 HT_CPU_RC_CAD_L9 HT_CPU_RC_CAD_H8 HT_CPU_RC_CAD_L8
HT_CPU_RC_CAD_H7 HT_CPU_RC_CAD_L7 HT_CPU_RC_CAD_H6 HT_CPU_RC_CAD_L6 HT_CPU_RC_CAD_H5 HT_CPU_RC_CAD_L5 HT_CPU_RC_CAD_H4 HT_CPU_RC_CAD_L4 HT_CPU_RC_CAD_H3 HT_CPU_RC_CAD_L3 HT_CPU_RC_CAD_H2 HT_CPU_RC_CAD_L2 HT_CPU_RC_CAD_H1 HT_CPU_RC_CAD_L1 HT_CPU_RC_CAD_H0 HT_CPU_RC_CAD_L0
HT_CPU_RC_CLK_H1 13 HT_CPU_RC_CLK_L1 13 HT_CPU_RC_CLK_H0 13 HT_CPU_RC_CLK_L0 13
1
TP15TP15
1
TP13TP13
HT_CPU_RC_CTL_H0 13 HT_CPU_RC_CTL_L0 13
HT_CPU_RC_CAD_H[15..0] 13 HT_CPU_RC_CAD_L[15..0] 13
CPUHS1
CPUHS1
HEATSINK_SOCKET_940_M2
HEATSINK_SOCKET_940_M2
B B
CPU_DBREQ#8
CPU_DBRDY8
CPU_TCK8 CPU_TMS8 CPU_TDI8
CPU_TRST#8
CPU_TDO8
1D5V_STR
HDT Connector
Use buffered reset
HDT1
HDT1
C11C2 C33C4 C55C6 C77C8 C99C10 C1111C12 C1313C14 C1515C16 C1717C18 C1919C20 C2121C22 C2323C24
X
X
C26
Header_2X13_K25
Header_2X13_K25
Dummy
Dummy
2 4 6 8 10 12 14 16 18 20 22 24 26
R413 0
R413 0
Dummy
Dummy
1D5V_STR
+3.3V
R384
R384
*
*
4.7K
Dummy
4.7K
Dummy
+/-5%
+/-5%
*
*
+/-5%
+/-5%
Dummy
Dummy
Q52
Q52
Dummy
Dummy
D S
R383 0
R383 0
Dummy
Dummy
*
*
G
*
*
R387
R387 0
0
+/-5%
+/-5%
FDV301N
FDV301N
+/-5%
+/-5%
CPU_HT_RESET_L 8,13
HDT Header
A A
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
AM3 HyperTransport
AM3 HyperTransport
AM3 HyperTransport
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
5
4
3
2
FOXCONN PCEG
MCP61M07
MCP61M07
MCP61M07
6 35Saturday, December 04, 2010
6 35Saturday, December 04, 2010
6 35Saturday, December 04, 2010
1
AC
AC
AC
of
of
of
5
4
3
2
1
DDR3 Memory Interface A DDR3 Memory Interface B
CPU Memory
U206B
U206B
AG21
MA_CLK_H7
AG20
MA_CLK_L7
AE20
MA_CLK_H6
AE19
MA_CLK_L6
U27
MA_CLK_H5
U26
MA_CLK_L5
MEM_MA_BANK2 MEM_MA_BANK1 MEM_MA_BANK0
AC25 AA24
AE28 AC28
AD27 AA25
AE27 AC27
AB25 AB27 AA26
AA27
AC26
AD15 AE15 AG18 AG19 AG24 AG25 AG27 AG28
AF15 AF19
AH29
V27 W27 W26 W25
U24
V24
G19
H19
G20
G21
E20
N25
Y27
L27
M25
M27
N24
N26
P25
Y25
N27
R24
P27
R25
R26
R27
T25
U25
T27 W24
D29
C29
C25
D25
E19
F19
F15
G15
AJ25
B29
E24
E18
H15
MA_CLK_H4 MA_CLK_L4 MA_CLK_H3 MA_CLK_L3 MA_CLK_H2 MA_CLK_L2 MA_CLK_H1 MA_CLK_L1 MA_CLK_H0 MA_CLK_L0
MA0_CS_L1 MA0_CS_L0
MA0_ODT1 MA0_ODT0
MA1_CS_L1 MA1_CS_L0
MA1_ODT1 MA1_ODT0
MA_RESET_L
MA_CAS_L MA_WE_L MA_RAS_L
MA_BANK2 MA_BANK1 MA_BANK0
MA_CKE1 MA_CKE0
MA_ADD15 MA_ADD14 MA_ADD13 MA_ADD12 MA_ADD11 MA_ADD10 MA_ADD9 MA_ADD8 MA_ADD7 MA_ADD6 MA_ADD5 MA_ADD4 MA_ADD3 MA_ADD2 MA_ADD1 MA_ADD0
MA_DQS_H7 MA_DQS_L7 MA_DQS_H6 MA_DQS_L6 MA_DQS_H5 MA_DQS_L5 MA_DQS_H4 MA_DQS_L4 MA_DQS_H3 MA_DQS_L3 MA_DQS_H2 MA_DQS_L2 MA_DQS_H1 MA_DQS_L1 MA_DQS_H0 MA_DQS_L0
MA_DM7 MA_DM6 MA_DM5 MA_DM4 MA_DM3 MA_DM2 MA_DM1 MA_DM0
MEM CHA
MEM CHA
PZ94121-3126-01F
PZ94121-3126-01F
MA1 & MA_CKE1
CPU
D D
C C
B B
MEM_MA0_CLK0_P10 MEM_MA0_CLK0_N10
MEM_MA0_CLK1_P10 MEM_MA0_CLK1_N10
MEM_MA0_CS_L110 MEM_MA0_CS_L010
MEM_MA0_ODT110 MEM_MA0_ODT010
MEM_MA_RESET#10 MEM_MB_RESET#11
MEM_MA_CAS#10 MEM_MA_WE#10 MEM_MA_RAS#10
MEM_MA_BANK[2..0]10 MEM_MB_BANK[2..0]11
MEM_MA_CKE010
MEM_MA_ADD[15..0]10 MEM_MB_ADD[15..0]11
MEM_MA_DQS7_P10 MEM_MA_DQS7_N10 MEM_MA_DQS6_P10 MEM_MA_DQS6_N10 MEM_MA_DQS5_P10 MEM_MA_DQS5_N10 MEM_MA_DQS4_P10 MEM_MA_DQS4_N10 MEM_MA_DQS3_P10 MEM_MA_DQS3_N10 MEM_MA_DQS2_P10 MEM_MA_DQS2_N10 MEM_MA_DQS1_P10 MEM_MA_DQS1_N10 MEM_MA_DQS0_P10 MEM_MA_DQS0_N10
MEM_MA_DM[7..0]10 MEM_MB_DM[7..0]11
MEM_MA_ADD15 MEM_MA_ADD14 MEM_MA_ADD13 MEM_MA_ADD12 MEM_MA_ADD11 MEM_MA_ADD10 MEM_MA_ADD9 MEM_MA_ADD8 MEM_MA_ADD7 MEM_MA_ADD6 MEM_MA_ADD5 MEM_MA_ADD4 MEM_MA_ADD3 MEM_MA_ADD2 MEM_MA_ADD1 MEM_MA_ADD0
MEM_MA_DM7 MEM_MA_DM6 MEM_MA_DM5 MEM_MA_DM4 MEM_MA_DM3 MEM_MA_DM2 MEM_MA_DM1 MEM_MA_DM0
MA0 & MA_CKE0
CPU
A A
TO DIMMA0
A0
MA_DATA63 MA_DATA62 MA_DATA61 MA_DATA60 MA_DATA59 MA_DATA58 MA_DATA57 MA_DATA56 MA_DATA55 MA_DATA54 MA_DATA53 MA_DATA52 MA_DATA51 MA_DATA50 MA_DATA49 MA_DATA48 MA_DATA47 MA_DATA46 MA_DATA45 MA_DATA44 MA_DATA43 MA_DATA42 MA_DATA41 MA_DATA40 MA_DATA39 MA_DATA38 MA_DATA37 MA_DATA36 MA_DATA35 MA_DATA34 MA_DATA33 MA_DATA32 MA_DATA31 MA_DATA30 MA_DATA29 MA_DATA28 MA_DATA27 MA_DATA26 MA_DATA25 MA_DATA24 MA_DATA23 MA_DATA22 MA_DATA21 MA_DATA20 MA_DATA19 MA_DATA18 MA_DATA17 MA_DATA16 MA_DATA15 MA_DATA14 MA_DATA13 MA_DATA12 MA_DATA11 MA_DATA10
MA_DATA9 MA_DATA8 MA_DATA7 MA_DATA6 MA_DATA5 MA_DATA4 MA_DATA3 MA_DATA2 MA_DATA1 MA_DATA0
MA_DQS_H8 MA_DQS_L8
MA_DM8
MA_CHECK7 MA_CHECK6 MA_CHECK5 MA_CHECK4 MA_CHECK3 MA_CHECK2 MA_CHECK1 MA_CHECK0
MA_EVENT_L
TO DIMMA1
AE14 AG14 AG16 AD17 AD13 AE13 AG15 AE16 AG17 AE18 AD21 AG22 AE17 AF17 AF21 AE21 AF23 AE23 AJ26 AG26 AE22 AG23 AH25 AF25 AJ28 AJ29 AF29 AE26 AJ27 AH27 AG29 AF27 E29 E28 D27 C27 G26 F27 C28 E27 F25 E25 E23 D23 E26 C26 G23 F23 E22 E21 F17 G17 G22 F21 G18 E17 G16 E15 G13 H13 H17 E16 E14 G14
J28 J27
J25
K25 J26 G28 G27 L24 K27 H29 H27
W30
MEM_MA_DATA63 MEM_MA_DATA62 MEM_MA_DATA61 MEM_MA_DATA60 MEM_MA_DATA59 MEM_MA_DATA58 MEM_MA_DATA57 MEM_MA_DATA56 MEM_MA_DATA55 MEM_MA_DATA54 MEM_MA_DATA53 MEM_MA_DATA52 MEM_MA_DATA51 MEM_MA_DATA50 MEM_MA_DATA49 MEM_MA_DATA48 MEM_MA_DATA47 MEM_MA_DATA46 MEM_MA_DATA45 MEM_MA_DATA44 MEM_MA_DATA43 MEM_MA_DATA42 MEM_MA_DATA41 MEM_MA_DATA40 MEM_MA_DATA39 MEM_MA_DATA38 MEM_MA_DATA37 MEM_MA_DATA36 MEM_MA_DATA35 MEM_MA_DATA34 MEM_MA_DATA33 MEM_MA_DATA32 MEM_MA_DATA31 MEM_MA_DATA30 MEM_MA_DATA29 MEM_MA_DATA28 MEM_MA_DATA27 MEM_MA_DATA26 MEM_MA_DATA25 MEM_MA_DATA24 MEM_MA_DATA23 MEM_MA_DATA22 MEM_MA_DATA21 MEM_MA_DATA20 MEM_MA_DATA19 MEM_MA_DATA18 MEM_MA_DATA17 MEM_MA_DATA16 MEM_MA_DATA15 MEM_MA_DATA14 MEM_MA_DATA13 MEM_MA_DATA12 MEM_MA_DATA11 MEM_MA_DATA10 MEM_MA_DATA9 MEM_MA_DATA8 MEM_MA_DATA7 MEM_MA_DATA6 MEM_MA_DATA5 MEM_MA_DATA4 MEM_MA_DATA3 MEM_MA_DATA2 MEM_MA_DATA1 MEM_MA_DATA0
MEM_MA_CHECK7 MEM_MA_CHECK6 MEM_MA_CHECK5 MEM_MA_CHECK4 MEM_MA_CHECK3 MEM_MA_CHECK2 MEM_MA_CHECK1 MEM_MA_CHECK0
R672
R672
*
*
1K +/-5%
1K +/-5%
A1
MEM_MA_DATA[63..0] 10 MEM_MB_DATA[63..0] 11
MEM CHA
MEM_MB0_CLK0_P11
MEM_MB0_CLK0_N11
MEM_MB0_CLK1_P11
MEM_MB0_CLK1_N11
CPU
MEM_MB0_CS_L111 MEM_MB0_CS_L011
MEM_MB0_ODT111
TO DIMMA0 & DIMMA1
MEM CHB
CPU
TO DIMMB0 & DIMMB1
MEM_MA_DQS8_P 10 MEM_MA_DQS8_N 10
MEM_MA_DM8 10
MEM_MA_CHECK[7..0] 10
MEM_MA_EVENT_L 10
Layout: Route as 60 ohms with 5/10 W/S from CPU pins.
MEMORY CLOCK TRANSLATION
DIMM
DDR3 Memory Signal
DIMM A0
DIMM A1
DIMM B0
DIMM B1
MEM_MA0_CLK1
MEM_MA0_CLK0 MA_CLK4
MEM_MA1_CLK1 MA_CLK5
MEM_MA1_CLK0 MA_CLK3
MEM_MB0_CLK1 MB_CLK2
MEM_MB0_CLK0 MB_CLK4
MEM_MB1_CLK1 MB_CLK5
MEM_MB1_CLK0 MB_CLK3
A0 A1
B0 B1
CPU Signal
MA_CLK2
MEM_MB0_ODT011
MEM_MB_CAS#11
MEM_MB_WE#11
MEM_MB_RAS#11
MEM_MB_CKE111MEM_MA_CKE110 MEM_MB_CKE011
MEM_MB_DQS7_P11 MEM_MB_DQS7_N11 MEM_MB_DQS6_P11 MEM_MB_DQS6_N11 MEM_MB_DQS5_P11 MEM_MB_DQS5_N11 MEM_MB_DQS4_P11 MEM_MB_DQS4_N11 MEM_MB_DQS3_P11 MEM_MB_DQS3_N11 MEM_MB_DQS2_P11 MEM_MB_DQS2_N11 MEM_MB_DQS1_P11 MEM_MB_DQS1_N11 MEM_MB_DQS0_P11 MEM_MB_DQS0_N11
MEM_MB_BANK2 MEM_MB_BANK1 MEM_MB_BANK0
MEM_MB_ADD15 MEM_MB_ADD14 MEM_MB_ADD13 MEM_MB_ADD12 MEM_MB_ADD11 MEM_MB_ADD10 MEM_MB_ADD9 MEM_MB_ADD8 MEM_MB_ADD7 MEM_MB_ADD6 MEM_MB_ADD5 MEM_MB_ADD4 MEM_MB_ADD3 MEM_MB_ADD2 MEM_MB_ADD1 MEM_MB_ADD0
MEM_MB_DM7 MEM_MB_DM6 MEM_MB_DM5 MEM_MB_DM4 MEM_MB_DM3 MEM_MB_DM2 MEM_MB_DM1 MEM_MB_DM0
MB0 & MB_CKE0
CPU
TO DIMMB0
B0
AJ19
AK19 AL19 AL18
W29
W28
W31
AE30 AC31
AF31 AD29
AE29 AB31
AG31 AD31
AC29 AC30 AB29
AA31 AA28
AE31
AA29
AA30
AK13
AJ13 AK17
AJ17 AK23 AL23 AL28 AL29
AJ14 AH17
AJ23 AK29
U31 U30
Y31 Y30 V31
A18 A19 C19 D19
B19
N31
M31 M29
N28 N29
N30 P29
P31 R29 R28 R31 R30 T31 T29 U29 U28
D31 C31 C24 C23 D17 C17 C14 C13
C30 A23 B17 B13
U206C
U206C
MB_CLK_H7 MB_CLK_L7 MB_CLK_H6 MB_CLK_L6 MB_CLK_H5 MB_CLK_L5 MB_CLK_H4 MB_CLK_L4 MB_CLK_H3 MB_CLK_L3 MB_CLK_H2 MB_CLK_L2 MB_CLK_H1 MB_CLK_L1 MB_CLK_H0 MB_CLK_L0
MB0_CS_L1 MB0_CS_L0
MB0_ODT1 MB0_ODT0
MB1_CS_L1 MB1_CS_L0
MB1_ODT1 MB1_ODT0
MB_RESET_L
MB_CAS_L MB_WE_L MB_RAS_L
MB_BANK2 MB_BANK1 MB_BANK0
MB_CKE1 MB_CKE0
MB_ADD15 MB_ADD14 MB_ADD13 MB_ADD12 MB_ADD11 MB_ADD10 MB_ADD9 MB_ADD8 MB_ADD7 MB_ADD6 MB_ADD5 MB_ADD4 MB_ADD3 MB_ADD2 MB_ADD1 MB_ADD0
MB_DQS_H7 MB_DQS_L7 MB_DQS_H6 MB_DQS_L6 MB_DQS_H5 MB_DQS_L5 MB_DQS_H4 MB_DQS_L4 MB_DQS_H3 MB_DQS_L3 MB_DQS_H2 MB_DQS_L2 MB_DQS_H1 MB_DQS_L1 MB_DQS_H0 MB_DQS_L0
MB_DM7 MB_DM6 MB_DM5 MB_DM4 MB_DM3 MB_DM2 MB_DM1 MB_DM0
PZ94121-3126-01F
PZ94121-3126-01F
AH13
MB_DATA63
AL13
MB_DATA62
AL15
MB_DATA61
AJ15
MB_DATA60
AF13
MB_DATA59
AG13
MB_DATA58
AL14
MB_DATA57
AK15
MB_DATA56
AL16
MB_DATA55
AL17
MB_DATA54
AK21
MB_DATA53
AL21
MB_DATA52
AH15
MB_DATA51
AJ16
MB_DATA50
AH19
MB_DATA49
AL20
MB_DATA48
AJ22
MB_DATA47
AL22
MB_DATA46
AL24
MB_DATA45
AK25
MB_DATA44
AJ21
MB_DATA43
AH21
MB_DATA42
AH23
MB_DATA41
AJ24
MB_DATA40
AL27
MB_DATA39
AK27
MB_DATA38
AH31
MB_DATA37
AG30
MB_DATA36
AL25
MB_DATA35
AL26
MB_DATA34
AJ30
MB_DATA33
AJ31
MB_DATA32
E31
MB_DATA31
E30
MB_DATA30
B27
MB_DATA29
A27
MB_DATA28
F29
MB_DATA27
F31
MB_DATA26
A29
MB_DATA25
A28
MB_DATA24
A25
MB_DATA23
A24
MB_DATA22
C22
MB_DATA21
D21
MB_DATA20
A26
MB_DATA19
B25
MB_DATA18
B23
MB_DATA17
A22
MB_DATA16
B21
MB_DATA15
A20
MB_DATA14
C16
MB_DATA13
D15
MB_DATA12 MB_DATA11 MB_DATA10
MB_DATA9 MB_DATA8 MB_DATA7 MB_DATA6 MB_DATA5 MB_DATA4 MB_DATA3 MB_DATA2 MB_DATA1 MB_DATA0
MB_DQS_H8
MB_DQS_L8
MB_DM8
MB_CHECK7 MB_CHECK6 MB_CHECK5 MB_CHECK4 MB_CHECK3 MB_CHECK2 MB_CHECK1 MB_CHECK0
MB_EVENT_L
C21 A21 A17 A16 B15 A14 E13 F13 C15 A15 A13 D13
J31 J30
J29
K29 K31 G30 G29 L29 L28 H31 G31
V29
MEM_MB_CHECK7 MEM_MB_CHECK6 MEM_MB_CHECK5 MEM_MB_CHECK4 MEM_MB_CHECK3 MEM_MB_CHECK2 MEM_MB_CHECK1 MEM_MB_CHECK0
MEM CHB
MEM CHB
MB1 & MB_CKE1
CPU
TO DIMMB1
MEM_MB_DATA63 MEM_MB_DATA62 MEM_MB_DATA61 MEM_MB_DATA60 MEM_MB_DATA59 MEM_MB_DATA58 MEM_MB_DATA57 MEM_MB_DATA56 MEM_MB_DATA55 MEM_MB_DATA54 MEM_MB_DATA53 MEM_MB_DATA52 MEM_MB_DATA51 MEM_MB_DATA50 MEM_MB_DATA49 MEM_MB_DATA48 MEM_MB_DATA47 MEM_MB_DATA46 MEM_MB_DATA45 MEM_MB_DATA44 MEM_MB_DATA43 MEM_MB_DATA42 MEM_MB_DATA41 MEM_MB_DATA40 MEM_MB_DATA39 MEM_MB_DATA38 MEM_MB_DATA37 MEM_MB_DATA36 MEM_MB_DATA35 MEM_MB_DATA34 MEM_MB_DATA33 MEM_MB_DATA32 MEM_MB_DATA31 MEM_MB_DATA30 MEM_MB_DATA29 MEM_MB_DATA28 MEM_MB_DATA27 MEM_MB_DATA26 MEM_MB_DATA25 MEM_MB_DATA24 MEM_MB_DATA23 MEM_MB_DATA22 MEM_MB_DATA21 MEM_MB_DATA20 MEM_MB_DATA19 MEM_MB_DATA18 MEM_MB_DATA17 MEM_MB_DATA16 MEM_MB_DATA15 MEM_MB_DATA14 MEM_MB_DATA13 MEM_MB_DATA12 MEM_MB_DATA11 MEM_MB_DATA10
MEM_MB_DATA9 MEM_MB_DATA8 MEM_MB_DATA7 MEM_MB_DATA6 MEM_MB_DATA5 MEM_MB_DATA4 MEM_MB_DATA3 MEM_MB_DATA2 MEM_MB_DATA1 MEM_MB_DATA0
R677
R677
*
*
1K +/-5%
1K +/-5%
MEM_MB_DQS8_P 11
MEM_MB_DQS8_N 11
MEM_MB_DM8 11
MEM_MB_CHECK[7..0] 11
EVENT pins are for future AM3r2EVENT pins are for future AM3r2
MEM_MB_EVENT_L 11
1D5V_STR1D5V_STR
Layout: Route as 60 ohms with 5/10 W/S from CPU pins.
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
AM3- 2 DDR -1
AM3- 2 DDR -1
AM3- 2 DDR -1
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
FOXCONN PCEG
MCP61M07
MCP61M07
MCP61M07
7 35Saturday, December 04, 2010
7 35Saturday, December 04, 2010
7 35Saturday, December 04, 2010
1
AC
AC
AC
5
4
3
2
1
2D5V_VDDA CPU_VDDA_RUN
Layout: Keep trace to resistors
CPU_ALL_PWROK13 CPU_LDTSTOP_L13
D D
CPU_HT_RESET_L6,13
Less than 600mil to CPU
C509 3.9nF
CPU_CLKIN_H13
Less than 1250mil to CPU
CPU_CLKIN_L13
C C
*
*
R404 300 +/-5%*R404 300 +/-5%*R410 300 +/-5%*R410 300 +/-5%
R420 300 +/-5%*R420 300 +/-5%
C509 3.9nF
+/-10%
+/-10%
*
*
C510 3.9nF
C510 3.9nF
+/-10%
+/-10%
*
*
*
*
R409 300 +/-5%*R409 300 +/-5%
*
*
*
*
*
*
Dummy
Dummy
Dummy
Dummy
R416 300 +/-5%
R416 300 +/-5%
R415 300 +/-5%
R415 300 +/-5%
R397 300 +/-5%*R397 300 +/-5%
R400 300 +/-5%*R400 300 +/-5%
R399 300 +/-5%*R399 300 +/-5%
R402
R402
*
*
169 Ohm
169 Ohm
+/-1%
+/-1%
CPU_DBREQ#6
CPU_VDD_FB_H30 CPU_VDD_FB_L30
CPU_TEST20 CPU_TEST22 CPU_TEST24 CPU_M_ZN CPU_TEST12 CPU_TEST18_PLLTEST1 CPU_TEST19_PLLTEST0 CPU_TEST21_SCANEN CPU_TEST15_BP1 CPU_TEST14_BP0
less than 1" from CPU pins.
R421
R421
*
*
300
300
+/-5%
+/-5%
CPU_SIC18 CPU_SID18
CPU_TDI6
CPU_TRST#6
CPU_TCK6 CPU_TMS6
Layout: Keep trace to resistors less than 1" from CPU pins.
R423
R423
*
*
300
300
+/-5%
+/-5%
R426
R426
R425
R425
*
*
*
*
1K
1K
300
300
+/-5%
+/-5%
+/-5%
+/-5%
R544
R544 0 +/-5%
0 +/-5%
Dummy
Dummy
*
*
CPU_M_VREF_SUS
TP29TP29 TP30TP30
*
*
R401
R401 300
300
+/-5%
+/-5%
SA0_AM3
R405
R405
*
*
300
300
+/-5%
+/-5%
1D5V_STR
*
*
R408
R408
R406
R406
*
*
*
*
511 Ohm
511 Ohm
39.2
39.2
+/-1%
+/-1%
+/-1%
+/-1%
CPU_TEST25_H_BYPASSCLK_H
R403
R403
R411
R411
*
*
*
*
39.2
39.2
511 Ohm
511 Ohm
+/-1%
+/-1%
+/-1%
+/-1%
*
*
R393
R393 300
300
+/-5%
+/-5%
CPU_CLKIN_SC_P CPU_CLKIN_SC_N
CPU_PWRGD LDT_STOP# CPU_HT_RESET_L
CPU_SIC CPU_SID
CPU_ALERT#
CPU_TDI CPU_TRST# CPU_TCK CPU_TMS
CPU_DBREQ#
CPU_VDD_FB_H CPU_VDD_FB_L
CPU_M_ZP
CPU_TEST25_H_BYPASSCLK_L CPU_TEST19_PLLTEST0 CPU_TEST18_PLLTEST1
CPU_TEST17_BP3 CPU_TEST16_BP2 CPU_TEST15_BP1 CPU_TEST14_BP0 CPU_TEST12
C536
C536
22uF
22uF
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
CPU_VDDA_RUN
FB29
FB29
FB 30Ohm
FB 30Ohm
TP14TP14
21
C513
C513
*
*
*
*
4.7uF
4.7uF
Pin naming for VID pins indicate "Serial VID"/"Parallel VID" connections.
U206D
U206D
C10
VDDA_1
D10
VDDA_2
A8
CLKIN_H
B8
CLKIN_L
C9
PWROK
D8
LDTSTOP_L
C7
RESET_L
AL3
CPU_PRESENT_L
AL6
SIC
AK6
SID
AK4
SA0
AL4
ALERT_L
AL10
TDI
AJ10
TRST_L
AH10
TCK
AL9
TMS
A5
DBREQ_L
G2
VDD_FB_H
G1
VDD_FB_L
F3
M_VDDIO_PWRGD
E12
VDDR_SENSE
F12
M_VREF
AH11
M_ZN
AJ11
M_ZP
A10
TEST25_H
B10
TEST25_L
F10
TEST19
E9
TEST18
AJ7
TEST13
F6
TEST9
D6
TEST17
E7
TEST16
F8
TEST15
C5
TEST14
AH9
TEST12
E5
TEST7
AJ5
TEST6
AH7
TEST3
AJ6
TEST2
C18
RSVD1
C20
RSVD2
F2
RSVD3
G24
RSVD4
G25
RSVD5
INT. MISC.
INT. MISC.
H25
RSVD6
L25
RSVD7
L26
RSVD8
C508
C508
0.22uF
0.22uF
MISC.
MISC.
C537
C537
3.3nF
3.3nF
*
*
+/-10%
+/-10%
THERMTRIP_L
CPU Control and Miscellaneous
Layout: Keep CPU_HTREF0 less than 1.5" from in length.
CORE_TYPE
SVC/VID3 SVD/VID2
PVIEN/VID1
THERMDC THERMDA
PROCHOT_L
DBRDY
VDDIO_FB_H
VDDIO_FB_L VDDNB_FB_H VDDNB_FB_L
PSI_L
HTREF1 HTREF0
TEST29_H
TEST29_L
TEST24 TEST23 TEST22 TEST21 TEST20
TEST28_H
TEST28_L
TEST27 TEST26 TEST10
TEST8
RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16
G5
D2
VID5
D1
VID4
C1 E3 E2 E1
VID0
AG9 AG8 AK7 AL7
AK10
TDO
B6
AK11 AL11 G4 G3
F1
V8 V7
C11 D11
AK8 AH8 AJ9 AL8 AJ8
J10 H9 AK9 AK5 G7 D4
L30 L31 AD25 AE24 AE25 AJ18 AJ20 AK3
CPU_CORE_TYPE
CPU_VID5 CPU_VID4 CPU_SVC CPU_SVD CPU_PVEN CPU_VID0
CPU_THERMDC CPU_THERMDA CPU_THERMTRIP# CPU_PROCHOT#
CPU_TDO
CPU_DBRDY
CPU_VDDNB_FB_H CPU_VDDNB_FB_L
TP1TP1
CPU_HTREF1 CPU_HTREF0
CPU_TEST29_H_FBCLKOUT_H CPU_TEST29_L_FBCLKOUT_L
CPU_TEST24
CPU_TEST22 CPU_TEST21_SCANEN CPU_TEST20
CPU_TEST27 CPU_TEST26_BURNIN_L CPU_TEST10_ANALOGOUT CPU_TEST8_DIG_T
+1.2V_HT
R412
R412
*
*
44.2Ohm
44.2Ohm
+/-1%
+/-1%
R395
R395
*
*
44.2Ohm
44.2Ohm
+/-1%
+/-1%
TP7TP7 TP8TP8
1D5V_STR
R414
R414
*
*
*
*
300
300
300
+/-5%
+/-5%
R422
R422
CPU_TDO 6
300
+/-5%
+/-5%
R428
R428
CPU_STR_FB_H 29 CPU_STR_FB_L 29
R389
R389
80.6
80.6
+/-1%
+/-1%
1K
1K
+/-5%
+/-5%
CPU_THERMDC 24 CPU_THERMDA 24
Layout: Keep CPU_HTREF0 less than 1.5" from in length.
*
*
CPU_CORE_TYPE 30
CPU_VID5 30 CPU_VID4 30 CPU_SVC 30 CPU_SVD 30 CPU_PVEN 30 CPU_VID0 30
CPU_THERMTRIP* 13
+/-5%
+/-5%
R407 0
R407 0
*
*
CPU_DBRDY 6
CPU_VDDNB_FB_H 30 CPU_VDDNB_FB_L 30
Layout: Route as 80 ohms diff impedance. Keep trace to resistor < 1" from CPU pins.
CPU_PROCHOT_L_1.8 13
+/-5%
+/-5%
R424
CPU_TEST27
CPU_TEST26_BURNIN_L
R424
1D5V_STR
*
*
300
300
+/-5%
+/-5%
R398
R398
*
*
300
300
PZ94121-3126-01F
B B
1D5V_STR
R390
R390
*
*
1K
1K
Dummy
Dummy
+/-5%
+/-5%
CPU_ALERT#
PZ94121-3126-01F
CPU_M_VREF_SUS
1D5V_STR
CPU_M_VREF_SUS
R391
A A
5
4
R391
*
*
15
15
+/-1%
+/-1%
C512
*
*
C511
C511
0.1uF
0.1uF
C512
1nF
1nF
*
*
50V, X7R, +/-10%
50V, X7R, +/-10%
Layout: Place within 500 mils of the CPU socket.
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
AM3- 3 MISC
AM3- 3 MISC
AM3- 3 MISC
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
FOXCONN PCEG
MCP61M07
MCP61M07
MCP61M07
1
8 35Saturday, December 04, 2010
8 35Saturday, December 04, 2010
8 35Saturday, December 04, 2010
AC
AC
AC
of
of
of
R394
R394
*
*
15
15
+/-1%
+/-1%
3
5
4
3
2
1
VCCP_CPU
U206E
U206E
B3
VDD_1
C2
VDD_2
C4
VDD_3
D3
VDD_4
D5
VDD_5
E4
VDD_6
E6
VDD_7
D D
C C
B B
F5
F7 G6 G8 H7
H11 H23
J8
J12 J14 J16 J18 J20 J22 J24
K7
K9
K11 K13 K15 K17 K19 K21 K23
L4
L5
L8
L10 L12 L14 L16 L18 L20 L22
M2 M3 M7 M9
M11 M13 M15 M17 M19 M21 M23
N8
N10 N12 N14 N16 N18 N20 N22
P7
P9
P11 P13 P15 P17 P19 P21 P23
R4 R5 R8
R10 R12 R14 R16 R18 R20 R22
T2
T3
T7
T9
T11 T13
VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23 VDD_24 VDD_25 VDD_26 VDD_27 VDD_28 VDD_29 VDD_30 VDD_31 VDD_32 VDD_33 VDD_34 VDD_35 VDD_36 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43 VDD_44 VDD_45 VDD_46 VDD_47 VDD_48 VDD_49 VDD_50 VDD_51 VDD_52 VDD_53 VDD_54 VDD_55 VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62 VDD_63 VDD_64 VDD_65 VDD_66 VDD_67 VDD_68 VDD_69 VDD_70 VDD_71 VDD_72 VDD_73 VDD_74 VDD_75 VDD_76 VDD_77 VDD_78 VDD_79 VDD_80 VDD_81 VDD_82 VDD_83 VDD_84 VDD_85
PZ94121-3126-01F
PZ94121-3126-01F
A3
VSS_1
A7
VSS_2
A9
VSS_3
A11
VSS_4
B4
VSS_5
B9
VSS_6
B11
VSS_7
B14
VSS_8
B16
VSS_9
B18
VSS_10
B20
VSS_11
B22
VSS_12
B24
VSS_13
B26
VSS_14
B28
VSS_15
B30
VSS_16
C3
VSS_17
D14
VSS_18
D16
VSS_19
D18
VSS_20
D20
VSS_21
D22
VSS_22
D24
VSS_23
D26
VSS_24
D28
VSS_25
D30
VSS_26
E11
VSS_27
F4
VSS_28
F14
VSS_29
F16
VSS_30
F18
VSS_31
F20
VSS_32
F22
VSS_33
F24
VSS_34
F26
VSS_35
F28
VSS_36
F30
VSS_37
G9
VSS_38
G11
VSS_39
H8
VSS_40
H10
VSS_41
H12
VSS_42
H14
VSS_43
H16
VSS_44
H18
VSS_45
H24
VSS_46
H26
VSS_47
H28
VSS_48
H30
VSS_49
J4
VSS_50
J5
POWER/GND1
POWER/GND1
VSS_51
J7
VSS_52
J9
VSS_53
J11
VSS_54
J13
VSS_55
J15
VSS_56
J17
VSS_57
J19
VSS_58
J21
VSS_59
J23
VSS_60
K2
VSS_61
K3
VSS_62
K8
VSS_63
K10
VSS_64
K12
VSS_65
K14
VSS_66
K16
VSS_67
K18
VSS_68
K20
VSS_69
K22
VSS_70
K24
VSS_71
K26
VSS_72
K28
VSS_73
K30
VSS_74
L7
VSS_75
L9
VSS_76
L11
VSS_77
L13
VSS_78
L15
VSS_79
L17
VSS_80
L19
VSS_81
L21
VSS_82
L23
VSS_83
M8
VSS_84
M10
VSS_85
Bottom Side Decoupling
1D5V_STR
*
*
*
*
*
*
10uF
10uF
C772
C772
C766
C766
+/-10%
+/-10%
VCCP_CPU
*
*
*
C750
Dummy*C750
Dummy
22uF
22uF
A A
VCCP_CPU
*
*
VCCP_NB
*
*
C731
C731
C738
C738
10uF
10uF
*
*
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
c0805h14
c0805h14
*
*
22uF
22uF
C742
C742
*
*
10uF
10uF
C770
C770
+/-10%
+/-10%
*
*
C757
C757
Dummy
Dummy
22uF
22uF
C728
C728
10uF
10uF
*
*
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
c0805h14
c0805h14
*
*
22uF
22uF
5
*
10uF
10uF
C764
C764
+/-10%
+/-10%
C758
C758
*
*
22uF
22uF
C725
C725
10uF
10uF
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
c0805h14
c0805h14
C723
C723
10nF
10nF
*
*
*
10uF
10uF
C765
C765
+/-10%
+/-10%
C760
C760
*
*
*
*
C759
C759
Dummy
Dummy
22uF
22uF 22uF
22uF
VCCP_CPU VCCP_NBVCCP_CPU
C730
C730
10nF
10nF
*
*
10nF
10nF
C771
C771
C737
C737
C749
C749
*
*
22uF
22uF
22uF
22uF
C762 2.2uF
C762 2.2uF
*
*
C768 2.2uF
C768 2.2uF
*
*
VCCP_CPU
*
*
10nF
10nF
C769
C769
*
*
Dummy
Dummy
*
*
C741
C741
1D5V_STR
C753
C753
22uF
22uF
0.22uF
0.22uF
4.7uF
4.7uF
AA10 AA12 AA14 AA16 AA18 AA20 AA22
AB11 AB13 AB15 AB17 AB19 AB21 AB23
AC10 AC12 AC14 AC16 AC18 AC20 AC22
AD11 AD23 AE10 AE12
AF11
T15 T17 T19 T21 T23
U10 U12 U14 U16 U18 U20 U22
V11 V13 V15 V17 V19 V21 V23 W4 W5
W8 W10 W12 W14 W16 W18 W20 W22
Y11
Y13
Y15
Y17
Y19
Y21
Y23
AA8
AB7
AB9
AC4 AC5 AC8
AD2 AD3 AD7 AD9
AF7
AF9
AG4 AG5 AG7 AH2 AH3
C767
C767
C739
C739
U8
V9
Y2 Y3 Y7 Y9
*
*
*
*
Dummy
Dummy
*
*
EMC
U206F
U206F
VDD_86 VDD_87 VDD_88 VDD_89 VDD_90 VDD_91 VDD_92 VDD_93 VDD_94 VDD_95 VDD_96 VDD_97 VDD_98 VDD_99 VDD_100 VDD_101 VDD_102 VDD_103 VDD_104 VDD_105 VDD_106 VDD_107 VDD_108 VDD_109 VDD_110 VDD_111 VDD_112 VDD_113 VDD_114 VDD_115 VDD_116 VDD_117 VDD_118 VDD_119 VDD_120 VDD_121 VDD_122 VDD_123 VDD_124 VDD_125 VDD_126 VDD_127 VDD_128 VDD_129 VDD_130 VDD_131 VDD_132 VDD_133 VDD_134 VDD_135 VDD_136 VDD_137 VDD_138 VDD_139 VDD_140 VDD_141 VDD_142 VDD_143 VDD_144 VDD_145 VDD_146 VDD_147 VDD_148 VDD_149 VDD_150 VDD_151 VDD_152 VDD_153 VDD_154 VDD_155 VDD_156 VDD_157 VDD_158 VDD_159 VDD_160 VDD_161 VDD_162 VDD_163 VDD_164 VDD_165 VDD_166 VDD_167 VDD_168 VDD_169 VDD_170
PZ94121-3126-01F
PZ94121-3126-01F
C763
C763
180pF
180pF
*
*
50V, NPO, +/-5%
50V, NPO, +/-5%
0.22uF
0.22uF
C736
C736
C752
C752
*
*
Dummy
Dummy
22uF
22uF
*
*
C740
C740
4.7uF
4.7uF
VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98
VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134
POWER/GND2
POWER/GND2
VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170
C754
C754
C751
C751
*
*
0.22uF
0.22uF
22uF
22uF
22uF
22uF
C748
C748
10nF
10nF
*
*
*
*
10nF
10nF
C761
C761
4.7uF
4.7uF
C743 2.2uF
C743 2.2uF
*
*
M12 M14 M16 M18 M20 M22 N4 N5 N7 N9 N11 N13 N15 N17 N19 N21 N23 P2 P3 P8 P10 P12 P14 P16 P18 P20 P22 R7 R9 R11 R13 R15 R17 R19 R21 R23 T8 T10 T12 T14 T16 T18 T20 T22 U4 U5 U7 U9 U11 U13 U15 U17 U19 U21 U23 V2 V3 V10 V12 V14 V16 V18 V20 V22 W7 W9 W11 W13 W15 W17 W19 W21 W23 Y8 Y10 Y12 Y14 Y16 Y18 Y20 Y22 AA4 AA5 AA7 AA9
C726
C726
0.22uF
0.22uF
C727
C727
180pF
180pF
*
*
50V, NPO, +/-5%
50V, NPO, +/-5%
4
VCCP_NB
Processor Power and Ground
U206G
U206G
A4
VDDNB_1
A6
VDDNB_2
B5
VDDNB_3
B7
VDDNB_4
C6
VDDNB_5
C8
VDDNB_6
D7
VDDNB_7
D9
VDDNB_8
E8
VDDNB_9
E10
VDDNB_10
F9
VDDNB_11
F11
VDDNB_12
G10
VDDNB_13
G12
VDDNB_14
B2
NP/RSVD
H20
NP/VSS1
AE7
NP/VSS2
PZ94121-3126-01F
PZ94121-3126-01F
VCCP_NB VDDR_R
VCCP_NB
C546
C546
C541
C541
10uF
10uF
10uF
10uF
*
*
*
*
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
c0805h14
c0805h14
c0805h14
c0805h14
+1.2V_HT
*
*
*
*
C539
C539
C605
C605
4.7uF
4.7uF
4.7uF
4.7uF
VLDT_HT3_RUN
VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201
POWER/GND3
POWER/GND3
VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214
C553
C553
*
*
C548
C548
4.7uF
4.7uF
0.22uF
0.22uF
C585
C585
C576
C576
0.22uF
0.22uF
0.22uF
0.22uF
C587
C587
0.22uF
0.22uF
180pF
180pF
C586
C586
+1.2V_HT
U206H
U206H
VDDR_L
1D5V_STR
C545
C545
10uF
10uF
*
*
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
c0805h14
c0805h14
*
*
AB24 AB26 AB28 AB30 AC24 AD26 AD28 AD30
AF30
AJ1 AJ2 AJ3 AJ4
A12 B12 C12 D12
M24 M26 M28 M30 P24 P26 P28 P30 T24 T26 T28 T30 V25 V26 V28 V30 Y24 Y26 Y28 Y29
C540
C540
4.7uF
4.7uF
VLDT_A_1 VLDT_A_2 VLDT_A_3 VLDT_A_4
VDDR_1 VDDR_2 VDDR_3 VDDR_4
VDDIO_1 VDDIO_2 VDDIO_3 VDDIO_4 VDDIO_5 VDDIO_6 VDDIO_7 VDDIO_8 VDDIO_9 VDDIO_10 VDDIO_11 VDDIO_12 VDDIO_13 VDDIO_14 VDDIO_15 VDDIO_16 VDDIO_17 VDDIO_18 VDDIO_19 VDDIO_20 VDDIO_21 VDDIO_22 VDDIO_23 VDDIO_24 VDDIO_25 VDDIO_26 VDDIO_27 VDDIO_28 VDDIO_29
PZ94121-3126-01F
PZ94121-3126-01F
C570
C570
*
*
C542
C542
4.7uF
4.7uF
POWER/GND4
POWER/GND4
C575
C575
C551
C551
0.22uF
0.22uF
0.22uF
0.22uF
AA11 AA13 AA15 AA17 AA19 AA21 AA23 AB2 AB3 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC7 AC9 AC11 AC13 AC15 AC17 AC19 AC21 AC23 AD8 AD10 AD12 AD14 AD16 AD20 AD22 AD24 AE4 AE5 AE11 AF2 AF3 AF8 AF10 AF12 AF14 AF16
VDDR_R
10nF
10nF
C550
C550
VLDT_B_1 VLDT_B_2 VLDT_B_3 VLDT_B_4
*
*
0.22uF
0.22uF
VDDR_5 VDDR_6 VDDR_7 VDDR_8 VDDR_9
VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242
C661
C661
4.7uF
4.7uF
H1 H2 H5 H6
AG12 AH12 AJ12 AK12 AL12
AF18 AF20 AF22 AF24 AF26 AF28 AG10 AG11 AH14 AH16 AH18 AH20 AH22 AH24 AH26 AH28 AH30 AK2 AK14 AK16 AK18 AK20 AK22 AK24 AK26 AK28 AK30 AL5
VLDT_HT3_RUN_B
VDDR_R
+1.2V_HT
CP18
CP18
12
X_COPPER
X_COPPER
CP19
CP19
12
X_COPPER
X_COPPER
Layout: Place as close as possible to CPU socket.
*
*
C594
C594
4.7uF
4.7uF
CPU
1D5V_STR
A1
AM3
Top View
AL1
VDDR_L
180pF
180pF
C581
C581
*
*
Dummy
Dummy
C544
C544
4.7uF
4.7uF
A31
AL31
*
*
C547
C547
4.7uF
4.7uF
1D5V_STR
1D5V_STR
Layout: Place across each VDDIO-GND plane split.
C543
C543
10uF
10uF
C592
C592
*
*
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
10nF
10nF
C549
C549
c0805h14
c0805h14
C593
C593
2.2uF
2.2uF
*
*
*
*
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
C600
C600
2.2uF
2.2uF
*
*
*
*
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
*
*
C658
C658
4.7uF
4.7uF
0.22uF
0.22uF
C598
C598
2.2uF
2.2uF
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
180pF
180pF
C591
C591
C538
C538
2.2uF
2.2uF
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
180pF
180pF
C556
C556
DIMMs
VTT_DDR
VTT_DDR
*
*
*
*
*
*
C657
C657
4.7uF
4.7uF
Layout: Place behind the DIMMs, evenly spaced on VTT fill.
C660
C660
4.7uF
4.7uF
C837
C837
4.7uF
4.7uF
*
*
C838
C838
4.7uF
4.7uF
VTT_DDR
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
AM3- 4 Power
AM3- 4 Power
AM3- 4 Power
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
3
2
Date: Sheet
FOXCONN PCEG
MCP61M07
MCP61M07
MCP61M07
1
AC
AC
AC
of
of
of
9 35Friday, December 03, 2010
9 35Friday, December 03, 2010
9 35Friday, December 03, 2010
5
DIMM1
DIMM1
198
FREE4
1D5V_STR
VDD_SPD
187
FREE3
49
FREE2
48
FREE1
240
VTT
120
VTT
239
VSS
235
VSS
232
VSS
229
VSS
226
VSS
223
VSS
220
VSS
217
VSS
214
VSS
211
VSS
208
VSS
205
VSS
202
VSS
199
VSS
166
VSS
163
VSS
160
VSS
157
VSS
154
VSS
151
VSS
148
VSS
145
VSS
142
VSS
139
VSS
136
VSS
133
VSS
130
VSS
127
VSS
124
VSS
121
VSS
119
VSS
116
VSS
113
VSS
110
VSS
107
VSS
104
VSS
101
VSS
98
VSS
95
VSS
92
VSS
89
VSS
86
VSS
83
VSS
80
VSS
47
VSS
44
VSS
41
VSS
38
VSS
35
VSS
32
VSS
29
VSS
26
VSS
23
VSS
20
VSS
17
VSS
14
VSS
11
VSS
8
VSS
5
VSS
2
VSS
197
VDDQ
194
VDDQ
191
VDDQ
189
VDDQ
186
VDDQ
183
VDDQ
182
VDDQ
179
VDDQ
176
VDDQ
173
VDDQ
170
VDDQ
78
VDD
75
VDD
72
VDD
69
VDD
66
VDD
65
VDD
62
VDD
60
VDD
57
VDD
54
VDD
51
VDD
236
VDDSPD
67
VREFCA
1
VREFDQ
118
SCL
238
SDA
237
SA1
117
SA0
52
BA2
190
BA1
71
BA0
169
CKE1
50
CKE0
76
S1*
193
S0*
64
CK1/NU*
63
CK1/NU
185
CK0*
184
CK0
188
A0
181
A1
61
A2
180
A3
59
A4
58
A5
178
A6
56
A7
177
A8
175
A9
70
A10/AP
55
A11
174
A12
196
A13
172
A14
171
A15
168
RESET*
74
CAS*
192
RAS*
73
WE*
DDR III
DDR III
MEM_MA_EVENT_L7
VTT_DDR
D D
MEM_VREFDQ_SUS
1D5V_STR MEM_VREFDQ_SUS
R674
R674
*
*
15
15
+/-1%
+/-1%
R673
R673
*
*
15
15
+/-1%
+/-1%
C832
C832
0.1uF
0.1uF
*
*
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
Dummy
Dummy
C836
C836
C830
C830
1nF
1nF
*
*
*
*
0.1uF
0.1uF
50V, X7R, +/-10%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
50V, X7R, +/-10%
Layout: Place within 500 mils of the DIMMB1 socket.
MEM_VREFCA_SUS
C C
1D5V_STR MEM_VREFCA_SUS
C834
*
*
*
*
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
Layout: Place within 500 mils of the DIMMB1 socket.
R445 0 +/-5%
R445 0 +/-5%
*
*
MEM_MA_BANK[2..0]7
C834
0.1uF
0.1uF
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
Dummy
Dummy
C835
C835
1nF
1nF
C833
C833
*
*
0.1uF
0.1uF
50V, X7R, +/-10%
50V, X7R, +/-10%
VDD_SPD
MEM_MA_ADD[15..0]
5
VDD_SPD 11
SMB_MEM_SCL11,18
SMB_MEM_SDA11,18
MEM_MA_BANK[2..0]
MEM_MA_CKE17 MEM_MA_CKE07
MEM_MA0_CS_L17 MEM_MA0_CS_L07
MEM_MA0_CLK1_N7
MEM_MA0_CLK1_P7
MEM_MA0_CLK0_N7
MEM_MA0_CLK0_P7
MEM_MA_RESET#7 MEM_MA_CAS#7 MEM_MA_RAS#7
MEM_MA_WE#7
MEM_VREFCA_SUS MEM_VREFDQ_SUS
MEM_MA_BANK2 MEM_MA_BANK1 MEM_MA_BANK0
MEM_MA_ADD0 MEM_MA_ADD1 MEM_MA_ADD2 MEM_MA_ADD3 MEM_MA_ADD4 MEM_MA_ADD5 MEM_MA_ADD6 MEM_MA_ADD7 MEM_MA_ADD8 MEM_MA_ADD9 MEM_MA_ADD10 MEM_MA_ADD11 MEM_MA_ADD12 MEM_MA_ADD13 MEM_MA_ADD14 MEM_MA_ADD15
R676
R676
*
*
15
15
+/-1%
+/-1%
R675
R675
*
*
15
15
+/-1%
+/-1%
+3.3V
B B
MEM_MA_ADD[15..0]7
A A
4
79
RSVD
77
ODT1
195
ODT0
68
NC/PAR_IN
53
NC/ERR_OUT
167
NC/TEST4
39
CB<0>
40
CB<1>
45
CB<2>
46
CB<3>
158
CB<4>
159
CB<5>
164
CB<6>
165
CB<7>
7
DQS<0>
6
DQS*<0>
16
DQS<1>
15
DQS*<1>
25
DQS<2>
24
DQS*<2>
34
DQS<3>
33
DQS*<3>
85
DQS<4>
84
DQS*<4>
94
DQS<5>
93
DQS*<5>
103
DQS<6>
102
DQS*<6>
112
DQS<7>
111
DQS*<7>
43
DQS<8>
42
DQS*<8>
125
DM0/DQS9
126
DQS9*
134
DM1/DQS10
135
DQS10*
143
DM2/DQS11
144
DQS11*
152
DM3/DQS12
153
DQS12*
203
DM4/DQS13
204
DQS13*
212
DM5/DQS14
213
DQS14*
221
DM6/DQS15
222
DQS15*
230
DM7/DQS16
231
NC/DQS16*
161
DM8/DQS17
162
DQS17*
3
DQ<0>
4
DQ<1> DQ<2> DQ<3> DQ<4> DQ<5> DQ<6> DQ<7> DQ<8>
DQ<9> DQ<10> DQ<11> DQ<12> DQ<13> DQ<14> DQ<15> DQ<16> DQ<17> DQ<18> DQ<19> DQ<20> DQ<21> DQ<22> DQ<23> DQ<24> DQ<25> DQ<26> DQ<27> DQ<28> DQ<29> DQ<30> DQ<31> DQ<32> DQ<33> DQ<34> DQ<35> DQ<36> DQ<37> DQ<38> DQ<39> DQ<40> DQ<41> DQ<42> DQ<43> DQ<44> DQ<45> DQ<46> DQ<47> DQ<48> DQ<49> DQ<50> DQ<51> DQ<52> DQ<53> DQ<54> DQ<55> DQ<56> DQ<57> DQ<58> DQ<59> DQ<60> DQ<61> DQ<62> DQ<63>
4
9 10 122 123 128 129 12 13 18 19 131 132 137 138 21 22 27 28 140 141 146 147 30 31 36 37 149 150 155 156 81 82 87 88 200 201 206 207 90 91 96 97 209 210 215 216 99 100 105 106 218 219 224 225 108 109 114 115 227 228 233 234
DDRIII
DDRIII
MEM_MA_CHECK0 MEM_MA_CHECK1 MEM_MA_CHECK2 MEM_MA_CHECK3 MEM_MA_CHECK4 MEM_MA_CHECK5 MEM_MA_CHECK6 MEM_MA_CHECK7
MEM_MA_DQS0_P 7 MEM_MA_DQS0_N 7
MEM_MA_DQS1_P 7 MEM_MA_DQS1_N 7
MEM_MA_DQS2_P 7 MEM_MA_DQS2_N 7
MEM_MA_DQS3_P 7 MEM_MA_DQS3_N 7
MEM_MA_DQS4_P 7 MEM_MA_DQS4_N 7
MEM_MA_DQS5_P 7 MEM_MA_DQS5_N 7
MEM_MA_DQS6_P 7 MEM_MA_DQS6_N 7
MEM_MA_DQS7_P 7 MEM_MA_DQS7_N 7
MEM_MA_DQS8_P 7 MEM_MA_DQS8_N 7
MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7
MEM_MA_DM8
MEM_MA_DATA0 MEM_MA_DATA1 MEM_MA_DATA2 MEM_MA_DATA3 MEM_MA_DATA4 MEM_MA_DATA5 MEM_MA_DATA6 MEM_MA_DATA7 MEM_MA_DATA8 MEM_MA_DATA9 MEM_MA_DATA10 MEM_MA_DATA11 MEM_MA_DATA12 MEM_MA_DATA13 MEM_MA_DATA14 MEM_MA_DATA15 MEM_MA_DATA16 MEM_MA_DATA17 MEM_MA_DATA18 MEM_MA_DATA19 MEM_MA_DATA20 MEM_MA_DATA21 MEM_MA_DATA22 MEM_MA_DATA23 MEM_MA_DATA24 MEM_MA_DATA25 MEM_MA_DATA26 MEM_MA_DATA27 MEM_MA_DATA28 MEM_MA_DATA29 MEM_MA_DATA30 MEM_MA_DATA31 MEM_MA_DATA32 MEM_MA_DATA33 MEM_MA_DATA34 MEM_MA_DATA35 MEM_MA_DATA36 MEM_MA_DATA37 MEM_MA_DATA38 MEM_MA_DATA39 MEM_MA_DATA40 MEM_MA_DATA41 MEM_MA_DATA42 MEM_MA_DATA43 MEM_MA_DATA44 MEM_MA_DATA45 MEM_MA_DATA46 MEM_MA_DATA47 MEM_MA_DATA48 MEM_MA_DATA49 MEM_MA_DATA50 MEM_MA_DATA51 MEM_MA_DATA52 MEM_MA_DATA53 MEM_MA_DATA54 MEM_MA_DATA55 MEM_MA_DATA56 MEM_MA_DATA57 MEM_MA_DATA58 MEM_MA_DATA59 MEM_MA_DATA60 MEM_MA_DATA61 MEM_MA_DATA62 MEM_MA_DATA63
MEM_MA0_ODT1 7 MEM_MA0_ODT0 7
MEM_MA_CHECK[7..0] 7
MEM_MA_DM[7..0]
MEM_MA_DM8 7
MEM_MA_DATA[63..0]
MEM_MA_DM[7..0] 7
MEM_MA_DATA[63..0] 7
3
2
1
SMBus Addressing
Device
DIMMA0
DIMMB0
DIMMA1
DIMMB1
Title
Title
Title
DDR SDRAM DIMM 1
DDR SDRAM DIMM 1
DDR SDRAM DIMM 1
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
3
2
Date: Sheet
SMBus 0
8-bit Address (hex)
A0
A2
A4
A6
FOXCONN PCEG
FOXCONN PCEG
FOXCONN PCEG
MCP61M07
MCP61M07
MCP61M07
1
10 35Saturday, December 04, 2010
10 35Saturday, December 04, 2010
10 35Saturday, December 04, 2010
AC
AC
AC
of
of
of
5
MEM_MB_EVENT_L7
VTT_DDR
D D
C C
1D5V_STR
MEM_MB_ADD[15..0]
5
MEM_VREFDQ_SUS
MEM_VREFCA_SUS
SMB_MEM_SCL10,18
SMB_MEM_SDA10,18
MEM_MB_BANK[2..0]
MEM_MB_CKE17 MEM_MB_CKE07
MEM_MB0_CS_L17 MEM_MB0_CS_L07
MEM_MB0_CLK1_N7
MEM_MB0_CLK1_P7
MEM_MB0_CLK0_N7
MEM_MB0_CLK0_P7
MEM_MB_RESET#7 MEM_MB_CAS#7 MEM_MB_RAS#7
MEM_MB_WE#7
VDD_SPD
MEM_VREFCA_SUS MEM_VREFDQ_SUS
+3.3V
MEM_MB_BANK2 MEM_MB_BANK1 MEM_MB_BANK0
MEM_MB_ADD0 MEM_MB_ADD1 MEM_MB_ADD2 MEM_MB_ADD3 MEM_MB_ADD4 MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7 MEM_MB_ADD8 MEM_MB_ADD9 MEM_MB_ADD10 MEM_MB_ADD11 MEM_MB_ADD12 MEM_MB_ADD13 MEM_MB_ADD14 MEM_MB_ADD15
B B
MEM_MB_BANK[2..0]7
MEM_MB_ADD[15..0]7
A A
VDD_SPD10
VDD_SPD
DIMM2
DIMM2
198
FREE4
187
FREE3
49
FREE2
48
FREE1
240
VTT
120
VTT
239
VSS
235
VSS
232
VSS
229
VSS
226
VSS
223
VSS
220
VSS
217
VSS
214
VSS
211
VSS
208
VSS
205
VSS
202
VSS
199
VSS
166
VSS
163
VSS
160
VSS
157
VSS
154
VSS
151
VSS
148
VSS
145
VSS
142
VSS
139
VSS
136
VSS
133
VSS
130
VSS
127
VSS
124
VSS
121
VSS
119
VSS
116
VSS
113
VSS
110
VSS
107
VSS
104
VSS
101
VSS
98
VSS
95
VSS
92
VSS
89
VSS
86
VSS
83
VSS
80
VSS
47
VSS
44
VSS
41
VSS
38
VSS
35
VSS
32
VSS
29
VSS
26
VSS
23
VSS
20
VSS
17
VSS
14
VSS
11
VSS
8
VSS
5
VSS
2
VSS
197
VDDQ
194
VDDQ
191
VDDQ
189
VDDQ
186
VDDQ
183
VDDQ
182
VDDQ
179
VDDQ
176
VDDQ
173
VDDQ
170
VDDQ
78
VDD
75
VDD
72
VDD
69
VDD
66
VDD
65
VDD
62
VDD
60
VDD
57
VDD
54
VDD
51
VDD
236
VDDSPD
67
VREFCA
1
VREFDQ
118
SCL
238
SDA
237
SA1
117
SA0
52
BA2
190
BA1
71
BA0
169
CKE1
50
CKE0
76
S1*
193
S0*
64
CK1/NU*
63
CK1/NU
185
CK0*
184
CK0
188
A0
181
A1
61
A2
180
A3
59
A4
58
A5
178
A6
56
A7
177
A8
175
A9
70
A10/AP
55
A11
174
A12
196
A13
172
A14
171
A15
168
RESET*
74
CAS*
192
RAS*
73
WE*
DDR III
DDR III
4
79
RSVD
77
ODT1
195
ODT0
68
NC/PAR_IN
53
NC/ERR_OUT
167
NC/TEST4
39
CB<0>
40
CB<1>
45
CB<2>
46
CB<3>
158
CB<4>
159
CB<5>
164
CB<6>
165
CB<7>
7
DQS<0>
6
DQS*<0>
16
DQS<1>
15
DQS*<1>
25
DQS<2>
24
DQS*<2>
34
DQS<3>
33
DQS*<3>
85
DQS<4>
84
DQS*<4>
94
DQS<5>
93
DQS*<5>
103
DQS<6>
102
DQS*<6>
112
DQS<7>
111
DQS*<7>
43
DQS<8>
42
DQS*<8>
125
DM0/DQS9
126
DQS9*
134
DM1/DQS10
135
DQS10*
143
DM2/DQS11
144
DQS11*
152
DM3/DQS12
153
DQS12*
203
DM4/DQS13
204
DQS13*
212
DM5/DQS14
213
DQS14*
221
DM6/DQS15
222
DQS15*
230
DM7/DQS16
231
NC/DQS16*
161
DM8/DQS17
162
DQS17*
3
DQ<0>
4
DQ<1> DQ<2> DQ<3> DQ<4> DQ<5> DQ<6> DQ<7> DQ<8>
DQ<9> DQ<10> DQ<11> DQ<12> DQ<13> DQ<14> DQ<15> DQ<16> DQ<17> DQ<18> DQ<19> DQ<20> DQ<21> DQ<22> DQ<23> DQ<24> DQ<25> DQ<26> DQ<27> DQ<28> DQ<29> DQ<30> DQ<31> DQ<32> DQ<33> DQ<34> DQ<35> DQ<36> DQ<37> DQ<38> DQ<39> DQ<40> DQ<41> DQ<42> DQ<43> DQ<44> DQ<45> DQ<46> DQ<47> DQ<48> DQ<49> DQ<50> DQ<51> DQ<52> DQ<53> DQ<54> DQ<55> DQ<56> DQ<57> DQ<58> DQ<59> DQ<60> DQ<61> DQ<62> DQ<63>
9 10 122 123 128 129 12 13 18 19 131 132 137 138 21 22 27 28 140 141 146 147 30 31 36 37 149 150 155 156 81 82 87 88 200 201 206 207 90 91 96 97 209 210 215 216 99 100 105 106 218 219 224 225 108 109 114 115 227 228 233 234
DDRIII
DDRIII
4
MEM_MB_CHECK0 MEM_MB_CHECK1 MEM_MB_CHECK2 MEM_MB_CHECK3 MEM_MB_CHECK4 MEM_MB_CHECK5 MEM_MB_CHECK6 MEM_MB_CHECK7
MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7
MEM_MB_DM8
MEM_MB_DATA0 MEM_MB_DATA1 MEM_MB_DATA2 MEM_MB_DATA3 MEM_MB_DATA4 MEM_MB_DATA5 MEM_MB_DATA6 MEM_MB_DATA7 MEM_MB_DATA8 MEM_MB_DATA9 MEM_MB_DATA10 MEM_MB_DATA11 MEM_MB_DATA12 MEM_MB_DATA13 MEM_MB_DATA14 MEM_MB_DATA15 MEM_MB_DATA16 MEM_MB_DATA17 MEM_MB_DATA18 MEM_MB_DATA19 MEM_MB_DATA20 MEM_MB_DATA21 MEM_MB_DATA22 MEM_MB_DATA23 MEM_MB_DATA24 MEM_MB_DATA25 MEM_MB_DATA26 MEM_MB_DATA27 MEM_MB_DATA28 MEM_MB_DATA29 MEM_MB_DATA30 MEM_MB_DATA31 MEM_MB_DATA32 MEM_MB_DATA33 MEM_MB_DATA34 MEM_MB_DATA35 MEM_MB_DATA36 MEM_MB_DATA37 MEM_MB_DATA38 MEM_MB_DATA39 MEM_MB_DATA40 MEM_MB_DATA41 MEM_MB_DATA42 MEM_MB_DATA43 MEM_MB_DATA44 MEM_MB_DATA45 MEM_MB_DATA46 MEM_MB_DATA47 MEM_MB_DATA48 MEM_MB_DATA49 MEM_MB_DATA50 MEM_MB_DATA51 MEM_MB_DATA52 MEM_MB_DATA53 MEM_MB_DATA54 MEM_MB_DATA55 MEM_MB_DATA56 MEM_MB_DATA57 MEM_MB_DATA58 MEM_MB_DATA59 MEM_MB_DATA60 MEM_MB_DATA61 MEM_MB_DATA62 MEM_MB_DATA63
MEM_MB0_ODT1 7 MEM_MB0_ODT0 7
MEM_MB_CHECK[7..0] 7
MEM_MB_DQS0_P 7 MEM_MB_DQS0_N 7
MEM_MB_DQS1_P 7 MEM_MB_DQS1_N 7
MEM_MB_DQS2_P 7 MEM_MB_DQS2_N 7
MEM_MB_DQS3_P 7 MEM_MB_DQS3_N 7
MEM_MB_DQS4_P 7 MEM_MB_DQS4_N 7
MEM_MB_DQS5_P 7 MEM_MB_DQS5_N 7
MEM_MB_DQS6_P 7 MEM_MB_DQS6_N 7
MEM_MB_DQS7_P 7 MEM_MB_DQS7_N 7
MEM_MB_DQS8_P 7 MEM_MB_DQS8_N 7
MEM_MB_DM8 7
MEM_MB_DATA[63..0]
MEM_MB_DM[7..0]
MEM_MB_DATA[63..0] 7
3
MEM_MB_DM[7..0] 7
3
2
Title
Title
Title
DDR SDRAM DIMM 2
DDR SDRAM DIMM 2
DDR SDRAM DIMM 2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
1
FOXCONN PCEG
FOXCONN PCEG
FOXCONN PCEG
MCP61M07
MCP61M07
MCP61M07
1
11 35Saturday, December 04, 2010
11 35Saturday, December 04, 2010
11 35Saturday, December 04, 2010
AC
AC
AC
of
of
of
5
D D
C601 10nF
C601 10nF
C608 0.1uF
C608 0.1uF
C618 0.1uF
C618 0.1uF
C619 0.1uF
EMI decoupling cap, place evenly around 1D8V_STR
C C
C619 0.1uF
C609 1uF
C609 1uF
C604 1uF
C604 1uF
C612 1uF
C612 1uF
C613 1uF
C613 1uF
C616 1uF
C616 1uF
C614 1uF
C614 1uF
C615 1uF
C615 1uF
C617 1uF
C617 1uF
4
*
*
12
1D5V_STR VTT_DDR
*
* *
* *
* *
* *
* *
* *
* *
* *
* *
* *
*
C610 1uF
C610 1uF
C611 1uF
C611 1uF
3
*
* *
*
2
1
B B
A A
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
DDR III terminator
DDR III terminator
DDR III terminator
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet of
FOXCONN PCEG
MCP61M07
MCP61M07
MCP61M07
1
12 35Saturday, December 04, 2010
12 35Saturday, December 04, 2010
12 35Saturday, December 04, 2010
AC
AC
AC
of
of
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