Each Fluke product is warranted to be free from defects in material and workmanship under normal use and
service. The warranty period is one year and begins on the date of shipment. Parts, product repairs, and
services are warranted for 90 days. This warranty extends only to the original buyer or end-user customer of
a Fluke authorized reseller, and does not apply to fuses, disposable batteries, or to any product which, in
Fluke's opinion, has been misused, altered, neglected, contaminated, or damaged by accident or abnormal
conditions of operation or handling. Fluke warrants that software will operate substantially in accordance
with its functional specifications for 90 days and that it has been properly recorded on non-defective media.
Fluke does not warrant that software will be error free or operate without interruption.
Fluke authorized resellers shall extend this warranty on new and unused products to end-user customers
only but have no authority to extend a greater or different warranty on behalf of Fluke. Warranty support is
available only if product is purchased through a Fluke authorized sales outlet or Buyer has paid the
applicable international price. Fluke reserves the right to invoice Buyer for importation costs of
repair/replacement parts when product purchased in one country is submitted for repair in another country.
Fluke's warranty obligation is limited, at Fluke's option, to refund of the purchase price, free of charge repair,
or replacement of a defective product which is returned to a Fluke authorized service center within the
warranty period.
To obtain warranty service, contact your nearest Fluke authorized service center to obtain return
authorization information, then send the product to that service center, with a description of the difficulty,
postage and insurance prepaid (FOB Destination). Fluke assumes no risk for damage in transit. Following
warranty repair, the product will be returned to Buyer, transportation prepaid (FOB Destination). If Fluke
determines that failure was caused by neglect, misuse, contamination, alteration, accident, or abnormal
condition of operation or handling, including overvoltage failures caused by use outside the product’s
specified rating, or normal wear and tear of mechanical components, Fluke will provide an estimate of repair
costs and obtain authorization before commencing the work. Following repair, the product will be returned to
the Buyer transportation prepaid and the Buyer will be billed for the repair and return transportation charges
(FOB Shipping Point).
THIS WARRANTY IS BUYER'S SOLE AND EXCLUSIVE REMEDY AND IS IN LIEU OF ALL OTHER
WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTY
OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. FLUKE SHALL NOT BE LIABLE
FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES OR LOSSES,
INCLUDING LOSS OF DATA, ARISING FROM ANY CAUSE OR THEORY.
Since some countries or states do not allow limitation of the term of an implied warranty, or exclusion or
limitation of incidental or consequential damages, the limitations and exclusions of this warranty may not
apply to every buyer. If any provision of this Warranty is held invalid or unenforceable by a court or other
decision-maker of competent jurisdiction, such holding will not affect the validity or enforceability of any other
provision.
Fluke Corporation
P.O. Box 9090
Everett, WA 98206-9090
U.S.A.
Fluke Europe B.V.
P.O. Box 1186
5602 BD Eindhoven
The Netherlands
11/99
To register your product online, visit register.fluke.com
Claims
Immediately upon arrival, purchaser shall check the packing container against the enclosed
packing list and shall, within thirty (30) days of arrival, give Fluke notice of shortages or any
nonconformity with the terms of the order. If purchaser fails to five notice, the delivery shall be
deemed to conform with the terms of the order.
The purchaser assumes all risk of loss or damage to instruments upon delivery by Fluke to the
carrier. If an instrument is damaged in transit, PURCHASER MUST FILE ALL CLAIMS FOR
DAMAGE WITH THE CARRIER to obtain compensation. Upon request by purchaser, Fluke will
submit an estimate of the cost to repair shipment damage.
Fluke will be happy to answer all questions to enhance the use of this instrument. Please address
your requests or correspondence to: Fluke Corporation, P.O. Box 9090, Everett, WA 98206-9090.
Interference Information
This equipment generates and uses radio frequency energy and if not installed and used in strict
accordance with the manufacturer’s instructions, may cause interference to radio and television
reception. It has been type tested and found to comply with the limits for a Class A computing
device in accordance with the specifications in Subpart J of Part 15 of FCC Rules, which are
designed to provide reasonable protection against such interference in a residential installation.
However, there is no guarantee that interference will not occur in a particular installation. If this
equipment does cause interference to radio or television reception, which can be determined by
turning the equipment off and on, the user is encouraged to try to correct the interference by one
of more of the following measures:
• Reorient the receiving antenna
• Relocate the equipment with respect to the receiver
• Move the equipment away from the receiver
• Plug the equipment into a different outlet so that the computer and receiver are on different
branch circuits
If necessary, the user should consult the dealer or an experienced radio/television technician for
additional suggestions. The user may find the following booklet prepared by the Federal
Communications Commission helpful: How to Identify and Resolve Radio-TV Interference
Problems. This booklet is available from the U.S. Government Printing Office, Washington, D.C.
20402. Stock No. 004-000-00345-4.
OPERATOR SAFETY
SUMMARY
XWWARNING
HIGH VOLTAGE
is used in the operation of this equipment
LETHAL VOLTAGE
may be present on the terminals, observe all safety precautions!
To avoid electrical shock hazard, the operator should not
electrically contact the output hi or sense hi binding posts.
During operation, lethal voltages of up to 2200 V ac or dc may
be present on these terminals.
Whenever the nature of the operation permits, keep one hand
away from equipment to reduce the hazard of current flowing
thought vital organs of the body.
Terms in this Manual
This instrument has been designed and tested in accordance with the safety standards listed in
the General Specifications, which are located in Chapter 1 of this manual. This manual contains
information and warnings which have to be followed by the user to ensure safe operation and to
retain the instrument in safe condition.
XWWARNING statements identify conditions or practices that could result in personal injury or
loss of life.
XWCAUTION statements identify conditions or practices that could result in damage to the
equipment or other property.
Symbols Marked on Equipment
X
.
Q
W
Caution, risk of electric shock.
Protective ground (earth) terminal.
Functional earth terminal.
Caution, risk of danger. Refer to the manual to maintain the safety provided by the
equipment.
XWWarning
• Do not operate this calibrator in a position where it is difficult to operate
the power switch.
• Do not operate this calibrator in a manner not specified in the manual or
the protection provided by the equipment may be impaired.
• Do not operate the calibrator if it shows signs of damage or malfunction,
the protection provided by the equipment may be impaired.
• Do not use hook-up wire on the calibrator with an insulation or current
rating of less than the calibrator output.
Power Source
The 57LFC is intended to operate from a power source that will not apply more than 246 V ac
rms between the supply conductors or between either supply conductor and ground. A protective
ground connection by way of the grounding conductor in the power cord is essential for safe
operation.
Use the Proper Fuse
To avoid fire hazard, use only the fuse specified on the line voltage selection switch label, and
which is identical in type voltage rating, and current rating.
Grounding the 57LFC
The 57LFC is Safety Class I (grounded enclosure) instruments as defined in IEC 61010 2nd
Edition. The enclosure is grounded through the grounding conductor of the power cord. To avoid
electrical shock, plug the power cord into a properly wired earth grounded receptacle before
connecting anything to any of the 57LFC terminals. A protective ground connection by way of
the grounding conductor in the power cord is essential for safe operation.
Use the Proper Power Cord
• Use only the power cord and connector appropriate for proper operation of a 57LFC.
• Use only a power cord that is in good condition.
• Refer cord and connector changes to qualified service personnel.
Do Not Operate in Explosive Atmospheres
To avoid explosion, do not operate the 57LFC in an atmosphere of explosive gas.
Do Not Remove Cover
To avoid personal injury, do not remove the cover from the 57LFC. Do not operate the 57LFC
without the cover properly installed. There are no user-serviceable parts inside the 57LFC, so
there is no need for the operator to ever remove the cover.
SERVICING SAFETY
SUMMARY
FOR QUALIFIED SERVICE
PERSONNEL ONLY
Also refer to the preceding Operator Safety Summary
Do Not Service Alone
Do not perform internal service or adjustment of this product unless another person
capable of rendering first aid and resuscitation is present.
Use Care When Servicing With Power On
Dangerous voltage exist at many points inside this product. To avoid personal injury, do
not touch exposed connections and components while power is on.
Whenever the nature of the operation permits, keep one hand away from equipment to
reduce the hazard of current flowing through vital organs of the body.
Do not wear a grounded wrist strap while working on this product. A grounded wrist strap
increase the risk of current flowing through the body.
Disconnect power before removing protective panels, soldering, or replacing components.
High voltage may still be present even after disconnecting power.
FIRST AID FOR
ELECTRIC SHOCK
Free the Victim From the Live Conductor
Shut off high voltage at once and ground the circuit. If high voltage cannot be turned off
quickly, ground the circuit.
If the circuit cannot be broken or grounded, use a board, dry clothing, or other
nonconductor to free the victim.
Get Help!
Yell for help. Call an emergency number. Request medical assistance.
Never Accept Ordinary and General Tests for Death
Symptoms of electric shock may include unconsciousness, failure to breathe, absence of
pulse, pallor, and stiffness, and severe burns.
Treat the Victim
If the victim is not breathing, begin CPR or mouth-to-mouth resuscitation if you are
certified.
Table of Contents
Chapter Title Page
1 Introduction and Specifications ........................................................ 1-1
AC Voltage Accuracy ............................................................................... 1-8
AC Voltage Distortion .............................................................................. 1-9
AC Current Accuracy................................................................................ 1-10
AC Current Distortion............................................................................... 1-11
1-1
57LFC/AN
Service Manual
1-2
Introduction and Specifications
Introduction 1
Introduction
The Fluke Model 57LFC System Calibrator (hereafter called the Calibrator) is a precise
instrument that calibrates a wide variety of electrical measuring instruments. This
calibrator maintains a high accuracy over a wide ambient temperature range, and is able
to test instruments in harsh environments, eliminating the restriction of calibrating only in
a temperature-controlled standards laboratory. With a 57LFC, you can calibrate precision
multimeters that measure ac or dc voltage, ac or dc current, and resistance. The Calibrator
operates in a similar manner to the 57XXA series calibrators.
Specifications are provided at the end of this chapter. The Calibrator is a fullyprogrammable precision source of the following:
• DC voltage to 220 V.
• AC voltage to 220 V rms, with output available from 10 Hz to 100 kHz.
• AC and DC current to 2.2 A, with AC output available from 10 Hz to 20 kHz.
• Resistance in values from 0 Ω to 19 MΩ in 1 and 1.9x.
Features of the calibrator include the following:
• Automatic meter error calculation obtained through using a simple remote adjust.
• Programmable entry limits used for restricting the levels that can be remotely keyed
into the calibrator, preventing access to levels that may be harmful to equipment or
personnel.
• Real-time clock and calendar.
• Offset and scaling modes that simplify linearity testing of multimeters.
• Standard IEEE-488 (GPIB) interface, complying with ANSI/IEEE Standards 488.1-
1987 and 488.2-1987.
• Internal self-testing and diagnostics of analog and digital functions.
• Status LEDs on front panel to indicate standby (yellow), operate (green), high
voltage (red), and fault (red and yellow).
Service Information
Each calibrator is warranted to the original purchaser for a period of one year beginning
on the date received. The warranty is located at the front of this manual.
Service and technical advice for the calibrator is available at Fluke Service Centers. For a
complete list of Fluke Service Centers, visit www.fluke.com.
A worldwide network of Fluke service centers supports Fluke instruments and assists
customers in many ways. Most service centers have standards and calibration laboratories
certified by local national standards organizations. The following is a partial list of the
services provided by most service centers:
• Repair and certified traceable calibration of all Fluke products.
• Certified traceable calibration of many non-Fluke standards and calibrators.
• Worldwide exchange of calibrator internal modules. Delivery inside the U.S.A. is
typically within 48 hours.
• Service agreements with the flexibility to suit your needs. These can be a simple
warranty extension or an agreement that includes on-site support. Calibration service
agreements are also available in many areas.
1-3
57LFC/AN
Service Manual
Accessories
• Training programs and seminars, including laboratory metrology, system
applications, and product maintenance.
• Application help and consulting, including system design, hardware selection,
custom software, site evaluation and installation.
• Replacement parts inventory, including recommended spare parts and module kits.
Visit www.fluke.com for locations and phone numbers of authorized Fluke service
centers.
Table 1-1 summarizes the accessories available for the Calibrator. Following the table is
a brief description of each accessory.
Table 1-1. 57LFC Accessories
Model Description
5440A-7002
5440A-7003
Y8021 IEEE-488 Shielded Interface Cable, 1 Meter
Y8022 IEEE-488 Shielded Interface Cable, 2 Meters
Y5537 Rack Mount Kit for 57LFC and 5500A
Low Thermal EMF Test Lead Set with Banana Plugs:
One 4 ft. cable (122 cm) and two 2 ft. (61 cm) cables.
Low Thermal EMF Test Lead Set with Spade Lugs.
Two 4 ft. (122 cm) cables and One 2 ft. (61 cm) cable.
Low Thermal EMF Test Leads
Two types of low thermal test leads are available. These cables are designed to exhibit
low thermal emfs. The types available are:
• Model 5440A-7002. Low Thermal Test Lead cables with banana plugs.
Set includes one 4 ft. (122 cm) cable and two 2 ft. (61 cm) cables. Each cable
includes two conductors and a shield lead.
• Model 5440A-7003. Low Thermal Test Lead cables with spade lugs.
Set includes two 4 ft. (122 cm) cables and one 2 ft. (61 cm) cable. Each cable
includes two conductors and a shield lead. Shield lead has a banana plug connector.
Rack Mount Kit
The rack mount kit provides all the hardware necessary to mount the 57LFC. Rack mount
instructions are included with each kit.
1-4
Shielded IEEE-488 Cables (Y8021, Y8022, and Y8023)
Shielded IEEE-488 cables are available in two lengths (See Table 1-1). The cables attach
the calibrator to any other IEEE-488 device. Each cable has double 24-pin connectors at
both ends to allow stacking. Metric threaded mounting screws are provided with each
connector. Figure 4-2 in Chapter 4 shows the pinout for the IEEE-488 connector.
Introduction and Specifications
Contacting Fluke 1
Contacting Fluke
All Calibrators delivered to the Navy, contractors and subcontractors for the RTCASS
program will be repaired and calibrated at the Fluke Technical Support Center in Everett,
Washington. Contact Fluke Technical Support at 1-888-993-5853 or by sending a fax to
1-425-446-6390. The address for the Fluke Technical Support
Center address is:
Fluke Technical Support Center
1420 75th ST SW
Everett, WA 98203-6256
U. S. A.
Once full production is started the following service centers will also maintain and
calibrate the Calibrator in Europe.
FLUKE NEDERLAND B.V.
Customer Support Services
Science Park Eindhoven 5108
5692 EC Son
Netherlands
and in Asia,
FLUKE DEUTSCHLAND GMBH
Customer Support Services
Heinrich Hertz Straße 11
D-34123 Kassel
Germany
FLUKE SOUTH EAST ASIA PTE LTD.
Service Center
83 Clemenceau Avenue
#15-15/06 Ue Square
239920
Singapore
1-5
57LFC/AN
Service Manual
Specifications
General Specifications
Factory set IEEE488 address ....... 4
Warm-up Time ...............................Twice the time since last warmed up, to a maximum of 30 minutes
Temperature Performance............ Operating: 0 to 50 °C
Temperature Coefficient............... Temperature Coefficient for temperatures outside tcal ±5 °C is 10% of
Relative Humidity
Altitude
Safety .............................................Designed to comply with IEC 61010-1 2000-1; ANSI/ISA-S82.01-1994;
Analog Low Isolation .................... 20 V
EMC ................................................Designed to comply with IEC 61326-1 2000-11 (EMC) Class A Criteria
Line Power
Settling Time.................................. ≤ 3 to 10 seconds, similar to 5700A.
Chassis Dimensions, H x W x D ... 178 mm x 432 mm x 457 mm (7 in x 17 in x 18 in) maximum
Weight ............................................ Less than 18.15 kg (40 pounds)
Electrical/Signal Interface............. Fluke 5700A/LP equivalent signal interface, AC Mains, IEEE-488, and
Cooling........................................... 1.42 cubic meters (50 cubic feet) per minute
The 57LFC System Calibrators are verified and calibrated at the factory prior to shipment
to ensure they meet the accuracy standards required for all certified calibration
laboratories. By calibrating to the specifications in this chapter, you can maintain the high
performance level throughout the life of your calibrator.
Specifications are valid after a warm-up period of twice the time the calibrator has been
turned off, up to a maximum of 30 minutes. For example, if the calibrator has been turned
off for five minutes, the warm-up period is ten minutes.
To ensure the validity of the specifications, a dc zeros calibration must be performed at
least every 15 days. If more than 15 days elapse without a dc zeros calibration a warning
message appears. This procedure does not require any external equipment or connections
and takes approximately 5 minutes to complete.
Calibration: 15 to 37.7 °C
Storage: -40 to 75 °C
the 1-year spec per °C.
Operating: ................................... <95% to 43 °C (non-condensing), <40% to 50 °C.
Operating: ...................................3,050 m (10,000 ft) maximum
Non-operating: ........................... 12,200 m (40,000 ft) maximum
CAN/CSA-C22.2 No. 1010.1-92
C
Line Voltage (selectable): ........... 100 V, 120 V, 208 V, and 230 V
Line Frequency: .......................... 47 to 63 Hz
Line Voltage Variation: ................±7% about line voltage setting
Maximum VA: ............................. 200
RS-232 connectors, AC power switch, and Line Voltage selection all on
front panel
1-6
XWCaution
Internal damage may occur if excessive external power is
applied to the binding posts while the instrument is operating in
current, voltage, or ohms. In voltage and current, exceeding
30 V may cause damage. In ohms, do not exceed the maximum
specified current.
Introduction and Specifications
Specifications 1
Accuracy Specifications
DC Voltage Accuracy
Ranges
0 mV to 220 mV 0.004% 3 µV 0.1 µV
Absolute Uncertainty,
tcal ±5 °C
±(% output + V) 1 Year
Resolution
50 Ω output impedance
0 V to 2.2 V 0.0025% 3 µV 1 µV 50 mA
0 V to 11 V 0.0025% 30 µV 10 µV 50 mA
0 V to 22 V 0.0025% 30 µV 10 µV 50 mA
0 V to 220 V 0.004% 300 µV 100 µV 20 mA
[1] Remote sensing provided on all but 220 mV range.
Note: minimum output 0 V for all ranges.
[1] Discrete resistors with characterized values stored in non-volatile memory. Specifications apply to the characterized value using 4-wire connections.
[2] Active two-wire compensation may be selected for values up to 190 kΩ. Active compensation is 11 mA load and 2 V burden minimum.
Characterized Value,
tcal ± 5 °C
± (Ω) 1 Year
Full Specification
Current
Maximum Peak
Current
8 mA to 200 mA 220 mA 0.001
8 mA to 100 mA 220 mA 0.001
8 mA to 100 mA 220 mA 0.001
8 mA to 11 mA 220 mA 0.001
8 mA to 11 mA 160 mA 0.001
8 mA to 11 mA 70 mA 0.001
8 mA to 11 mA 50 mA 0.001
1 mA to 2 mA 22 mA 0.010
1 mA to 1.5 mA 16 mA 0.010
0.1 mA to 0.5 mA 3 mA 0.100
0.05 mA to 0.25 mA 1.6 mA 0.200
0.01 mA to 0.1 mA 0.3 mA 1.000
5 µA to 50 µA 0.16 mA 2.000
5 µA to 20 µA 30 µA NA
2.5 µA to 10 µA 16 µA NA
0.5 µA to 2 µA 3 µA NA
0.25 µA to 1 µA 1.6 µA NA
Two-Wire Active
Compensation
Adder (ohms)
[2]
1-7
57LFC/AN
Service Manual
AC Voltage Accuracy
Ranges Frequency
10 mV to 22 mV
10 Hz to 45 Hz 0.15% 20 µV
45 Hz to 20 kHz 0.08% 20 µV
20 kHz to 50 kHz 0.25% 20 µV
Absolute Uncertainty,
tcal ±5 °C
± (% output + V) 1 year
Resolution
1 µV
Maximum
Burden
[1] [2]
50 Ω output
impedance
50 kHz to 100 kHz 0.5% 50 µV
22 mV to 220 mV
10 Hz to 45 Hz 0.15% 50 µV
45 Hz to 20 kHz 0.05% 50 µV
20 kHz to 50 kHz 0.25% 50 µV
1 µV
50 Ω output
impedance
50 kHz to 100 kHz 0.4% 200 µV
0.22 V to 2.2 V
10 Hz to 45 Hz 0.1% 250 µV
45 Hz to 20 kHz 0.05% 100 µV
20 kHz to 50 kHz 0.1% 320 µV
10 µV 50 mA
50 to 100 kHz 0.25% 2000 µV
2.2 V to 22 V
10 Hz to 45 Hz 0.1% 1 mV
45 Hz to 20 kHz 0.05% 1 mV
20 kHz to 50 kHz 0.1% 1 mV
100 µV 50 mA
50 kHz to 100 kHz 0.25% 2 mV
22 V to 220 V
[2]
10 Hz to 45 Hz 0.1% 10 mV
45 Hz to 20 kHz 0.05% 10 mV
20 kHz to 50 kHz 0.25% 20 mV
1 mV 20 mA
50 kHz to 100 kHz 0.5% 50 mV
[1] Remote sensing provided on all but 22 mV and 220 mV ranges. Maximum output current is reduced by 50% above 40 °C. Maximum load capacitance
is 500 pF.
[2] V x Hz limited to 11.8e6.
Note: Frequency uncertainty is specified to be 0.01% of frequency setting.
1-8
Introduction and Specifications
Specifications 1
AC Voltage Distortion
Max Distortion and noise
Ranges Frequency
10 mV to 22 mV
22 mV to 220 mV
0.22 V to 2.2 V
2.2 V to 22 V
22 V to 220 V
[1] For larger resistive loads, multiply uncertainty specifications by (actual load/maximum full load for accuracy)2.
10 Hz to 45 Hz 0.15% 90 µV
45 Hz to 20 kHz 0.035% 90 µV
20 kHz to 50 kHz 0.15% 90 µV
50 kHz to 100 kHz 0.25% 90 µV
10 Hz to 45 Hz 0.15% 90 µV
45 Hz to 20 kHz 0.035% 90 µV
20 kHz to 50 kHz 0.15% 90 µV
50 kHz to 100 kHz 0.20% 90 µV
10 Hz to 45 Hz 0.15% 200 µV
45 Hz to 20 kHz 0.035% 200 µV
20 kHz to 50 kHz 0.15% 200 µV
50 kHz to 100 kHz 0.20% 200 µV
10 Hz to 45 Hz 0.15% 2 mV
45 Hz to 20 kHz 0.035% 2 mV
20 kHz to 50 kHz 0.2% 2 mV
50 kHz to 100 kHz 0.5% 2 mV
10 Hz to 45 Hz 0.15% 10 mV
45 Hz to 20 kHz 0.05% 10 mV
20 kHz to 50 kHz 0.8% 10 mV
50 kHz to 100 kHz 1.0% 10 mV
10 Hz to 10 MHz Bandwidth
±(% output + V)
[1]
1-9
57LFC/AN
Service Manual
AC Current Accuracy
Ranges
[3]
Frequency
10 Hz to 20 Hz
20 Hz to 45 Hz
30 µA to 220 µA
45 Hz to 1 kHz
1 kHz to 5 kHz
5 kHz to 10 kHz
10 Hz to 20 Hz
20 Hz to 45 Hz
0.22 mA to 2.2 mA
45 Hz to 1 kHz
1 kHz to 5 kHz
5 kHz to 10 kHz
10 Hz to 20 Hz
20 Hz to 45 Hz
2.2 mA to 22 mA
45 Hz to 1 kHz
1 kHz to 5 kHz
5 kHz to 10 kHz
10 kHz to 20 kHz
10 Hz to 20 Hz
20 Hz to 45 Hz
22 mA to 220 mA
45 Hz to 1 kHz
1 kHz to 5 kHz
5 kHz to 10 kHz
10 kHz to 20 kHz
0.22 A to 2.2 A
10 Hz to 45 Hz
45 Hz to 1 kHz
1 kHz to 5 kHz
5 kHz to 10 kHz
[1] 400 µH with inductive compensation ON.
[2] See AC Current Compliance Adder and Distortion Table for impact of compliance voltage on specification.
[3] I-guard, (as on the 5700A rear panel), required when sourcing low-level currents through a long cable.
Note: Frequency uncertainty is specified to be 0.01% of frequency setting.
Absolute Uncertainty,
tcal ±5 °C
±(% of output + A) 1 year
Resolution
0.3% 0.2 µA
0.15% 0.2 µA
0.125% 0.2 µA
0.01 µA 7 V 50 µH
0.4% 0.3 µA
1.5% 0.4 µA
0.2% 0.3 µA
0.15% 0.3 µA
0.1% 0.3 µA
0.1 µA 7 V 50 µH
0.2% 0.3 µA
0.8% 0.5 µA
0.2% 3 µA
0.1% 3 µA
0.1% 3 µA
0.2% 3 µA
1 µA 7 V 50 µH
0.4% 5 µA
0.8% 5 µA
0.18% 30 µA
0.1% 30 µA
0.1% 30 µA
0.3% 50 µA
10 µA 7 V 50 µH
0.4% 100 µA
0.8% 200 µA
0.18% 300 µA 100 µA 4 V 2.5 µH
0.1% 300 µA
1% 3000 µA
5% 5000 µA
Maximum
Compliance
Voltage (rms)
[2]
Maximum
Inductive
[1]
Load
1-10
Introduction and Specifications
Specifications 1
AC Current Distortion
Maximum Resistive
Ranges Frequency
Load For Full
Accuracy Ω
[1]
10 Hz to 20 Hz 0.15% 0.5 µA
20 Hz to 45 Hz 0.1% 0.5 µA
30 µA to 220 µA
45 Hz to 1 kHz 0.05% 0.5 µA
20 kΩ
1 kHz to 5 kHz 0.5% 0.5 µA
5 kHz to 10 kHz
1.0% 0.5 µA
10 Hz to 20 Hz 0.15% 1.5 µA
20 Hz to 45 Hz 0.06% 1.5 µA
10 k
0.22 mA to 2.2 mA
45 Hz to 1 kHz 0.05% 1.5 µA
Ω
1 kHz to 5 kHz 0.5% 1.5 µA
5 kHz to 10 kHz
1.0% 1.5 µA
10 Hz to 20 Hz 0.15% 5 µA
20 Hz to 45 Hz 0.05% 5 µA
2.2 mA to 22 mA
45 Hz to 1 kHz 0.07% 5 µA
1 kHz to 5 kHz 0.3% 5 µA
3.18 k
Ω
5 kHz to 10 kHz 0.7% 5 µA
10 kHz to 20 kHz
1.0% 5 µA
10 Hz to 20 Hz 0.15% 50 µA
20 Hz to 45 Hz 0.05% 50 µA
22 mA to 220 mA
45 Hz to 1 kHz 0.07% 50 µA
1 kHz to 5 kHz 0.30% 50 µA
318
Ω
5 kHz to 10 kHz 0.70% 50 µA
10 kHz to 20 kHz
1.0% 50 µA
10 Hz to 45 Hz 0.2% 500 µA
0.22 A to 2.2 A
[1] For larger resistive loads, multiply uncertainty specifications by actual load/maximum full load for accuracy.
Note: Current times Load cannot exceed the maximum compliance voltage.
This Chapter is intended to provide a detailed description and analysis, where
appropriate, of the printed circuit board assemblies (PCAs) used in the 57LFC System
Calibrator. The Calibrator contains the following PCAs.
• A1 LED PCA
• A3 Motherboard PCA
• A5 Ohms PCA
• A6 Digital Synthesis PCA
• A7 Current PCA
• A8 High Voltage PCA
• A9 Out-Guard CPU PCA
See Figure 2-1 for a block diagram of the 57LFC System Calibrator.
2-3
57LFC/AN
Service Manual
A9
Outguard
Controller
IEEE488
RS232
Mains
Transformer
A6
Inguard
Controller
A3
Outguard
Power
±12 V
+5 V
A3
Inguard
Power
±15 V
±5 V
+6 V
A6
Digital
Synthesis &
Reference
0 to ±2.2 V
AC/DC
S
W
I
T
C
H
A3
Output
Switch
A5
OHMS
0 to 19 M
A7
Current
0 to ±2.2 A
AC/DC
Binding
Posts
S
W
I
T
C
H
S
W
I
T
C
H
2-4
A3
High
Voltage
Power
±45 V
±180 V
Figure 2-1. 57LFC Block Diagram
A8
High
Voltage
2 to ±220 V
AC/DC
S
W
I
T
C
H
apv101f.eps
Theory of Operation
A1 LED PCA 2
A1 LED PCA
The Calibrator front panel A1 LED PCA provides the only visual indication of the
instrument operation. These LEDs provide a color-coded scheme for the instrument
status.
XWWarning
This instrument is capable of outputting lethal voltages.
Observe all safety precautions.
While the LEDs should provide years of operation, they are
subject to wear out like any other component. Never touch the
binding posts without first checking the output with a
multimeter.
The front panel A1 LED PCA is connected to and controlled by the A3 Motherboard
PCA. A cable is used to connect the A3 Motherboard PCA to the A1 LED PCA. On
power up, the yellow LED will light indicating that the instrument has moved into a
standby state. The green LED is used to indicate that the instrument is in operate and
there may be live voltages on the binding posts. The red LED is used to indicate that the
instrument may be outputting hazardous voltages greater than 30 V rms. If diagnostic
failures occur during power-up, both the yellow and red LEDs light. If all three LEDs are
lit, the instrument is broken and must be sent to a qualified technician for repair.
A3 Motherboard PCA
The following discussion covers the theory of operations for the A3 Motherboard PCA
circuits. This A3 Motherboard PCA generally carries power as well as system signal
buses to the circuit cards. The A3 Motherboard PCA can be divided into several areas: 1)
relay control and switch matrix, 2) LED control and output cables, 3) analog and digital
buses, 4) low volt buffer, 5) in-guard power supplies, 6) out-guard power supplies, 7)
miscellaneous circuits, and 8) list of fuses. Please refer to the A3 Motherboard PCA
schematics for this discussion.
The A3 Motherboard PCA contains lethal voltages. Only
qualified technicians should do troubleshooting.
Relay Control and Switch Matrix
The relay matrix is shown on Sheet 1 of the A3 Motherboard PCA schematic, and the
relay control is shown on Sheet 5. Some of the purposes of the relay matrix are to provide
isolation between the output binding posts and the internal circuitry during standby, and
provide isolation when running zero calibration or diagnostics. The functions of the
relays are shown in Table 2-1. The relay control circuits consist of U3, U5, U6, U8, and
U9. For U3 (74HC138), the IG_CS1 signal is generated on the A6 Digital Synthesis
PCA. U8 selects the driver latch used to set or reset the latching relays.
XWWarning
2-5
57LFC/AN
Service Manual
Relay Functional Description
K1 Reset: connect LO’s to the A6 Digital Synthesis PCA; connect OUT_LO to the A6 Digital
K2 Reset: select internal sensing; connect OSNS_HI to IN_SNS_HI and OSNS_LO to
K3 Reset: connect the Digital Synthesis PCA divider; connect IN_SNS_HI to the A6 VDIV
K4 Reset: select VMID for output; connect VMID to OUT_HI
K5 Reset: select external guard; disconnect GUARD from SCOM
Table 2-1. Functional Description of A3 Motherboard PCA Relays
Synthesis PCA RET_LO, and connects IN_SNS_LO to the A6 SNS_LO
Set: disconnect LO’s from the A6 Digital Synthesis PCA; disconnect the A6 Digital
Synthesis PCA RET_LO and SNS_LO from the LO input terminals
IN_SNS_LO
Set: select remote sensing; connect SNS_HI to IN_SNS_HI and SNS_LO to
IN_SNS_LO
Set: disconnect the Digital Synthesis PCA divider; disconnect IN_SNS_HI from VDIV
Set: disconnect VMID from output; disconnect VMID from OUT_HI
Set: select internal guard; connect GUARD to SCOM
K6 Reset: select the 2 V buffer amp; connect V3BUF to VMID for output
Set: disconnect the 2 V buffer amp; disconnect V3BUF from VMID
K7 Reset: disconnect the A8 High Voltage PCA output; disconnect OUT_220V from
OUT_HI
Set: select the A8 High Voltage PCA output; connect OUT_220V to OUT_HI
K8 Reset: disconnect HIGUARD (IGUARD) from GUARD (VGUARD)
Set: connect HIGUARD to GUARD
K9 Reset: connect A6 Digital Synthesis PCA LO return; connect OUT_LO to A6_RET_LO
Set: disconnect the A6 Digital Synthesis PCA LO return, disconnect OUT_LO from
A6_RET_LO
K10 Reset: provide an internal VMID sense path, connect VMID to the A6 VDIV
Set: normal operation; disconnect VMID from VDIV
K11 Reset: provide an internal 220 V sense path; connect OUT_220V to VMID
Set: normal operation; disconnect OUT_220V from VMID
On power up, the relays are forced into a benign setting to protect circuitry and the
customer. Table 2-2 shows the state of the A3 Motherboard PCA relays after power up.
Table 2-3 shows the A3 Motherboard PCA relay states when in several states (power up
and standby). Table 2-4 shows the status of control lines for all modes of A3
Motherboard PCA operation.
2-6
Theory of Operation
Table 2-2. A3 Motherboard PCA Power-up and Fault Relay States
Relay State on Power-up or after Fault
K1 Set: disconnect A6 Digital Synthesis PCA LO sense
K2 Reset: select internal sensing
K3 Set: disconnect the A6 Digital Synthesis PCA divider
K4 Set: disconnect VMID from output
K5 Reset: select external guard
K6 Undefined
K7 Reset: disconnect the A8 High Voltage PCA output
K8 Undefined
K9 Set: disconnect the A6 Digital Synthesis PCA LO return
K10 Undefined
K11 Undefined
A3 Motherboard PCA 2
2-7
57LFC/AN
Service Manual
Table 2-3. A3 Motherboard PCA Final Relay States by Instrument State
Guard:
Sense:
Relay (Virtual) Register:
Relay:
Instrument State\Bit
Power Up r s s s r s r s s r s 03ad
Dormant r s s s r s r s s r s 03ad
External Guard (mod
mask 0010h)
Internal Guard x x x x x x s x x x x 0010 0010
Internal Sense (mod mast
002h)
External Sense x x x x x x x x x s x 000 2 0002
22 mV A6 Output r s r s r s g r s r r 02a4 02b4 - -
Standby 22 mV A6
Output
220 mV A6 Output r s r s r s g r s r r 02a4 02b4 - -
Standby 220 mV A6
Output
Optt 3.3 V A6 Output
using LO Comp Amp
Opt 3.3 V A6 Output r s r s r s g r r d r 0210 02b0 02a2 02b2
Standby Opt 3.3 A6
Output
2.2 V Buffer Out using LO
Comp Amp
2.2 V Buffer Output r s r s r r g r r d r 0280 0290 0282 0292
Standby 2.2 V Buffer
Output
22 V A8 Output using LO
Comp Amp
22 V A8 Output r s r s r s g r r d r 02a0 02b0 02a2 02b2
Standby 22 V A8 Output r s s s r s r s s r s 03ad
220 V A8 Output Using
LO Comp Amp
220 V A8 Output r s r s s s g s r d r 02e8 02f8 02ea 02fa
Standby 220 V A8 Output r s s s r s r s s r s 03ad
Ohms A5 Output 4-Wire r s s r r s g s s s s - - 032f 033f
Standby Ohms A5 4W r s s r r s r s s r s 032d
Ohms A5 Output 2-Wire r s s r r s g s s r s 032d 033d - -
Standby Ohms A5 2W r s s r r s r s s r s 032d
Ohms A5 Out 2W Comp r s s r r s g s s d s 032d 033d 032f 033f
Standby A5 2W Comp r s s r r s r s s r s 032d
Current A7 Output r s s r r s g s s s s 032f 033f - -
Key: x = don’t care, r = reset, s = set, d = reset (0) for internal sense or set (1) for remote sense, g = reset (0) for external
guard or set (1) for internal guard
Notes:
• An over-voltage detection or other serious problem should trip the instrument to the fault state.
• An over-compliance or over-current detection should trip the instrument to the appropriate overload fault.
• A hardware fault causes the instrument to enter the fault state.
2-8
Theory of Operation
Table 2-4. Control Register States by Instrument State
Output Ohms, I, or V
>30 V, Monitor Internal
Temperature via SMUX
Output V > 30 V,
Monitor Internal
Temperature via SMUX
Key: x = don’t care, H = High (Off), L = Low (On)
8 4 2 1 8 4 2 1 hex
x x H H x H L H 35
x x H L x H L H 25
x x H L x L L H 21
x x L H x H L H 15
x x L H x L L H 11
A3 Motherboard PCA 2
2-9
57LFC/AN
Service Manual
LED Control and Output Cables
STANDBY* Turns on the STANDBY LED when asserted Low (YELLOW)
OPERATE* Turns on the OPERATE LED when asserted Low (GREEN)
WARNING* Turns on the WARNING LED when asserted Low (RED)
CKHVCUR* Turns on an analog switch to place the rectified and filtered shunt voltage generated
CKIT* Turns on a switch to connect the output of the temperature to SMUX.
Sheet 5 of the schematic shows the LED control (panel LED's connector). The LEDs are
mounted on their own daughter card with control wires cabled from the A3 Motherboard
PCA. A description of each LED is provided in Table 2-5.
Table 2-5. Functional Description of LED Signals
Signal Functional Description
by the HVCOM current onto the SMUX line when asserted Low
Sheet 1 of the A3 Motherboard PCA schematic shows the connection and wiring for the
output cable from the A3 Motherboard PCA to the front panel binding posts. Note that
there are two guards - IGUARD and GUARD (voltage guard). These guards may be tied
together through K8 when voltage is selected. The other signal leads are OUT_HI,
SNS_HI, OUT_LO, and SNS_LO. The output high and low signals (OUT_HI and
OUT_LO) are used for the main output for volts, current, and ohms. The output sense
signals (SNS_HI and SNS_LO) are used to sense and internally adjust the output signals.
The sense terminals are not used for standard (uncompensated) two wire ohms or ac and
dc current.
Signal Buses
The system analog and digital buses are brought to the circuit cards through the A3
Motherboard PCA connectors J105-108 and J205-208. J105-J108 provides the in-guard
(IG) digital bus signal lines while J205-208 route the in-guard analog signal lines. Guard
is tied to chassis through a set of diodes and MOVs (CR57, CR58, and RV3 and CR69,
CR68, and RV1) and prevents the guard from floating more than 20 V from chassis. The
guard is tied to SCOM through CR55, CR56, RV2, and R86. Note that relay K5 on
Sheet 1 can connect the guard trace directly to SCOM.
Low Volt Buffer
The low voltage buffer circuit is shown on Sheet 4 of the A3 Motherboard PCA
schematic (along the bottom-middle of the Sheet). The V3_3 input signal to U2 comes
from the A6 Digital Synthesis PCA (A6). U2, combined with Q1,2,7 and 8, act to buffer
the V3_3 signal and isolate the output voltage from the A6 card. Q3 and Q4 limit the
output current that may be drawn.
In-guard Power Supplies
The power supplies for the analog circuits, also referred to as in-guard supplies, are
shown on Sheets 2, 3, and 4 of the A3 Motherboard PCA. On Sheet 2 of the A3
Motherboard PCA schematic, the raw transformer secondaries enter at P2. 5AC1, 5AC2,
15AC1 and 15AC2 go to Sheet 3 of the A3 Motherboard PCA schematic along with the
GUARD signal. RT7-10 protects the transformer from large current draws that might
occur if a diode bridge on Sheet 3 of the A3 Motherboard PCA schematic or other
components short.
2-10
Theory of Operation
A3 Motherboard PCA 2
The 45 ac, 180 ac, and 360 ac provide the raw voltages that will be used by the A8 High
Voltage and A5 Ohms PCAs. If secondary voltages become too large, TRIAC Q19 will
turn on the limit voltage, open the mains fuse, and prevent damage. CR62 is the full wave
rectifier for the +/-45UNR supply. The +/-45UNR are regulated to become the +/-45V
supplies. MP7 and MP8 are assemblies that contain the heat sinks and the main pairs of
drive transistors for the 45 V regulated supplies. U18 controls the regulation. Q12 with
resistor R48 and R54 and Q13 with resistors R49 and R57 limit the output currents to
~120 mA. CR28 with VR10 and VR11 and CR 26 with VR12 and VR 13 protect against
high voltages damaging the regulation circuits. Note that the HVCOM line caries the
ground return currents for the high voltage supplies back to the center tap of the
transformer.
On Sheet 3 of the A3 Motherboard PCA schematic, CR67 and CR51 rectify the 15 V ac
and 5 V ac (left side of the Sheet), respectively. The resulting +15UNR goes through
U21, a dual regulator., and becomes the guarded +15 V supply. -15UNR goes into U22
and becomes the -15 V supply. VR14 and VR15 limit short term over-voltages to 22 V or
so. The 5 ac signals are regulated to be the power for the relays (+5RLH) and the logic
(+5 V). The +/-15 V supplies are referenced to SCOM, while the +/-5 V supplies are
referenced to DCOM. Note that SCOM and DCOM grounds are kept close to each other
electrically due to the Schottky diodes, CR18 and CR19. CR29 and CR31 limit the
amount that the +/-15 V and +/-5 V power supplies can float from each other. Each
regulator in the design is protected against short-term over voltages occurring at the
regulator output with diodes CR41, CR48, CR35, CR36, and CR34. The 6 turn beads
reduce conducted noise.
Outguard Power Supplies
The connector P1 and the out-guard secondaries labeled 12GAC and 5GAC are shown on
Sheet 2 of the A3 Motherboard PCA schematic. These unregulated supplies including
+5VG_UNR, become the regulated supplies for the outguard controller card (A9) and
include +5VG and +/-12VG. These supply power the A9 Out-Guard CPU PCA through
the connector J1 (found on Sheet five). RT1, and RT3-RT5 protect the transformer from
large current draws that might occur if there is a short down stream. Each regulator in the
design (U20, U25, and U19) is protected against short-term over voltages occurring at the
regulator output with diodes CR42, CR43, and CR59. The 6 turn beads reduce conducted
noise. The regulated +/-12 V supplies also provide power to the 24 V fan located at the
front of the instrument. A second fan connector was added for a future version of the
instrument. GCOM is the reference and is tied through resistors to earth, and tied to
DCOM (the in-guard digital ground) through a 24 V bi-directional Zener, VR17.
Miscellaneous Circuits
On Sheet five of the A3 Motherboard PCA schematic, J1 connects the digital signals
from the A9 Controller card to the A3 Motherboard PCA. The serial data signals form the
communication path to the A6 Digital Synthesis PCA (which also controls the in-guard
digital bus). J6 is used for trouble shooting the circuitry in manufacturing and service
testing. Also on that Sheet is an area marked NOT INSTALLED. These circuits may be
used in a future version of the product.
Sheet 3 of the A3 Motherboard PCA schematic shows U27, a switch used to connect
signals to the SMUX bus line for monitoring the A6 Digital Synthesis PCA.
CKHVCUR* is driven by U7 pin 12 on Sheet 5 of the A3 Motherboard PCA schematic
for connecting the output of the circuit checking the HVCOM current to SMUX. CKIT*
can turn on a switch in U27 to connect the output of the temperature sensor h30 to
SMUX.
2-11
57LFC/AN
Service Manual
Troubleshooting Test Points
When a problem occurs with the instrument operation, one likely place to look is the
A3 Motherboard PCA and its power supplies. There are a number of convenient test
points to monitor the supply voltages. The test points are listed in Table 2-6.
The test points can be divided into several groups: general, function unique, out-guard,
and fault. General test points include V3BUF, +/-5UNR, +/-5V, +/-15UNR, and
+/-15V. The V3BUF monitors the buffered signal used for ac and dc output voltages
between 220 mV and 2.2 V +/-5UNR, +/-5V, +/-15UNR, and +/-15V monitor the main
supplies used in all of the in-guard board circuitry.
Power supplies unique to the A7 Current PCA are monitored by MMONGO, MMCOM,
IREF, ICOM, +/-15I_UNR, and 15I. Power supplies unique to the A8 High Voltage PCA
are +/-45UNR, +/-45V, +/-180UNR, and +/-360UNR. The A8 High Voltage PCA uses
the +/-45V, +/-180UNR and +/-360UNR to produce the high voltage outputs. The A5
Ohms PCA uses the general and +/-45Vsupplies.
Out-guard test points monitor provide access to +5VG_UNR, +5VG, GGND,
+/-12VG_UNR, and +/-12VG power signals. These power supplies are only used for the
controller card (A9) and for manufacturing test fixtures.
Besides monitoring the power supplies, several test points are used to monitor fault
conditions. Note that the FAULT* signal is a wired "O". The main fault signal is TP3. If
any fault occurs, TP3 becomes active. TP2 monitors the 15V BALANCE FAULT* signal
and provides status on the +15 V and -15 V supplies. If either supply varies from the
other by too much (indicating excessive load or failure), the fault becomes active. TP4
monitors the HVCOM signal trace. If the HVCOM signal moves more than 0.5 V from
SCOM, the fault becomes active. TP5 monitors OVER22V. This signal indicates if
SCOM differs from chassis ground by more than about 23 V. TP49 monitors 45 V
BALANCE FAULT. This fault is similar to the 15 V BALANCE FAULT and monitors
that +45 V and -45 V supplies stay within a fixed range of each other.
Table 2-6. A3 Motherboard PCA Test Points List
2-12
Number Description Number Description NumberDescription
TP 1 V3BUF TP21 +45 V TP41 +MMONGO
TP 2 15V BALANCE FAULT* TP22 -45 V TP42 +15UNR
TP 3 FAULT* TP23 +15 V TP43 -15UNR
TP 4 HVCOM FAULT* TP24 SCOM TP44 -12VG
TP 5 CHASSIS 22V FAULT* TP25 SCOM TP45 -15I_UNR
TP 6 +5VG_UNR TP26 -15 V TP46 +12VG_UNR
TP 7 DCOM TP27 HVCOM TP47 -12VG_UNR
TP 8 DCOM TP28 HVCOM TP48 -45UNR
TP 9 -5 V TP29 GGND TP49 45V BALANCE FAULT*
TP10 +5RLH TP30 +360UNR
TP11 +5 V TP31 +180UNR
TP12 -MMONGO TP32 -180UNR
TP13 MMCOM TP33 -360UNR
Theory of Operation
Table 2-6. A3 Motherboard PCA Test Points List (cont.)
Number Description Number Description NumberDescription
TP14 MMCOM TP34 GGND
TP15 +IREF TP35 -5UNR
TP16 -IREF TP36 +15I_UNR
TP17 -15I TP37 +5VG
TP18 ICOM TP38 +12VG
TP19 ICOM TP39 +5UNR
TP20 +15I TP40 +45UNR
A5 Ohms PCA 2
List of Fuses
There are several fuses used on the A3 Motherboard PCA when resistive thermal
switches cannot be used. The fuses are used primarily in the high-voltage power supply
circuits. F1 and F2 are used to protect the raw +/-45 V supplies. F4 and F5 protect the +/180 V supplies, and F3 and F6 protect the +/-360 V supplies.
A5 Ohms PCA
The following discussion covers the theory of operations for the A5 Ohms PCA circuitry.
The A5 Ohms PCA sources 1x and 1.9x fixed value resistances, provides compensation,
and generates an active guard. The A5 Ohms PCA can source ohms in one of several
ways: two-wire, two-wire with compensation, and four-wire ohms. For discussion
purposes, the A5 Ohms PCA can be divided into several areas: precision thin film resistor
networks, relay switch matrix and control circuits, other control circuits, guard circuit,
two-wire compensation circuits, monitoring circuits, and diagnostic circuits. See Figure
2-1 for a block diagram of the A5 Ohms PCA. The last part of this section discusses
diagnostic capability built into the A5 Ohms PCA. See the A5 Ohms PCA schematics for
circuit details.
OUT_HI
SNS_HI
SNS_LO
OUT_LO
A3 Motherboard PCA
HIGUARD
Relay
Switch
Matrix and
Switch
Control
Other Control and
Monitor Circuits
Thin Film Resistor
Networks
Compensation
Circuits
Active Guard
Circuits
Floating
Supply
(FCOM)
Figure 2-2. Block Diagram of the A5 Ohms PCA
apv001f.eps
2-13
57LFC/AN
Service Manual
Precision Resistor Networks
Relay Switch Matrix and Control
Fluke proprietary hermetically sealed thin film resistors (Z1-5) are used in the A5 Ohms
PCA. While the values are not exact, the thin film resistors are made to have excellent
time and thermal stability with low temperature coefficients. The resistors are made for
4-wire operation but may be used as 2-wire devices with degraded specifications. In
four-wire mode, the resistors are connected to OUT_HI, SNS_HI, OUT_LO, and
SNS_LO. The resistors have the following nominal ohm values: 0 (short), Z1 (1, 1.9), Z2
(10, 19, 100, 190, 1.0 k, 1.9 k), Z3 (10 k, 100 k, 1 M, 10 M), Z4 (19 k, 190 k, 1.9 M,
19 M). As an example, at 19 M, the maximum peak current is 1.6 µA. The limit is
required because an active circuit used to guard the resistance value from leakage has a
maximum range of about +/-33 V. Exceeding that voltage may cause the ZGUARD
buffer to cause errors in resistance measurement. Note that the resistors have maximum
peak currents that should not be exceeded, and excessive current for extended periods of
time may damage the resistors and create a long term offset. Only one resistor is switched
onto the out high and out low signal traces at a time. The output and sense resistor traces
are directed to the output terminals through a series of relays.
The relay switch matrix and resistors are shown on Sheet 1 of the A5 Ohms PCA
schematic, and the switch control circuits are shown on Sheet 5 of the A5 Ohms PCA
schematic. A block diagram of the high/low and high-sense/low-sense relay routing is
shown in Figures 2-2 and 2-3. The relay matrix provides switching between the various
resistor values and the A3 Motherboard PCA, and also switches in guard circuits, 2-wire
mode compensation circuits, and other compensation circuits. These relays are latching
type and can be set or reset.
A3 Motherboard PCA connections are shown on Sheet 1 (8A-8D). K29 and K30 isolate
the ohms output and sense lines from the A3 Motherboard PCA. The HIGUARD signal is
switched through K25 and can be used to drive the shields of HI cables when the
Calibrator output is active. See the Guard Circuits section for more details.
2-14
Theory of Operation
A5 Ohms PCA 2
Out_Hi
Out_Lo
HiSRC
K29
K30
K37
K17
K15
K13,
14,16,
& 38
K39
K31
Z
3
K18,
19,
42, &
43
K41
F
K8,9,
& 10
Z
2
K32
K31
K11,
34, &
35
Z
2
K33
Comp_Out_Lo
Z
4
K7
K2
K7
K3
K20
Comp_Out_Hi
K12
K1
K27
K27
short
S
apv002.eps
K4
Z
1
Z
1
K5
Figure 2-3. A5 Ohms PCA High/Low Output
2-15
57LFC/AN
Service Manual
SNS_HI
HIGUARD
SNS_LO
K25
K26
K29
G
U
A
R
D
C
K
T
S
K30
BUFCOMPV
COMP_EXT_HI
K17
K36
K13
& 38
K31
K31
K39
K14
& 16
Z
3
K18
& 19
Z
4
COMP_OUT_LO
K8, 9,
& 10
K40
K32
K21
Z
2
K42
& 43
Z
4
K41
RCOM1
COMP_RES_LO
Z
3
Figure 2-4. A5 Ohms PCA High/Low Sense
K2
K3
K11,
34, &
35
K33
K23
K12
Z
1
Z
2
HI_CHK
COMP_RES_HI
K4
K5
K22
Z
1
LO_CHK
K6
K28
K28
short
apv003.eps
2-16
Theory of Operation
A5 Ohms PCA 2
Table 2-7 provides a functional description of the relay function for either the set or reset
condition on the A5 Ohms PCA. Table 2-8 provides information on the hardware control
map for the relays and shows the relay setting for each state. Table 2-9 shows the final
relay states by instrument state.
Table 2-7. Functional Description of A5 Ohms PCA Relays
Relay Functional Description
K1 Reset: Connect OHMS_OUT_LO to SGND
Set: Disconnect OHMS_OUT_LO from SGND
K2 Reset: Connect 1.9 Ω Z1 resistance to OHMS_OUT_HI and OHMS_SNS_HI
Set: Disconnect 1.9 Ω Z1 resistance from HI
K3 Reset: Connect 1.9 Ω Z1 resistance to OHMS_OUT_LO and OHMS_SNS_LO
Set: Disconnect 1.9 Ω Z1 resistance from LO
K4 Reset: Connect 1 Ω Z1 resistance to OHMS_OUT_HI and OHMS_SNS_HI
Set: Disconnect 1 Ω Z1 resistance from HI
K5 Reset: Connect 1 Ω Z1 resistance to OHMS_OUT_LO and OHMS_SNS_LO
Set: Disconnect 1 Ω Z1 resistance from LO
K6 Reset: Connect 19 Ω through 190 kΩ HI sense bus to OHMS_SNS_HI
Set: Disconnect 19 Ω through 190 kΩ HI sense bus from OHMS_SNS_HI
K7 Reset: Connect 10 Ω through 100 kΩ HI source bus to OHMS_OUT_HI
Set: Connect 19 Ω through 190 kΩ HI source bus to OHMS_OUT_HI
K8 Reset: Connect 1 kΩ Z2 resistance to OHMS_SNS_HI and 10 Ω through 100 kΩ HI
source bus
Set: Disconnect 1 kΩ Z2 resistance from HI
K9 Reset: Connect 100 Ω Z2 resistance to OHMS_SNS_HI and 10 Ω through 100 kΩ
HI source bus
Set: Disconnect 100 Ω Z2 resistance from HI
K10 Reset: Connect 10 Ω Z2 resistance to OHMS_SNS_HI and 10 Ω through 100 kΩ HI
source bus
Set: Disconnect 10 Ω Z2 resistance from HI
K11 Reset: Connect 1.9 kΩ Z2 resistance to 19 Ω through 190 kΩ HI sense and source
buses
Set: Disconnect 1.9 kΩ Z2 resistance from HI
K12 Reset: Connect OHMS_OUT_HI to COMP_OUT_HI and OHMS_SNS_HI to
COMP_RES_HI
Set: Disconnect OHMS_OUT_HI from COMP_OUT_HI and OHMS_SNS_HI from
COMP_RES_HI
K13 Reset: Connect 10 MΩ Z3 resistance to HI_OHMS_HI and HI_SNS_HI
Set: Disconnect 10 MΩ Z3 resistance from HI
K14 Reset: Connect 100 kΩ Z3 resistance to OHMS_SNS_HI and 10 Ω through 100 kΩ
HI source bus
Set: Disconnect 100 kΩ Z3 resistance from HI
2-17
57LFC/AN
Service Manual
K15 Reset: Connect 19 Ω through 190 kΩ HI source bus to HI_OHMS_HI
K16 Reset: Connect 10 kΩ Z3 resistance to OHMS_SNS_HI and 10 Ω through 100 kΩ
K17 Reset: Connect HI_SNS_HI to COMP_EXT_HI and HI_OHMS_HI to 2-wire comp
K18 Reset: Connect 1.9 MΩ Z4 resistance to HI_OHMS_HI and HI_SNS_HI
K19 Reset: Connect 19 MΩ Z4 resistance to HI_OHMS_HI and HI_SNS_HI
Table 2-7. Functional Description of A5 Ohms PCA Relays (cont.)
Relay Functional Description
Set: Disconnect 19 Ω through 190 kΩ HI source bus from HI_OHMS_HI
HI source bus
Set: Disconnect 10 kΩ Z3 resistance from HI
FGND
Set: Disconnect HI_OHMS_HI from FGND and connect COMP_EXT_HI to IZGRD
and not to HI_SNS_HI
Set: Disconnect 1.9 MΩ Z4 resistance from HI
Set: Disconnect 19 MΩ Z4 resistance from HI
K20 Reset: Connect HI_SRC to OHMS_OUT_HI
Set: Disconnect HI_SRC from HI
K21 Reset: Connect OHMS_SNS_LO to COMP_RES_LO
Set: Connect COMP_RES_LO to RCOM1 and not to OHMS_SNS_LO
K22 Reset: Connect OHMS_SNS_LO to LO_CHK
Set: Disconnect OHMS_SNS_LO from LO_CHK
K23 Reset: Connect OHMS_SNS_HI to HI_CHK
Set: Connect BUFHCOMPV to HI_CHK
K24 Reset: Short COMP_EXT_LO to COMP_OUT_LO
Set: Remove Short between COMP_EXT_LO and COMP_OUT_LO
K25 Reset: Connect A3 Motherboard PCA HIGUARD to ZGUARD drive
Set: Disconnect A3 Motherboard PCA HIGUARD from ZGUARD
K26 Reset: Connect HI_SNS_HI to input of ZGUARD amplifier
Set: Disconnect HI_SNS_HI from ZGUARD amplifier input
K27 Reset: Connect 0 Ω resistor (Short) to OHMS_OUT_HI and OHMS_OUT_LO
Set: Disconnect 0 Ω from HI and LO source
K28 Reset: Connect 0 Ω resistor (Short) to OHMS_SNS_HI and OHMS_SNS_LO
Set: Disconnect 0 Ω from HI and LO sense
2-18
K29 Reset: Connect A3 Motherboard PCA OUT_HI to HI_OHMS_HI and motherboard
SNS_HI to HI_SNS_HI
Set: Disconnect A3 Motherboard PCA OUT_HI and SNS_HI from HI_OHMS_HI and
HI_SNS_HI
Theory of Operation
Table 2-7. Functional Description of A5 Ohms PCA Relays (cont.)
Relay Functional Description
K30 Reset: Connect A3 Motherboard PCA OUT_LO to LO_OHMS_LO and motherboard
SNS_LO to LO_SNS_LO
Set: Disconnect A3 Motherboard PCA OUT_LO and SNS_LO from LO_OHMS_LO
and LO_SNS_LO
K31 Reset: Connect LO_SNS_LO to OHMS_SNS_LO and LO_OHMS_LO to
OHMS_OUT_LO
Set: Connect LO_SNS_LO to COMP_EXT_LO and LO_OHMS_LO to
COMP_OUT_LO
K32 Reset: Connect 10 Ω, 100 Ω, and 1 kΩ Z2 resistors to OHMS_SNS_LO and
OHMS_OUT_LO
Set: Disconnect 10 Ω, 100 Ω, and 1 kΩ Z2 resistors from LO
K33 Reset: Connect 19 Ω, 190 Ω, and 1.9 kΩ Z2 resistors to OHMS_SNS_LO and
OHMS_OUT_LO
Set: Disconnect 19 Ω, 190 Ω, and 1.9 kΩ Z2 resistors from LO
A5 Ohms PCA 2
K34 Reset: Connect 19 Ω Z2 resistance to 19 Ω through 190 kΩ HI sense and source
buses
Set: Disconnect 19 Ω Z2 resistance from HI
K35 Reset: Connect 190 Ω Z2 resistance to 19 Ω through 190 kΩ HI sense and source
buses
Set: Disconnect 190 Ω Z2 resistance from HI
K36 Reset: Connect OHMS_SNS_HI to HI_SNS_HI
Set: Disconnect OHMS_SNS_HI from HI_SNS_HI
K37 Reset: Connect 10 Ω through 100 kΩ HI source bus to HI_OHMS_HI
Set: Disconnect 10 Ω through 100 kΩ HI source bus from HI_OHMS_HI
K38 Reset: Connect 1 MΩ Z3 resistance to HI_OHMS_HI and HI_SNS_HI
Set: Disconnect 1 MΩ Z3 resistance from HI
K39 Reset: Connect 10 kΩ, 100 kΩ, 1 MΩ, and 10 MΩ Z3 resistors to OHMS_SNS_LO
and OHMS_OUT_LO
Set: Disconnect 10 kΩ, 100 kΩ, 1 MΩ, and 10 MΩ Z3 resistors from LO
K40 Reset: Connect 19 Ω through 190 kΩ HI sense bus to HI_SNS_HI
Set: Disconnect 19 Ω through 190 kΩ HI sense bus from HI_SNS_HI
K41 Reset: Connect 19 kΩ, 190 kΩ, 1.9 MΩ, and 19 MΩ Z4 resistors to OHMS_SNS_LO
and OHMS_OUT_LO
Set: Disconnect 19 kΩ, 190 kΩ, 1.9 MΩ, and 19 MΩ Z4 resistors from LO
K42 Reset: Connect 19 kΩ Z4 resistance to 19 Ω through 190 kΩ HI sense and source
buses
Set: Disconnect 19 kΩ Z4 resistance from HI
K43 Reset: Connect 190 kΩ Z4 resistance to 19 Ω through 190 kΩ HI sense and source
buses
Set: Disconnect 190 kΩ Z4 resistance from HI
2-19
57LFC/AN
Service Manual
K25 Set: Disconnects A3 Motherboard PCA HIGUARD from ZGUARD
K29 Set: Disconnects A3 Motherboard PCA OUT_HI and SNS_HI from HI_OHMS_HI
K30 Set: Disconnects A3 Motherboard PCA OUT_LO and SNS_LO from LO_OHMS_LO
K1 to K24 Undefined state (do not care)
K26 to K28 Undefined state (do not care)
K31 to K43 Undefined state (do not care)
Table 2-8. A5 Ohms PCA Power-up Fault Relay States
Relay State on Power-up or After Fault
and HI_SNS_HI
and LO_SNS_LO
2-20
Theory of Operation
Table 2-9. Final Relay States by Instrument State
f7bf
f7bf
f7b0
f7bb
f7b0
f7bb
f7b0
Hex
9
K2
5
K1 K2
0
K3
7
K1
1
K2
1
K3
K1
2
0
K2
3
K2
2
K2
4
K2
2
K3
3
K3
9
K3
1
K4
ORLY
K27,K2
6
K2
K2
,K
K4
,K
K9
,K
K10,K3
K18,K3
6,
8
3
5
35
4
8
2
K4
f7bb
e7b0
e7bb
d7b0
d7bb
e7b0
e7bb
d7b0
d7bb
A5 Ohms PCA 2
e7b0
e7bb
K6 K7 K1
7
K36,K3
0
K15,K4
3
K14,K4
9
K13,K1
11
,K
xssssrsrssssrsrsssssrssssrssrrrr7af5
-K8
84218421842184218421842184218421
xssssrsrssssrsrsssssrssssrsssrss7af5
xssssrsrsssssr rsssssrssssrssrrrr7af9
xssssrsrsssssr rsssssrssssrsssrss7af9
xssssrsrssrsssrssssr rssssrssrrrr7add
xssssrsrssrsssrssssr rssssrsssrss7add
xsssrssrssrsssrsssrsrssssrssrrrr76dd
xsssrssrssrsssrsssrsrssssrsssrss76dd
xssssrsrsssrssrssssr rssssrssrrrr7aed
xssssrsrsssrssrssssr rssssrsssrss7aed
xsssrssrsssrssrsssrsrssssrssrrrr76ed
xsssrssrsssrssrsssrsrssssrsssrss76ed
xrsssrsrssssssrssssr rssssrssrrrr3afd
xrsssrsrssssssrssssr rssssrsssrss3afd
Relay:
Register:
Relay (Virtual)
Inst. State \ Bit Weight:
Up
Powerxssssssrssssssssssssrssssrssssss7eff
Dormantxssssssrssssssssssssrssssrssssss7eff
4 Wire
Short,xssssrsrssssssr rssssrssssrssrrrr7afc
4 Wire, STBY
Short,xssssrsrssssssr rssssrssssrsssrss7afc
1 Ω, 4 Wire
1 Ω, 4 Wire, STBY
1.9 Ω, 4 Wire
1.9 Ω, 4 Wire, STBY
10 Ω, 4 Wire
10 Ω, 4 Wire, STBY
19 Ω, 4 Wire
19 Ω, 4 Wire, STBY
100 Ω, 4 Wire
100 Ω, 4 Wire, STBY
190 Ω, 4 Wire
190 Ω, 4 Wire, STBY
1 kΩ, 4 Wire
1 kΩ, 4 Wire, STBY
2-21
57LFC/AN
Service Manual
Table 2-9. Final Relay States by Instrument State (cont.)
Hex
9
K2
5
K1 K2
0
K3
7
K1
1
K2
1
K3
K1
2
0
K2
3
K2
2
K2
4
K2
2
K3
3
K3
9
K3
1
K4
ORLY
K27,K2
6
K2
K2
,K
K4
,K
K9
,K
K10,K3
K18,K3
6,
8
3
5
35
4
8
2
K4
d7b0
d7bb
b7b0
b7bb
77b0
77bb
b7b0
b7bb
77b0
77bb
b7b0
b7bb
77b0
77bb
b7b0
b7bb
77b0
77bb
2-22
Register:
Relay (Virtual)
K6 K7 K1
K36,K3
K15,K4
K14,K4
K13,K1
,K
-K8
Relay:
7
0
3
9
11
xrssrssrssssssrsssrsrssssrssrrrr36fd
xrssrssrssssssrsssrsrssssrsssrss36fd
84218421842184218421842184218421
Inst. State \ Bit Weight:
1.9 kΩ, 4 Wire
1.9 kΩ, 4 Wire, STBY
xssssrsr rsssssrssrssrssssrssrrrr7a7d
10 kΩ, 4 Wire
xssssrsr rsssssrssrssrssssrsssrss7a7d
10 kΩ, 4 Wire, STBY
xsssrssr rsssssrsrsssrssssrssrrrr767d
19 kΩ, 4 Wire
xsssrssr rsssssrsrsssrssssrsssrss767d
19 kΩ, 4 Wire, STBY
xssrsrsrssssssrssrssrssssrssrrrr6afd
100 kΩ, 4 Wire
xssrsrsrssssssrssrssrssssrsssrss6afd
100 kΩ, 4 Wire, STBY
xssrrssrssssssrsrsssrssssrssrrrr66fd
190 kΩ, 4 Wire
xssrrssrssssssrsrsssrssssrsssrss66fd
190 kΩ, 4 Wire, STBY
xssssssrsrssssrssrssrssssrssrrrr7ebd
1 MΩ, 4 Wire
xssssssrsrssssrssrssrssssrsssrss7ebd
1 MΩ, 4 Wire, STBY
xssssssrsrssssrsrsssrssssrssrrrr7ebd
1.9 MΩ, 4 Wire
xssssssrsrssssrsrsssrssssrsssrss7ebd
1.9 MΩ, 4 Wire, STBY
xsrssssrssssssrssrssrssssrssrrrr5efd
10 MΩ, 4 Wire
xsrssssrssssssrssrssrssssrsssrss5efd
10 MΩ, 4 Wire, STBY
xsrssssrssssssrsrsssrssssrssrrrr5efd
19 MΩ, 4 Wire
xsrssssrssssssrsrsssrssssrsssrss5efd
19 MΩ, 4 Wire, STBY
Theory of Operation
Table 2-9. Final Relay States by Instrument State (cont.)
ff4b
ff40
9
K2
5
K1 K2
0
K3
7
K1
1
K2
1
K3
K1
2
0
K2
3
K2
2
K2
4
K2
2
K3
3
K3
9
K3
1
K4
ORLY
K27,K2
6
K2
K2
,K
K4
,K
K9
,K
K10,K3
K18,K3
6,
8
3
5
35
4
8
2
K4
ff40
ff4b
ff4b
ef40
ef4b
df40
df4b
ef40
ef4b
df40
df4b
ef40
ef4b
df40
A5 Ohms PCA 2
bf40
bf4b
df4b
K6 K7 K1
7
K36,K3
0
K15,K4
3
K14,K4
9
K13,K1
11
,K
xssssssrsssrssrssssrssssrsr rrrrr7eed
xssssssrsssrssrssssrssssrsr rsrss7eed
xsssssrssssrssrsssrsssssrsrrrrrr7ded
xsssssrssssrssrsssrsssssrsrrsrss7ded
xrsssssrssssssrssssrssssrsr rrrrr3efd
-K8
xssssssrssssrsrsssssssssrsr rrrrr7ef5
xssssssrssssrsrsssssssssrsr rsrss7ef5
xssssssrsssssrrsssssssssrsr rrrrr7ef9
xssssssrsssssrrsssssssssrsr rsrss7ef9
xssssssrssrsssrssssrssssrsr rrrrr7edd
xssssssrssrsssrssssrssssrsr rsrss7edd
xsssssrsssrsssrsssrsssssrsrrrrrr7ddd
xsssssrsssrsssrsssrsssssrsrrsrss7ddd
xrsssssrssssssrssssrssssrsr rsrss3efd
xrssssrsssssssrsssrsssssrsr rrrrr3dfd
xrssssrsssssssrsssrsssssrsr rsrss3dfd
xssssssr rsssssrssrssssssrsr rrrrr7e7d
xssssssr rsssssrssrssssssrsr rsrss7e7d
Relay:
Register:
Relay (Virtual)
Inst. State \ Bit Weight: 84218421842184218421842184218421Hex
Table 2-9. Final Relay States by Instrument State (cont.)
7f4b
bf40
bf4b
7f40
7f40
9
K2
5
K1 K2
0
K3
7
K1
1
K2
1
K3
K1
2
0
K2
3
K2
2
K2
4
K2
2
K3
3
K3
9
K3
1
K4
ORLY
K27,K2
6
K2
K2
,K
K4
,K
K9
,K
K10,K3
K18,K3
6,
8
3
5
35
4
8
2
K4
7f4b
d0bb
d0bb
d0bb
70bb
70bb
b0bb
70bb
b0bb
70bb
0000
0000
2-24
K6 K7 K1
K36,K3
K15,K4
K14,K4
K13,K1
-K8
Register:
Relay (Virtual)
,K
Relay:
7
0
3
9
11
xsssrsrsrsssssrsrsssrrr rsrsssrss757d
xsssssrsrsssssrsrsssssssrsr rrrrr7d7d
xsssssrsrsssssrsrsssssssrsr rsrss7d7d
xssrsssrssssssrssrssssssrsr rrrrr6efd
xssrsssrssssssrssrssssssrsr rsrss6efd
xssrssrsssssssrsrsssssssrsr rrrrr6dfd
xssrssrsssssssrsrsssssssrsr rsrss6dfd
Inst. State \ Bit Weight: 84218421842184218421842184218421Hex
19 kΩ, 2W Comp
19 kΩ, 2W Comp, STBY
100 kΩ, 2W Comp
100 kΩ, 2W Comp, STBY
190 kΩ, 2W Comp
190 kΩ, 2W Comp, STBY
xsssrsrsssrsssrsssrsrrrrsrsssrss75dd
DIAG, 19 Ω, 4 Wire
xsssrsrssssrssrsssrsrrrrsrsssrss75ed
DIAG, 190 Ω, 4 Wire
xrssrsrsssssssrsssrsrrr rsrsssrss35fd
DIAG, 1.9 kΩ, 4 Wire
xssrrsrsssssssrsrsssrrr rsrsssrss65fd
xssssrsrsrssssrssrssrrr rsrsssrss7abd
xsssrsrssrssssrsrsssrrr rsrsssrss75bd
xsrssrsrssssssrssrssrrr rsrsssrss5afd
DIAG, 19 kΩ, 4 Wire
DIAG, 190 kΩ, 4 Wire
DIAG, 1 MΩ, 4 Wire
DIAG, 1.9 MΩ, 4 Wire
DIAG, 10 MΩ, 4 Wire
xsrsrsrsssssssrsrsssrrr rsrsssrss55fd
DIAG, 19 MΩ, 4 Wire
xxxxxxxxxxxxxxxxxxxxxr rrxxxxxxxx0000
DIAG, Any Ω, 2/4 W,
Measure Ivref, LO, HI, or
Vcompl (use mod mask
xxxxxxxxxxxxxxrxxxxxxxxxxxxxxxxx0000
00000700h)
Connect Guard Amp and
measure Vcompl (use mod
DIAG, Any Ω, 2/4 W,
mask 00020000h)
Theory of Operation
Table 2-9. Final Relay States by Instrument State (cont.)
fff7
9
K2
5
K1 K2
0
K3
7
K1
1
K2
1
K3
K1
2
0
K2
3
K2
2
K2
4
K2
2
K3
3
K3
9
K3
1
K4
ORLY
K27,K2
6
K2
K2
,K
K4
,K
K9
,K
K10,K3
K18,K3
6,
8
3
5
35
4
8
2
K4
A5 Ohms PCA 2
K6 K7 K1
7
K36,K3
0
K15,K4
3
K14,K4
9
K13,K1
11
,K
-K8
Relay:
Register:
Relay (Virtual)
Motherboard relay.
Key: x = don’t care, r = reset, s = set
Notes
• When sourcing a resistance, K25, K29, and K30 are reset after all other relays have been put into position.
• When entering STBY, K25, K29, and K30 are set first.
• Four Wire and two Wire (No Comp) use the same ORLY values. 4 Wire uses Remote Sense and 2 Wire (No Comp) uses Internal Sense, as selected by a
Inst. State \ Bit Weight: 84218421842184218421842184218421Hex
LO Comp, (V dc, V ac, etc.)xssssssrssssssssssssssssssssrsss7eff
• Two wire comp works only to 190 K.
2-25
57LFC/AN
Service Manual
Other Control Circuits
ENCOMPFAULT* Connects the divided and buffered SNS_HI compliance voltage to the circuit that
CKEXTRA* Not used.
CKCOMPV* Connects the divided and buffered SNS_HI voltage to the SMUX line when
CKLO* Connects the LO_CHK output from relay K22 to the SMUX line when asserted
Other controls on the A5 Ohms PCA are used for selecting a number of different
parameters. Table 2-10 lists the name of the other control signals and provides a
functional description. The control signals are driven by U39 and U35 as shown on Sheet
4 of the A5 Ohms PCA schematic.
Table 2-10. Functional Description of Signals
Signal Functional Description
will pull down the INS-HI line if the voltage exceeds +/-33.5 V when asserted
Low.
asserted Low.
Low.
CKHI* Connects the HI_CHK output from relay K23 to the SMUX line when asserted
Low.
CKIVREF* Connects the IVREF voltage to the SMUX line when asserted Low.
INRCOM* Connects the RCOM1 line to the IVREF ground reference buffer when asserted
Low.
INIVREF* Connects the I_ACDC and the IFBCK lines to the IVREF control amplifier when
asserted Low.
ZIVREF* Selects 0 V to the IVREF control amplifier when asserted low to select zero
output current. ZIVREF* should only be asserted when INIVREF* is de-asserted.
ISELHNA* Selects the Hundreds of nano-Amp current source output when asserted Low.
ISELUA* Selects the Micro-Amp current source output when asserted Low.
ISELTUA* Selects the Tens of Micro-Amp current source output when asserted Low.
ISELHUA* Selects the Hundreds of Micro-Amp current source output when asserted Low.
ISELMA* Selects the Milli-Amp current source output when asserted Low. This is the
normal default ISEL line. Only one of the ISEL lines is normally asserted at one
time.
Guard Circuits
The U40 guard amplifier circuit drives IZGRD, ZGUARD, and also HIGUARD (see A3
Motherboard PCA pins A29 and C29) whenever the instrument is put in Operate for
ohms. IZGRD also drives the shield to T1 shown on Sheet 2 of the A5 Ohms PCA
schematics. Since HIGUARD is connected to the I-GUARD terminal, the guard amp
drives that terminal plus whatever is connected to it as well. In Standby, HIGUARD is
not driven. For volts, HIGUARD is shorted to GUARD, so that output terminal IGUARD is connected to and driven by V-GUARD. The circuitry around U40, including,
Q6, R58-61, VR3, C93, VR4, and K46 provide capacitive load compensation and
regulate the 45 V supply from the A3 Motherboard PCA to about +/-6 V referenced to
SNS.HI.
2-26
Theory of Operation
A5 Ohms PCA 2
Compensation Circuits
In addition to four-wire ohms and two-wire ohms, the user can also select to have twowire compensated ohms where amplifiers and floating supplies are used to negate most of
the effects of path loss associated with a two terminal resistance measurement instrument.
Sheet 2 contains the compensation circuits for the HI and LO paths. HI compensation
(COMP_OUT_HI) is controlled by U19 with inputs from either the internal resistance
(COMP_RES_HI) and the external HI (COMP_EXT_HI). U20 provides the drive
capability. Similarly, U17 and U41 control the low compensation output
(COMP_OUT_LO). Relay K24 shorts the low compensation current inputs when not in
use. The maximum output compensation current exceeds 100 mA. The low compensation
circuit is referenced to SCOM while the high compensation circuit is referenced to
FCOM. The 2 Wire Comp sense, either internal or remote, is selected by a A3
Motherboard PCA relay.
The floating power supply used to power the HI compensation circuit is also shown on
Sheet 2 of the A5 Ohms PCA schematic. The floating +3.75/-5 V power supply is
generated by transformer T1, full wave rectifier bridge CR4, and a number of 1000 uF
capacitors, as regulated by Q1, Q2, U24 and associated components. VR1 along with the
R23/ R20 resistor divider set the positive regulator output. VR1 along with R30, R18,
R16, and R19 set the negative regulator output.
Monitor
The embedded software continually monitors specific hardware aspects when in operate.
In ohms, monitoring protects the instrument from damage and particularly the highperformance Fluke resistor networks from damage. This is accomplished by checking the
compliance voltage against the appropriate limit on a regular basis. Short-term overloads
below the hardware trip threshold will be allowed, while longer-period over-compliance
voltages will cause the instrument to go to Standby.
Whenever sourcing a resistance:
• ENCOMPFAULT* line will be asserted so that excessive compliance voltages
(above +-33 V) will quickly cause the hardware to trip out the instrument.
• The compliance voltage is measured regularly using the SMUX line when in Operate.
The absolute value of the measurement is internally compared with the SMUX limit
given in Table 2-12 for the appropriate resistance output. If too many consecutive
measurements exceed the limit, meaning the compliance voltage has been too high
for over 2.5 seconds, then the software will generate an over-compliance error and
put the instrument into Standby.
2-27
57LFC/AN
Service Manual
Table 2-11. Compliance Voltage Thresholds
Output Resistance
Max Vcompliance
V dc
Max BUFHCOMPV
V dc
SMUX Limit V dc
0 Ω 0 0 0.010
1.0 Ω 0.14 0.047 0.05
1.9 Ω 0.28 0.093 0.10
10 Ω 0.14 0.047 0.05
19 Ω 0.28 0.093 0.10
100 Ω 1.41 0.47 0.5
190 Ω 2.83 0.94 1.00
1.0 kΩ 2.83 0.94 1.00
1.9 kΩ 4.24 1.413 1.50
10 kΩ 14.14 4.714 5.00
19 kΩ 7.07 2.357 5.00
100 kΩ 14.14 4.714 5.00
190 kΩ14.14 4.714 10.0
1.0 MΩ 28.28 9.427 10.0
1.9 MΩ 28.28 9.427 10.0
10 MΩ 28.28 9.427 10.0
19 MΩ 28.28 9.427 10.0
2-28
Theory of Operation
A5 Ohms PCA 2
Diagnostics
Diagnostics which may be executed as a remote command, check that the relays are
working, and that each of the resistances is close to its calibrated value. If problems are
found, an error message is printed. The error messages can be found in Appendix A of
the 57LFC/AN Operators Manual. Table 2-12 lists a few of the relay settings after a
power up.
Ohms diagnostics work as follows for each resistance in turn:
• Sets the relays (see Table 2-8, ORLY) to the DIAG state for the resistance desired.
• Set the OTEST register for the test current desired based on Table 2-14.
• Set the I_ACDC DDS output voltage to be that for the proper test current shown in
the Table 2-14.
• Set the OCHK register (see Table 2-13) to the DIAG state for measuring Ivref, and
measure the SMUX line.
• Next, set the OCHK register to the DIAG state for measuring LO, and measure the
SMUX line. This reading should be less than the limit given in the Table 2-14. If not,
there is likely a relay or resistor problem. Save this reading for subtracting from the
following HI measurement.
• Next, set the OCHK register to the DIAG state for measuring HI, and measure the
SMUX line. Subtract the LO reading, divide by the Ichk current, and compare the
resistance with the calibration value. The difference should a couple percent. If the
difference is too large, there’s likely a relay, resistance, or diagnostic circuit problem.
2-29
57LFC/AN
Service Manual
Control Register: OTEST
Table 2-12. OTEST Register States by Instrument State
Signal: ISEL-
Instrument State \ Bit
MA*
8 4 2 1 8 4 2 1 Hex
ISEL-
HUA*
ISEL-
TUA*
ISEL-
UA*
ISEL-
HNA*
ZIVR
EF*
IN-
IVREF*
IN-
RCO
M*
Weight:
DormantL h h h h L h h 7b
Any non-Ω function L h h h h L h h 7b
Any Ω, 2/4 W, Oper or
L h h h h L
h h 7b
STBY or Measure
Vcompl
DIAG, 1.5 to 3.3 mA
L h h h h h L L 7c
Ichk
DIAG, 150 to-330 µA
h L h h h h L L bc
Ichk
DIAG, 15 to 33 µA
h h L h h h L L dc
Ichk
DIAG, 1.5 to 3.3 µA
h h h L h h L L ec
Ichk
DIAG, 150 to 330 nA
h h h h L h L L f4
Ichk
Key: x = don’t care, h = high (off, de-asserted), L = low (on, asserted)
2-30
Table 2-13. OCHK Register States by Instrument State
Control Register: OCHK
Signal: - -
Instrument State \ Bit
CK-
IVREF*
8 4 2 1 8 4 2 1 Hex
CKHI* CKLO* CK-
COMP-
V*
CK-
EXTRA*
EN-
COMP-
FAULT
*
Weight:
Dormant x x h h h h h h 3f
Any non-Ω function x x h h h h h h 3f
Any Ω, 2/4 W x x h h h h h L 3e
Any Ω, 2/4 W, STBY x x h h h h h h 3f
Any Ω, 2/4 W,
x x h h h L h L 3a
Measure Vcompl
DIAG, Any Ω,
x x L h h h h h 1f
Measure Ivref
Theory of Operation
Table 2-13. OCHK Register States by Instrument State (cont.)
Control Register: OCHK
Signal:
- - CK-
IVREF*
CKHI* CKLO* CK-
COMP-
V*
CK-
EXTRA*
EN-
COMP-
FAULT
A5 Ohms PCA 2
*
Instrument State \ Bit
8 4 2 1 8 4 2 1 Hex
Weight:
DIAG, Any Ω,
x x h h L h h h 37
Measure LO
DIAG, Any Ω,
x x h L h h h h 2f
Measure HI
DIAG, Any Ω,
x x h h h L h h 3b
Measure Vcompl
Key: x = don’t care, h = high (off, de-asserted), L = low (on, asserted)
Notes:
•Only one of the CKx lines can be asserted low at a time to switch a signal onto the SMUX line for
measurement
2-31
57LFC/AN
Service Manual
Table 2-14. Diagnostic Values by Instrument State
Instrument State Test
Ichk IDAC
Current
(X2)
Vdc Hex SMUX
OTES
T Reg
Ivref LO Limit Nominal HI
Vdc
SMUX
Vdc
SMUX Vdc
Dormant 0 mA - 7b - - -
Any non-Ω function 0 mA - 7b - - -
Any Ω, 2/4 W, Oper or STBY or
0 mA - 7b - - -
Monitor Comp or Msr Vcompl
DIAG, 0 Ω, Check Ivref, LO, or HI 3 mA 6.0 7c 3.000 0.001 <.0017
DIAG, 1 Ω, Check Ivref, LO, or HI 3 mA 6.0 7c 3.000 0.001 0.003
DIAG, 1.9 Ω, Check Ivref, LO, or HI 3 mA 6.0 7c 3.000 0.001 0.0057
DIAG, 10 Ω, Check Ivref, LO, or HI 3 mA 6.0 7c 3.000 0.001 0.030
DIAG, 19 Ω, Check Ivref, LO, or HI 3 mA 6.0 7c 3.000 0.001 0.057
DIAG, 100 Ω, Check Ivref, LO, or HI 3 mA 6.0 7c 3.000 0.001 0.300
DIAG, 190 Ω, Check Ivref, LO, or HI 3 mA 6.0 7c 3.000 0.001 0.570
DIAG, 1 kΩ, Check Ivref, LO, or HI 2 mA 4.0 7c 2.000 0.001 2.00
DIAG, 1.9 kΩ, Check Ivref, LO, or HI 2 mA 240 7c 2.000 0.001 3.80
DIAG, 10 kΩ, Check Ivref, LO, or HI 0.2 mA 4.0 bc 2.000 0.0001 2.00
DIAG, 19 kΩ, Check Ivref, LO, or HI 0.2 mA 4.0 bc 2.000 0.0001 3.80
DIAG, 100 kΩ, Check Ivref, LO, or HI 20 µA 4.0 dc 2.000 0.0001 2.00
DIAG, 190 kΩ, Check Ivref, LO, or HI 20 µA 4.0 dc 2.000 0.0001 3.80
DIAG, 1 MΩ, Check Ivref, LO, or HI 3 µA 6.0 ec 3.000 0.0001 3.00
DIAG, 1.9 MΩ, Check Ivref, LO, or HI 3 µA 6.0 ec 3.000 0.0001 5.70
DIAG, 10 MΩ, Check Ivref, LO, or HI 300 nA 6.0 f4 3.000 0.0001 3.00
DIAG, 19 MΩ, Check Ivref, LO, or HI 300 nA 6.0 f4 3.000 0.0001 5.70
Key: - = doesn’t apply
Notes:
1. +-30 mV, +-300 mV, +-12 V full-scale can be measured on the SMUX line.
2. 0 to +/-3.3 V is the range of voltages that can be output on I_ACDC.
2-32
Theory of Operation
A6 Digital Synthesis PCA 2
A6 Digital Synthesis PCA
The A6 Digital Synthesis PCA contains the following functional blocks:
• Precision, dual tracking, +/-7 V references
• Two precision, 28 bit, pulse width modulated, digital to analog converters (DAC's)
• A 0.33 V – 1000 V sense divider and buffer amplifier
• Two ac/dc averaging converters
• Two amplitude control loops, for dual channel operation
• An 18 bit analog to digital (A/D) converter with input mux and variable gain
amplifier
• A thermocouple based temperature sourcing and measuring circuit
• Digital control circuitry consisting of octal latches, relay drivers, and a high speed
serial link to the main CPU.
These functional blocks, when used with the A8 High Voltage PCA, and/or A7 Current
PCA, provide single or dual channel ac/dc V/A/W, offset table and nonsinusoidal
waveforms, duty cycle, temperature measuring and sourcing, internal calibration and
diagnostics, and digital control over all the analog assemblies. A brief description of each
block is described below.
Precision, Dual Tracking, +/-7 V References
Refer to Sheet 2 of the A6 Digital Synthesis PCA schematic.
The reference circuit is based on the ref amp set used in the 8842A. Reference amplifier,
Q1, and op amp, U38, along with Z3 and Z4 generate a trimmed -7 V reference. This
reference is inverted by a flying capacitor inverter circuit consisting of U76, C60 and
C74, and buffered by U27. Each reference is also buffered by a discrete output stage; Q4
& Q5.
Precision, 28bit, PWM, Dual DAC's
Refer to Sheet 2 of the A6 Digital Synthesis PCA schematic.
Since the two precision DAC's are identical, only the voltage channel DAC will be
described. This DAC design uses pulse width modulation (PWM) to convert a digital
value to a precise analog voltage. The duty cycle is generated by programmable counter
logic contained in an FPGA, U5. The counters are 14 bit binary, operating off of the
10Mhz clock, generating a variable duty factor pulse train at a frequency of 610.3515Hz.
The duty cycle has a resolution of 1 part in 16384 (14bits).
This variable duty cycle is complemented and deskewed by a D flip flop and outputted
from the FPGA as DAC1PREF and DAC1NREF, driving the gate pins of a quad analog
switch, U45. U45 alternately connects the input of the DAC filter, Z10, to the +/-7 V
references. The output of this filter which consists of Z10, R75,R76, U28, and C76-78,
will have a voltage equal to the average value of the voltage at its input.
VDC = (D-.5)*14
and
D = N/16384 where N is the value that the timer is programmed to.
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57LFC/AN
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DC Voltage Operation
U52 and Z10 are used to cancel the resistance of U45, while U58 and Z2 buffer the
output and divide it by two.
To obtain an additional 14bits of resolution, another PWM channel is generated and
output at U18-12. This signal is inverted by U19A, divided by R70, R72, and R73, and
summed into the filter at C76.
Refer to Sheet 3 of the A6 Digital Synthesis PCA schematic.
In the 3.3 V dc range the VDAC output from Z2 is applied to the non-inverting input of
the control loop integrator, U60. The output of U60 is inverted by U87B and is buffered
by the 3.3 V output amp, U42, and switched to VMID by K8. VMID is switched to the
instrument output by the A3 Motherboard PCA relay A3-K3. This output is sensed by
NSNS_HI and switched to VDIV by A3-K2. VDIV is applied to the sense divider, Z5, by
K3. The composite sense amplifier, U57 and U21, invert the sense signal which is then
applied to the inverting input of U60. The net result is an instrument output dc voltage
that is equal to -VDAC.
The 33 V dc range operates in a similar way, except the inverting amp, U87B, is
bypassed by switch U48D and the output of U42 is amplified and inverted by the A8
High. The output of the A8 High Voltage PCA is applied to VMID and the 33 V sense
input is selected by K2.
The 330 m V dc range does not use the sense divider/amplifier, but instead receives its
feedback through analog switch U15A. U87B is bypassed in this range so there is no
inversion in this mode of operation. The output of U42 is then divided by 10 by Z8, with
the output of Z8 connected to VMID by K7.
The 330 V dc and 1000 V dc ranges are generated by rectifying a high voltage ac signal.
First the output of U25, a DDS generated 2kHz square wave, is switched to the input of
U42 by switch U48C. This square wave is amplified, stepped up, rectified and filtered by
the A8 High Voltage PCA to approximately the desired dc voltage. This dc voltage is
then connected to VDIV for connection to the instrument output and for sensing. In the
case of the 330 V range, VDIV is connected to the sense divider/amplifier by K1. In the
1000 V range, U98 is used to invert the signal on VDIV. This divided voltage is applied
to U60, which generates an error signal. This error signal is fed back to U49 (Sheet 1 of
the A6 Digital Synthesis PCA schematic) for inversion and amplification before being
applied to the multiplying reference pin of the DDS waveform generation DAC, U13.
The voltage at this pin controls the amplitude of the ac square wave, thus adjusting the dc
voltage to exactly the desired value.
DDS Waveform Generation
Refer to Sheets 1 and 8 of the A6 Digital Synthesis PCA schematic.
Direct digital synthesis was first used at Fluke in the modulation oscillator of the 6080A
synthesized signal generator. It uses a high speed waveform reconstruction DAC, digital
phase accumulator, and a waveform lookup table to generate repetitive ac signals of
arbitrary waveform. A modified and improved circuit, based on the same technique is
contained in the FPGA, U5. The DDS circuit uses a 40 phase accumulator and uses
SRAM, U1 to store the wave tables. Each memory location in the SRAM wave table
corresponds to a phase. The value of each location in the wave table is the instantaneous
amplitude value of the waveform for that particular phase. As the phase accumulator
sequences through address locations the amplitude data is routed to the 16 bit DDS
DAC's (U13, U44) where, point by point, the waveform is generated.
2-34
Theory of Operation
A6 Digital Synthesis PCA 2
The FPGA splits the addresses into two channels where the address of the secondary
channel can be offset from the first, thereby causing a phase difference between the two.
It also provides logic for writing the waveform data to the table.
The differential output current of the primary DDS DAC (U13) is converted to a voltage
of about 9.7 V p-p by R41,R47 and U4. It is then filtered to remove glitches and clock
feed thru and adjusted in amplitude by the scaling DAC, U53 & U25. This voltage can be
further adjusted by adjusting the current flowing into U13's IREFIN pin. This is done by
amplifying the control loop error voltage by an amount inversely proportional the scaling
DAC's attenuation and applying it through R11 to the U13 pin 24.
The secondary DDS channel works in a similar way.
AC Voltage Operation
Refer to Sheet 3 of the A6 Digital Synthesis PCA schematic.
The output of the primary DDS channel is routed to the 3.3 V output amplifier, U42,
through switch U48. This amplified/divided, outputted and sensed the same as for V dc
except instead of the sense amplifier output being applied to the loop integrator, it is first
converted to a dc voltage by an average responding ac/dc converter, U40, U20, Q2, Q3,
CR5, U39. This dc voltage is filtered and buffered by U84 and U3, and switched into the
loop integrator by U15. As in dc the loop integrator reference pin has the VDAC signal
on it. The difference between the VDAC and the output of the averaging converter is
integrated and applied to the DDS DAC IREFIN pin. This adjusts the output voltage of
the DDS DAC, U13, until the difference is zero.
DC Current Operation
Refer to Sheets 2 and 4 of the A6 Digital Synthesis PCA schematic.
In all the dc current ranges the IDAC output from Z1 is applied to the noninverting input
of the control loop integrator, U9. The output of U9 is switched to I_AC/DC by U33A.
This signal is converted to a high impedance current source by the transconductance
amplifier on the A7 Current PCA. This current is routed to the AUX HI output and flows
through the UUT, returning into AUX LO terminal. It then passes through a shunt on the
A7 Current PCA, converting it back into a voltage, I_FBK. I_FBK is switched to the
inverting input of U9 by U31, which integrates the difference between its two inputs,
forcing them to be equal.
AC Current Operation
In all the ac current ranges, the second DDS channel from U34 is switched to I_ACDC
by U33C. This signal is converted to a current, outputted, and fed back on I_FBK the
same way as for dc currents. In AC, I_FBK is switched to the input of U14B where it is
rectified and filtered by U14A, CR1, U84A and U3 before it is switched into the negative
input of the error integrator, U9. U9 integrates the difference between this feedback
signal and the IDAC output, generating an error signal. This error signal is amplified by
the loop compensation DAC, U47, and U90 and then routed to the reference pin of the
DDS waveform DAC, U44, adjusting the output until the difference between the inputs
of U9 is zero.
Thermocouple Temperature Measurement
Thermocouples consist of a pair of wires that are each made of different metals or alloys.
On one end of this pair, the wires are electrically connected to each other. The other end
is terminated to copper contacts fastened to an isothermal block. The voltage produced at
the iso-thermal block is a function of the thermocouple type and the temperature
2-35
57LFC/AN
Service Manual
Iso-thermal Block Reference Junction Temperature Measurement
Thermocouple Voltage Measurement:
difference between the iso-thermal block and the end of the wire pair. Thus, to measure
the temperature of a thermocouple, its voltage, and the temperature of the iso-thermal
block must be measured.
Refer to Sheet 5 of the A6 Digital Synthesis PCA schematic.
The iso-thermal block contains two copper buttons to connect to the thermocouple plug, a
precision 10 kΩ bead themistor glued between the buttons, and a 6-layer PWB. It is
constructed to maintain as low a temperature difference between the buttons and the
transistor as possible. The thermistor is biased with a programmable current sink via
TC_ISO_SRC. This current sink consists of U97, U6, R108, R126, and R127 and
provides about 10 µA, developing about 1 V across the thermistor. The voltage of the
themistor is measured by connecting TC_ISO to the A/D input with U82A.
The thermocouple voltage is multiplied by 10 on the A10 Isothermal PCA. It is then
switched into the A/D by U82. The A7A10 Isothermal PCA is assembled and tested as
part of the A7 Current PCA.
Thermocouple Temperature Simulation
All that is required to simulate a thermocouple is source a voltage that would be
generated by a thermocouple at that temperature. The reference junction is measured to
determine the temperature of the isothermal block. Then this temperature and the
requested temperature are used to determine the correct output voltage. This voltage is
generated by the 3.3 DC range, buffered by U13 and divided by 10 on the A10 Isothermal
PCA before being outputted on the thermocouple connector.
Analog to Digital Converter
Refer to Sheet 4 on the A6 Digital Synthesis PCA schematic.
All internal calibration and diagnostic measurements are buffered by a gain
programmable instrumentation amplifier, U10. The gain of this amplifier is selected by
closing U82D (X10), closing U82C (/40), or by leaving both open (X1). The output of
U10 is applied to the A/D, U30 where it is converted into a digital value to be read by the
micro-controller.
Fault Detection
Refer to Sheet 7 of the A6 Digital Synthesis PCA schematic.
In order to minimize damage caused by misuse, abuse, component malfunction, or
software errors, a fault detection circuit was incorporated into the Calibrator. It consists
of a set/reset fault latch, a power MOSFET for driving reset coils, and various fault
detecting comparators. On the A6 Digital Synthesis PCA, the only kind of faults detected
are destructive voltages present at the instrument output during voltage mode operation.
This type of fault is detected with a window comparator, U50, that monitors the output of
the sense buffer, U21. When the output of U21 exceeds +/-10 V the output of U50 goes
low, setting the fault latch, U16. The output of the fault latch sets the signal CLR_DRVR
hi, disabling all the latching relay drivers, and turns on Q6, which resets all the latching
relays connected to REL_RST*. The fault latch also signals the FPGA of a fault
condition via the IG_FAULT signal, allowing the software to respond appropriately. In
the case of the DDS assembly, a fault condition disconnects all DDS relays that are
connected to the output.
2-36
Theory of Operation
The FAULT*, REL_RST*, and CLR_DRVR signals are also routed to the A3
Motherboard PCA, allowing any other assembly to detect and respond to any abnormal
conditions as needed.
Digital Control
Refer to Sheet 8 of A6 Digital Synthesis PCA schematic.
The inguard analog circuitry is controlled through an FPGA, U5. U5 contains a
1 megabit/s serial link, a serial to parallel shift register, and a state machine to provide a
microprocessor style data, address and control signals. U5 also incorporates six PWM
circuits for DAC's and a two channel DDS circuit with phase adjust and phase error
measurement. There are also some general purpose registers for control of the analog
circuitry.
A7 Current PCA 2
A7 Current PCA
Figure 2-4 shows the operation of DC current functions. The DC input signal to the A7
Current PCA comes from the A6 Digital Synthesis PCA on the I_ACDC line. The signal
is generated by a high resolution digital-to-analog-converter (IDAC), buffered by
amplifier U58, divided by Z1, and applied to the positive input of amplifier U9.
The output of U9 is the I_ACDC signal. The negative input of U9 is connected to the
IFBK line, which is the feedback from the shunt amplifier on the A7 Current PCA. In
operation the IFBK signal must be equal to the IDAC_OUT signal. If it is not equal, the
output of U9 changes the I_ACDC signal to adjust the A7 Current PCA output to make
them equal.
The I_ACDC signal is switched by U25 to provide the I_ACDC_SW input to U18. The
output of U18 is buffered and applied to one of the three transconductance output
amplifiers. The low current amplifier provides the 220 µA and 2.2 mA ranges. The mid
current amplifier provides the 22 mA and 220 mA ranges. The high current amplifier
provides the 2.2 A range.
The output current is driven through the load connected to the OUT_HI and OUT_LO
terminals and returned through the shunt resistors. The differential shunt amp amplifies
the voltage developed across the shunt resistors and generates the IFBK feedback signal
to the A6 Digital Synthesis PCA as noted above and also to U18 amplifier. When IFBK
and I_ACDC_SW signals at the input to U18 are equal the system is in balance providing
the correct output current.
Figure 2-5 shows the operation of ac current functions. Operation of the ac current
function is similar to dc operation except the signal provided on the I_ACDC line is an ac
signal generated by the DDS and scaling DACs on the A6 Digital Synthesis PCA. The ac
feedback on the IFBK line is buffered by U14 and converted to DC by the averaging ac
converter before it is applied to U9 on the A6 Digital Synthesis PCA.
2-37
57LFC/AN
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A6
A7
57LFCDC Current
IFBK
U31
TP9
I_ACDC
U33
R14
C63
U9
U58
+
Z1
14k
-
+
Z1
14k
IDAC
I_ACDC
IFBK
U25
R3
U18U25
+
-
C117
Shunt Amp
U48, U52,
U53, U33
Low Current Amplifier
OUT_HI
2GND
Mid Current Amplifier
IGND
High Current Amplifier
IGND
OUT_LO
+
-
Shunt
Resitors
SGND
2-38
IGND2GND
Figure 2-5. DC Current Functions
apv014f.eps
Theory of Operation
A7 Current PCA 2
57LFCAC Current
A6
IFBK
A7
R3
TP9
I_ACDC
U14
+
-
R17
DDS
U17
U25
Averaging
Converter
R3
Scaling
DAC
U47
U18
+
-
C117
U31
Scaling
DAC
U56
Current
_Error
R14
C63
U9
IDAC Out
+
U33
Low Current Amplifier
2GND
Mid Current Amplifier
Z1
Z1
U58
14k
14k
+
IDAC
OUT_HI
IFBK
U25
IGND
High Current Amplifier
IGND
Shunt Amp
+
U48, U52,
-
U53, U33
IGND
Shunt
Resitors
2GND
Figure 2-6. AC Current Functions
SGND
OUT_LO
apv015f.eps
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57LFC/AN
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Detailed Hardware Description of DC/AC Current
Current returning from the output load is sensed by current shunt R1 for the 2.2 A range,
by the 4 Ω shunt in R-net Z2 for the 220 mA range, by the 40 Ω shunt in R-net Z2; for
the 22 mA range, by the 400 Ω shunt in R-net Z2 for the 2.2 mA range, and by the four
1k resistors in series (4 k total) R19, R20, R52, R155 for 220 µA range.
Solid state switches U23, U10, and U28 select the shunt required by each range.
The SHUNT_SEL lines from the digital control circuits activate the switches for the
range required. Both the Hi and Low sides of the shunt are selected in pairs.
The shunt voltage is amplified by a differential amplifier composed of amplifiers U33,
U48, U53, U52 and associated components. R-net Z4 sets the gain of the differential amp
to 2.5. Amplifier U29 cancels any current in the RCOM1 line. U33 provides an additional
gain of 4 to the 2.2 A range shunt voltage so that a smaller value shunt could be used for
less power dissipation.
The output of the differential shunt amp is fed back to the A6 Digital Synthesis PCA on
the IFBCK line and the CAL_OS line via solid state switches U25 and U27, and to the
distortion loop error amp U18 via resistor R3.
The feedback from the differential shunt amplifier via R3 is compared to the input signal
from the A6 Digital Synthesis PCA I_ACDC_SW, by amplifier U18. Any difference is
amplified by U18, and the difference is used to drive one of the three output amplifiers,
depending on range, to the correct output level and to correct for any distortion produced
by the output amplifiers within the limits of the loop gain around the whole loop.
Switch U26 connects various feedback components to U18. The STBY* control line
from the digital control circuit turns on a switch to short U18 output to the negative input
during instrument standby to keep U18 biased to 0 output. The COMP3 control line
switches C135 around U18 to reduce the loop bandwidth in DC mode and the LCOMP
ON in the AC mode. The other control lines switch resistors in and out to tailor the
response of the loop as needed for each range.
The output U18 feeds an isolation amplifier composed of U44, U13 and associated
components. This isolation amplifier provides high impedance isolation from circuits
referenced to “S” common to circuits referenced to both “I” common and “2” common.
The “I” common and “2” common are separated from the “S” common by the shunt
resistor that is in use for each range. The output of the isolation amplifier is fed to the low
current, mid current, or high current output amplifiers via relays K10 and K1. Relays K10
and K1 also configure the “I” and “2” commons as required by the output amplifier in
use.
Low Current Output Amplifier
The output amplifier for the 220 µA and 2.2 mA ranges is composed of U32, U35, Q16,
Q19, Q 20, and associated components. This amplifier uses the “2” common for its
ground reference and has its own floating power supply referenced to the “2” common.
The power supply is composed of transformer T1, CR26, C102, C103, U50, U51 and
associated components. Amplifier U49 drives a shield in transformer T1 to reduce the
capacitance between “S” common and the “2” common. Capacitance between the two
commons appears across the current sensing shunt and degrades the frequency response
and therefore the accuracy of the instrument.
2-40
Transistor Q20, ½ of amplifier U35, CR11, R44, R148, R47, and R198 form a pull down
current source of 2 mA in the 220 µA range and 6.5 mA in the 2.2 mA range. Amplifier
U32, Q16, and R37 convert the input voltage at U32 pin 3 into a current that flows into
R43 and forms a voltage at U35 pin 5. The other input at U35 pin 6 is derived from the
resistors at the emitter of Q19 (R165, R147, and R48). Relay K12 switches R48 into the
Theory of Operation
A7 Current PCA 2
circuit for the 2.2 mA range and out for the 220 µA range. The other half of K12 switches
R47 and R198 into the circuit for the 2.2 mA range and out for the 220 µA range. When
the voltage at U35 pin 6 is equal to the voltage at pin 5 the amplifier is biased for
operation at 6.5 mA on the 2.2 mA range and 2 mA on the 220 µA range.
Transistors Q41, Q42, and resistor R7 limit the current that could be forced back into the
circuit if a voltage is applied to the output terminals of the instrument when the low
current amplifier is in use. The current will be limited to between 10 mA and 50 mA with
transient voltages up to 350 V.
Solid-state relay U34 is used to disable the amplifier when it is not being used. A high on
the LO_CURRENT_DISABLE line from the digital control circuit will turn on the relay,
shut off the bias current in the amplifier and put it in a dormant state.
The transconductance of this current amplifier is 2 mA/ V on the 2.2 mA range and
214 µA/ V on the 220 µA range.
Mid-Current Output Amplifier
The output amplifier for the 22 mA and 220 mA ranges is composed of U7, U58, U31,
Q3, Q5, Q14, Q15, MP13, MP14 and associated components. This amplifier uses the “I”
common for its ground reference.
This is a class-A push-pull output stage amplifier with 242 mA bias on the 220 mA range
and 27 mA bias on the 22 mA range.
MP13 and Q14 supply the positive output current. MP14 and Q15 supply the negative
output current. Relay K2 switches in the resistors to set the bias current. With the 1 ohm
resistors switched in to the emitters of MP13 and MP14, the bias will be set at 242 mA.
With the 10 ohm resistors switched in, the bias will be 27 mA.
Input pin 6 of U31 connects to the emitter resistors of MP13 and input pin 5 of U31
connects to R23 through R85. U31 will adjust the base voltage of Q14 and MP13 to make
the voltage at its inputs equal. Therefore, the voltage across R23 will set the bias for
positive output transistors. In similar manner, the other half of U31 will set the voltage at
the emitter of MP14 equal to the voltage across R32. The voltage across R32 will set the
bias for the negative output transistors.
With no output current, the current from the positive output transistors will flow into the
negative output transistors. To obtain a positive output, the current out of MP13 and Q14
is increased and the current through MP14 and Q15 is decreased by the same amount.
The total output current is therefore equal to two times the amount of the increase from
the positive output transistors. The current increment that was flowing in the negative
output transistors is now diverted to the output to supply ½ of the output, and the other ½
of the output comes from the increase in the positive output transistors. Negative output
currents are obtained in a similar manner. When the negative output transistors current is
increased, the positive output is decreased by the same amount.
The maximum output from the amplifier for class A operation will therefore be equal to 2
times the bias current. When either the positive transistors or the negative transistors
current is reduced to zero, the opposite side transistors will be supplying 2 times the bias
current to the output.
The differential drive for the output transistors is obtained from U7, U58, Q5, Q3 and
associated components. The positive output transistor drive voltage across R23 is
obtained from current supplied by Q5. Q5 is configured as a common base amplifier.
Current from R25 in the emitter of Q5 is passed out of the collector and into R23. Q5 is
biased by ½ of amplifier U58. R6 and R12 form a divider across the +15I supply to
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57LFC/AN
Service Manual
provide +2 V at the positive input of U58. The negative input of U58 is connected to the
emitter of Q5. U58 will therefore drive the base of Q5 to keep the emitter of Q5 at +2 V.
The input to the mid current output amplifier is amplified by U7. The output of U7 is
connected to R25//R28 and R27//R84. With zero input voltage the output of U7 will be
zero. The current through R25//R28 will be 2 mA (2 V/1 K). The 2 mA through
R25//R28 will be passed through Q5 to R23 to provide a voltage of 242 mV (2
mAx121 Ω).
The voltage at emitter of MP13 tracks the voltage on R23 as explained above. With the
1 Ω resistor R53 switched in, the bias current will be 242 mA (242 mV/1 Ω). With the
10 Ω resistor, R50 switched in the bias current will be 27 mA (24 2 mV/9.1 Ω) (10 Ω in
parallel with 100 Ω = 9.1 Ω).
The negative output transistor drive operates in a similar manner. Drive voltage across
R32 is obtained from the collector of Q3. Q3 is a common base stage biased to –2 volts
by the other ½ of U58 and divider R14 and R15, which is across the –15I supply. The
input current to Q3 emitter is from R27, which in turn is connected to the output of U7.
The current through R27 will be 2 mA also, and will pass through Q3 to R32 to provide
the 242 mV for the negative output transistor drive and sets the bias in the same way as
explained above for the positive output transistor.
Solid-state relay U30 is used to disable the amplifier when it is not being used. A high on
the MID_CURRENT_DISABLE line from the digital control circuit will turn on the
relay, shut off the bias current in the amplifier and put it in a dormant state.
The transconductance of this current amplifier is 242 mA/ V on the 220 mA range and
27 mA/ V on the 22 mA range.
High Current Output Amplifier
The output amplifier for the 2.2 A range is composed of U17, U59, U37, Q9, Q4, Q10,
Q1, Q2, Q8 and associated components. This amplifier uses the “I” common for its
ground reference.
This is a class-A push-pull output stage amplifier with 1.8 A bias in the ac mode and a
class-AB push-pull output stage amplifier with 0.5 A bias in the dc mode.
The circuit topology is similar to the mid current output amplifier. The output drive
transistors, bias current determination, and differential drive are established in the same
way as the mid current output amplifier. Refer to the mid current output amplifier above
for details of the operation.
Bias current for dc operation is set at 0.5 A. Relay K22 switches resistor R79 in parallel
with R74 on the positive side, and R78 in parallel with R77 on the negative side. This
parallel combination sets up the 0.5 A bias in the output stage. With R79 and R78
switched out of the circuit, the higher resistance and therefore higher voltage across them
boost the bias in the output stage to 1.8 A for ac operation.
With 0.5 A bias in the output stage in the dc mode, either the positive output transistor or
the negative output transistor will shut off, depending on the polarity of the output
current, at about 1 A of output current. At this point, the amplifier operates class-B with
only one or the other of the output transistors in use at a time.
2-42
Solid-state relay U38 is used to disable the amplifier when it is not being used. A high on
the 2.2A_
DISABLE line from the digital control circuit will turn on the relay, shut off the
bias current in the amplifier and put it in a dormant state.
The transconductance of this current amplifier is 1.83 A/ V for ac and .55 A/ V for dc
≤1 A and .45 A/ V for dc >1 A.
Theory of Operation
A7 Current PCA 2
The temperatures of MP2 and MP3 are monitored with some TMP36 temperature sensors
mounted to small circuit boards that are soldered to the tabs of the transistors. The
temperature sensors put out 10 mV/degree C and have a 500 mV offset. A voltage divider
and capacitor on the sensor circuit board reduce the +15 V supply down to around +5 V
to power the sensor. The output of the sensor goes through a RC low-pass filter and is
sent through U10 to the SMUX line where it can be periodically monitored when in the
2.2 A range. An out-of-range condition would indicate some kind of circuit failure or a
blocked or failed fan.
High Current Amplifier Power Supplies (Mongo Supplies)
The power supply for the 2.2 A high current amplifier was designed to have a magnitude
5 V higher than the output peak compliance voltage. The supply will therefore be +/-5 V
with 0 V compliance and +/-11 V with 6 V peak (4 V rms) compliance.
The circuitry used to detect the peak compliance voltage is composed of U16, U21, U20,
U19, and U47 and associated components. U16 is a unity gain buffer that monitors the
output voltage from the current PCB on the OUT_HI line through K19 and R114. The
output of U16 is switched by U47 to the input of U21. U21 is configured as a full-wave
rectifier which gives a positive rectified output for either polarity of the input signal. This
rectified output is filtered by R169, C58, and then applied to switch U47 where it is
switched to the PMUX line. PMUX is monitored by the A6 Digital Synthesis PCA,
which generates the "compliance voltage exceeded" message and places the instrument
back to standby.
The output of full-wave rectifier U21 is also applied to a track-and-hold circuit composed
of U20, C59, R170, and R193. The positive input signal from U21 is inverted and
charges C59 to a negative value of the same magnitude as the input. As the input voltage
begins to decrease U20 will turn off and leave C59 with a voltage equal to the negative of
the peak input voltage. C59 charges quickly through U20 and discharges slowly through
R193 and R170 after U20 shuts off. (U20 has an open collector output stage).
The voltage across C59 is applied to the positive input of one op-amp in U19. The
negative input is connected to Zener diode VR2 (5.1 V) that is connected between the opamp output and the negative input. VR2 is biased on by R108 and by R63, when solidstate relay U45 is on. With this circuit configuration the output of the op-amp will always
be 5.1 V lower than the voltage on the positive input. With 0 V compliance, the voltage
across C59 will be 0 and therefore the output of U19 will be -5.1 V. With 6 V compliance
the voltage across C59 will be -6 V and therefore the output of U19 will be -11.1 V. The
output of this op-amp is the –IREF that is supplied to the high current power supply on
the A3 Motherboard PCA. The other half of U19 is configured as a unity gain inverter,
and inverts the –IREF to generate the +IREF signal for the high current power supply.
At power ON, solid state relay U45 will be off and the bias current to VR2 and C57,
which is in parallel with VR2, must come from R108 (200k). The output signals +IREF
and –IREF will therefore rise slowly and in turn, the high current power supply will come
up slowly. After a delay, relay U45 will turn on and normal bias current will be provided
by R63.
The high current power supply is located on the A3 Motherboard PCA, and is composed
of U23, U24, Q14, Q17, Q9, C87, C53 and associated components. The AC input voltage
from the main power transformer is full-wave rectified by CR64 and CR60 for the
positive supply and by CR65 and CR61 for the negative supply.
When transistor Q14 is on, the positive rectified voltage will charge C87, which provides
the +MMONGO output. Q14 is controlled by U23. The inputs to U23 are the +IREF on
the + input and the full-wave + rectified AC on the negative input. If the +IREF signal is
larger than the AC input signal, the open collector output of U23 will be off and the gate
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of Q14 will be biased on by the +15I_UNR supply through R70 and R74. Once Q14 is
on, it will remain on until C87 is charged up to a voltage equal the +IREF signal and then
Q14 will be turned off by U23. The voltage at the negative input of U23 turns on the
output and shorts the input voltage to Q14. If Q14 is off, diode CR47 (which is connected
between the negative input of U23 and the supply output) will begin to conduct when the
AC input is one diode drop greater than the supply output. If the supply output decreases
more than one diode drop from the +IREF, U23 will turn off and turn Q14 on and allow
C87 to charge for more of the AC input cycle, rather then waiting for the next cycle of
the AC input.
When transistor Q9 is on, the negative rectified voltage will charge C53, which provides
the -MMONGO output. U24 and Q17 control Q9. The inputs to U24 are the
-IREF on the + input and the full-wave - rectified ac on the negative input. If the -IREF
signal is more negative than the AC input signal, the output of U24 will be negative,
which will turn on Q17. With Q17 on the +15I supply voltage will turn on Q9. Once Q9
is on, it will remain on until C53 is charged up to a voltage equal the -IREF signal and
then Q9 will be turned off by U24/Q17. The voltage at the negative input of U24 turns
the output off, which turns off Q17 and Q9. If Q9 is off, diode CR37, which is connected
between the negative input of U24 and the negative supply output, will begin to conduct
when the AC input is one diode drop less than the negative supply output. If the negative
supply output increased more than one diode drop from the -IREF, U24/Q17 will turn on
which will turn Q9 on and allow C53 to charge for more of the AC input cycle, rather
then waiting for the next cycle of the AC input.
A8 High Voltage PCA
The function of the A8 High Voltage PCA is to amplify the 2.2 V (nominal max.) signal
from the A6 Digital Synthesis PCA to the output levels required for the 22 V and 220 V
ranges. The A11 Isothermal PCA is assembled and tested as part of the A8 High Voltage
PCA.
This is accomplished by employing separate amplifiers for each range. These amplifiers
have gains of 10 and 100 for the 22 V and 220 V ranges respectively.
The exact gain of each amplifier is not critical as overall amplitude control is maintained
by an outer amplitude control loop external to the A8 High Voltage PCA. However, this
outer loop does not correct for distortion, noise or offset, all of which must be suitably
controlled within the amplifiers. Both amplifiers are directly (dc) coupled to the output
terminals and protection against short circuit is provided by appropriate output stage
current limit circuits.
The A8 High Voltage PCA also contains a dual polarity high voltage regulator circuit
which serves to isolate the 220 V amplifier from raw dc supply voltage variations
resulting from mains fluctuations, transformer regulation and ripple. The magnitude of
the positive and negative outputs may be independently set under firmware control to
levels of 188 V or 375 V as dictated by the required amplifier output, thus allowing
amplifier output device dissipation to be reduced. The regulator also contains a current
limit and over-current shutdown feature to further protect the 220 V amplifier in the event
of an output short circuit. See Figure 2-7 a diagram of the A8 High Voltage PCA 22 V
and 220V amplifier.
2-44
Theory of Operation
A8 High Voltage PCA 2
V3_3
P108
VMID
A8 22 V and 220 V Amplifiers
K1K1
and output stages
22V D iscrete Gain
+45
20k
C31
R141
R139
-45
U5/U11
-
+
R204
2k
R138
SGND
SGND
K4
K3
-
+
U60
OUT_220V
K2K2
U15
and output stages
220V Discrete Gain
+PA
200k
C29
R128
R132
K4
-PA
U3/U11
-
+
R203
2k
SGND
R133
A6
500k
K1
-
5k
U21
5k
50k
K2
K3
VDAC
U15
Averaging Converter
+
K3
V3_3
P108
RCOM1
VDIV
apv016f.eps
Figure 2-7. A8 High Voltage PCA 22 V and 220 V Amplifier
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Detailed Hardware Description of the 22 V Amplifier
The 22 V amplifier has a gain of 10 and provides output voltages of between 2.2 V and
22 V dc or ac rms at frequencies up to 100 kHz. The amplifier is designed to
accommodate a maximum burden of 50 mA dc or ac rms and a maximum capacitive load
of 500 pF. To achieve the maximum required voltage swing under ac conditions the
output stage is operated from ±45 V supply rails, whilst the input stages are operated
from ±15 V rails. All power supplies are derived externally.
In the 22 V range relays K3 and K4 route the input signal (V3_3) and it's associated
ground (RCOM1) from connector P108 to the inverting and non-inverting inputs
respectively of an operational amplifier input stage comprising U5 and U11. The
combination of wide bandwidth amplifier U5 and chopper-stabilised amplifier U11
allows wide bandwidth and good dc performance to be achieved simultaneously.
Transistors Q59 and Q60, diodesVR23 and VR24 and resistors R233 and R234 form a
feedback voltage clamp around the op-amp to ensure the output and inverting input
always remain within their linear operating range. This is necessary to prevent
conditional large signal instability of the 22V amplifier resulting from the finite overload
recovery time of the op-amp. Dual diodes CR31 and CR32 and associated components
clamp the op-amp inverting input at approximately ±1.5V under overload conditions.
The output of U5 is fed via R144, to voltage-to-current converter stage Q56. The
transconductance of this stage is set by R210 and emitter bias current is provided by
current source Q55. Diode CR47 is included to prevent reverse base-emitter breakdown
of Q56 which would otherwise occur under overload conditions.
The output from the collector of Q56 is applied to the input of common emitter amplifier
Q36: this stage is referenced to the -45V supply rail and provides the full output voltage
swing of the amplifier. Collector bias current for Q26 is supplied by current source Q35,
thus maximising the low frequency gain of the stage.
The output from Q35 is buffered by emitter followers Q11 (biased by current source
Q8/Q10) and Q12 (biased by current source Q9/Q34) before being fed to complimentary
output emitter followers Q4 and Q5 respectively. The output stage bias current is defined
by the quiescent voltage imposed across the series/parallel combination of resistors R3 to
R10: this voltage is the sum of the base emitter voltages of Q11 and Q12 and the voltage
across dual diodes CR16 and CR17 less the base emitter voltages of Q4 and Q5 and the
voltage across CR3 and CR6. Resistors R3 to R10 are chosen to set this current at
approximately 40mA so that the output stage operates in class A under all specified load
conditions to eliminate crossover distortion.
Transistor Q3 provides limiting for positive output currents by absorbing further
increases in base current to Q4 once sufficient voltage is developed across the R3/R4
parallel combination to turn Q3 on: Q6 provides limiting for negative currents in a similar
manner by restricting the base current to Q5. Under current limit conditions, dual diodes
CR16 and CR17 prevent reverse base-emitter breakdown of Q11and Q12 respectively
whilst diodes CR4 and CR5 prevent current flow from Q11 and Q12 to the output via the
forward biased collector-base junctions of Q3 and Q6 respectively.
The overall gain of the amplifier within the specified operating bandwidth is defined by
feedback network R139, R145 and R146 and is given by the expression (R145 +
R146)/R139. Stability is ensured by dominant pole compensation provided by local
feedback around Q35 via capacitor C33. Additional open loop frequency response
shaping is provided by local feedback around U5/U11 via R141 and C31.
2-46
Fuse F1 and diodes CR14 and CR15 are included to help protect the amplifier in the
event of an external high voltage source being connected to the output terminals. During
such an occurrence the amplifier output is clamped to the ±45V supply rails by CR14
Theory of Operation
A8 High Voltage PCA 2
and/or CR15, providing short-term protection. The resulting large current flow eventually
causes F1 to rupture, thus providing protection in the longer term. To minimize
undesirable effects due to variability in fuse characteristics with operating point,
temperature and time F1 is connected within the overall feedback loop of the amplifier.
The amplifier output is routed to connector P108 via resistor R143 and relay K1. R143 is
included to help prevent output stage instability in the presence of capacitive loads.
Detailed Description of the 220 V Amplifier
The 220 V amplifier has a gain of 100 and provides output voltages of between 22 V and
220 V dc or ac rms at frequencies up to 100 kHz. The amplifier is designed to
accommodate a maximum burden of 20 mA dc or ac rms or a maximum capacitive load
of 675 pF for ambient temperatures up to 40 °C. Above this temperature, the allowable
load capacitance is reduced.
To achieve the maximum required voltage swing under ac conditions the output stage is
operated from ±375 V supply rails (±PA). These rails are regulated to provide isolation
from raw dc supply voltage variations caused by mains fluctuations, transformer
regulation and ripple. To minimize output stage power dissipation (particularly under dc
output conditions), the positive and negative PA rails can be independently switched to a
value of 188 V under firmware control when compatible with the required amplifier
output voltage. See Table 2-15 for the supply values as a function of range.
Table 2-15. Supply Values as a Function of Ranges
Calibrator Output +PA -PA
±22 V to ±110 V dc +188 V -188 V
110 V to 220 V dc +375 V -188 V
-110 V to -220 V dc +188 V -375 V
22 V to 101 V ac +188 V -188 V
101 V to 220 V ac +375 V -375 V
The amplifier input stages are operated from ±15 V rails. Regulator circuits for the high
voltage rails are located on-the A8 High Voltage PCA while the ±15 V rails are derived
externally.
In the 220 V range relays K3 and K4 route the input signal (V3_3) and it's associated
ground (RCOM1) from connector P108 to the inverting and non-inverting inputs
respectively of an operational amplifier input stage comprising U3 and U4. The
combination of wide bandwidth amplifier U3 and chopper-stabilized amplifier U4 allows
wide bandwidth and good DC performance to be achieved simultaneously. Transistors
Q31 and Q32, diodesVR22 and VR42 and resistors R129 and R130 form a feedback
voltage clamp around the op-amp to ensure the output and inverting input always remain
within their linear operating range. This is necessary to prevent conditional large signal
instability of the 220 V amplifier resulting from the finite overload recovery time of the
op-amp. Dual diode CR30 clamps the op-amp inverting input at approximately ±0.7 V
under overload conditions.
The output of U3 is fed via R131 to voltage to current converter stage Q53. The
transconductance of this stage is set by R199 and emitter bias current is provided by
current source Q54. Diode CR29 is included to prevent reverse base-emitter breakdown
of Q53 which would otherwise occur under overload conditions.
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The output from the collector of Q53 is fed via common-gate connected high voltage Pchannel mosfet Q52 to the collector/base of Q51. Q52 is necessary to isolate the collector
of Q53, which is a low voltage small signal device, from the high voltage associated with
the -PA supply rail.
Q51 forms the input of a current mirror whose output flows into the collector of Q50. The
output/input current ratio of this mirror is defined essentially by the ratio of the values of
R198 and R118 and is approximately 4.7. The collector of Q50 is isolated from highvoltage signal excursions by common-gate configured N-channel mosfet stage Q33, and
at low frequencies the mirror output current almost entirely flows via the drain of this
device. The gate of Q33 is referenced to the -PA supply rail via VR18, and the drain of
this device provides the full output voltage swing of the amplifier. Drain bias current for
Q33 is supplied by a current source comprising Q47, Q48, CR46 and R194, thus
maximising the low frequency current-to-voltage gain of the stage: this current is set at
approximately 8 mA. Common base stage Q30 is included to recover mirror output
current which would otherwise be lost via the drain-gate capacitance of Q33 at high
frequencies. This is necessary to prevent loss of gain and to alleviate distortion caused by
variations of drain-gate capacitance with voltage.
The signal at the drain of Q33 is then fed to complimentary Darlington emitter follower
output transistors Q45/Q27 and Q46/Q44. The output stage bias current is set by the
quiescent voltage imposed across the series/parallel combination of resistors R186 to
R189: this voltage is the collector-emitter voltage of 'Vbe multiplier' transistor Q49 less
the base emitter voltages of Q27, Q44, Q45 and Q46. Resistors R186 to R189 in
conjunction with resistors R195, R196 and variable resistor R197 are chosen to allow this
current to be set at 18 mA.
High-voltage N-channel mosfet devices Q1 and Q25 isolate Q27 and Q45 from the high
potentials necessary to obtain the specified Amplifier output voltage swing. The
collector-emitter voltage of Q27 and Q45 is set at approximately 12 V by Zener diode
VR15 (which is referenced to the amplifier output) and the gate-source voltage of Q1.
Bias current for VR15 is supplied by series/parallel resistor combination R95, R96, R98
to R101, R103 and R104 which also serves to set the gate voltage of Q25 at
approximately half way between the +PA supply and amplifier output voltages: the
voltage presented across Q1 and Q25 is thus shared equally between the two devices.
C18 is included to counteract the effect of input capacitance of Q25, thus ensuring
effective voltage sharing up to the maximum operating frequency. High-voltage
P-channel mosfet devices Q2 and Q29 isolate Q44 and Q46 in a similar manner. Because
the voltage difference between the Amplifier output and the ±PA power supply rails is
supported almost entirely by Q1, Q2, Q25 and Q29, the bulk of the amplifier output stage
power dissipation is liberated in these in devices.
Transistor Q26 provides limiting for positive output currents by absorbing further
increases in gate-source voltage of Q4 once sufficient voltage is developed across the
R105 to turn Q3 on. Q6 provides limiting for negative currents in a similar manner by
restricting the gate-source voltage of Q2.
The overall gain of the amplifier within the specified operating bandwidth is defined by
feedback network R125, R127 and R132 and is given by the expression (R125 +
R127)/R132. Stability is ensured by dominant pole compensation provided by local
feedback from the emitter of Q46 to the base of Q50 via capacitor C48. Additional open
loop frequency response shaping is provided by local feedback around U3/U4 via R281
and C29.
2-48
Fuse F2 is included to provide limited protection in the event of an external high voltage
source being connected to the output terminals. This device is connected within the
overall feedback loop of the Amplifier to minimise distortion, particularly at low
frequencies, resulting from the non-linear characteristic of the device.
Theory of Operation
A8 High Voltage PCA 2
The amplifier output is routed to connector P108 via fuse F2, resistors R183 and R185,
chokes L2 and L2 and relay K1. R183, R185, L2 and L2 are included to help prevent
output stage instability in the presence of capacitive loads.
Op-Amp U15, transistors Q13 and Q61 and resistors R49, R94 and R97 comprise a
precision current mirror whose output from the collectors of Q13 and Q61 is proportional
to the current flowing from the +PA supply into the output stage. The input/output ratio
of the mirror is defined by the ratio of R49 to the parallel combination of R94 and R97
and is set at a nominal value of 110:1. Low-pass R-C network R235 and C65 restricts the
bandwidth of the signal fed to U15 and Darlington connected transistors Q14 and Q62
increase the output voltage capability of the mirror to accommodate the +PA supply. The
mirror output is sensed by resistor R58, and C67 is included to provide low-pass filtering
so that at high frequencies the resultant voltage represents the average output stage
current.
Dual FET-input operational amplifier U2, diode CR65, capacitor C92 and resistors R264
and R277 comprise a peak detector circuit that senses the voltage developed across R58
and temporarily holds its peak value. This ensures that at low frequencies the peak value
of current, which is more representative of output device dissipation than the average, is
sensed. The peak detector output is multiplexed onto the SMUX line via U10 for
subsequent A-to-D conversion.
The current from the -PA supply into the output stage is monitored in a similar manner to
that from the +PA supply.
Detailed Hardware Description of the High Voltage Regulator
The high voltage regulator circuits provides linear voltage regulation of the raw high
voltage dc supplies from the A3 Motherboard PCA to produce the ±PA supply rails
required by the 220 V amplifier output stage. The positive and negative outputs may be
set to zero or independently set to levels of 188 V or 375 V under firmware control. The
regulator has output current limit to protect both the 220 V amplifier and itself in the
event of fault and applied short-circuit conditions.
Raw unregulated dc supplies +360UNR, +180UNR, -180UNR and -360UNR (having
nominal values of +545 V, +270 V, -270 V and -545 V respectively) are presented at
connector P108.
For a required +PA output voltage of +375 V, control lines +HI/LO_V and +ON/OFF are
set low (-14 V) so that transistors Q18, Q20 and Q17 are turned off and pin 2 of analogue
switch U20 (SWA) is connected to HVCOM. The output of current source transistor Q21
(approx. 0.8mA) thus flows in resistors R241, R242, R252 and R253 and transistor Q66.
Op-amp U21 controls the gate drive to Q66 to maintain the voltage at the junction of
R241 and R242 equal to that at the output of 5 V reference U22, and the voltage at the
drain of Q66 is therefore set at 379 V due to the potential divider action of R241, R242,
R252 and R253. This voltage is applied to the gate of +PA output transistor Q22,
resulting in a nominal regulator output voltage of 375 V at the source terminal of the
device. Resistors R38, R41 to R43, R76, R78, R81 and R84 form a potential divider
chain which sets the gate (and consequently source) voltage of Q7 at approximately half
way between the voltages at the +360UNR input and the Regulator output (VR3, VR5,
VR6 and VR7 do not conduct as the sum of their breakdown voltages exceeds that
appearing at this node in normal operation and Q18 is turned off). The +PA Regulator
input/output voltage difference, and consequently output device power dissipation, is thus
shared equally between Q7 and Q22, allowing higher input voltages and output currents
than if a single output device were used. In this mode, diodes CR11 and CR12 are reverse
biased to prevent current flows from the +180UNR raw supply. Zener diodes VR9 and
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VR10 are included to restrict the regulator output voltage if Q66 or any of it's associated
components fails.
For a required +PA output voltage of +188 V, control line +HI/LO_V is set high (+14 V)
and +ON/OFF is set low (-14 V). Transistor Q18 is thus turned on, shorting Zener diodes
VR5, VR6 and VR7 and causing diode VR3 to conduct via resistors R38 and R41 to R43.
The gate, and consequently source, of Q7 are thus held at approximately 150 V. As this is
lower in voltage than the +180UNR input supply, diode CR13 is reverse biased and all
regulator input current flows from the +180UNR supply via CR12 into the drain terminal
of Q22: the drain potential of Q22 is thus essentially equal to that of the +180UNR
supply. In this condition, pin 2 of analogue switch U20 (SWA) is left unconnected to
HVCOM and R240 is thus included in series with R241 so that the voltage at the drain of
Q66 is now controlled at 192 V. This voltage is applied to the gate of +PA output
transistor Q22, resulting in a nominal regulator output voltage of 188 V.
For a required +PA output voltage of zero, control line +ON/OFF is set high. This turns
on Q17, shorting out shorting the drain terminal of Q66 to ground and resulting in a
nominal voltage of zero at this point. It should be noted that the +PA and -PA outputs
cannot be set to zero independently as their control lines are derived from the same logic
control signal.
Current flowing from the +PA output is sensed by R88, the voltage across which is
applied to the base and emitter terminals of Q23. The collector current of Q23 is sensed
by the parallel combination of VR33 and R171, and the voltage developed is applied to
an R-C low-pass filter comprising R168 and C15. The filter output is applied to the noninverting input (pin 5) of one half of dual comparator U9, the inverting input (pin 6) of
which is normally held at approximately 3.5 V by current source CR21 and resistor R77.
Under normal operation, Q23 does not conduct and. Pin 5 of U9 therefore remains at
approximately 0 V. The comparator output (pin 7) therefore pulls low
(approximately -14 V), reverse biasing CR36 and allowing the gate voltage of Q17 to be
set in accordance with the +ON/OFF line.
When the +PA supply output current exceeds a pre-determined overload limit of
approximately 90 mA, Q23 rapidly starts to conduct and the filter output begins to rise. If
the overload condition persists for longer than approximately 75 ms, the filter output
voltage becomes sufficient to cause the comparator output to start to change state. The
positive-going comparator output voltage causes Q19 to start to conduct. This results in
positive feedback via the inverting input, thus accelerating the change in state. This
process terminates when the open-collector output of the comparator is completely
inactive. In this state the gate voltage of Q17 is pulled up to approximately 7.5 V by
R159 and Q19 is saturated. Q17 is thus turned on, shorting out the drain of Q66 and
resulting in the +PA output being reduced to zero.
Reducing +PA to zero causes the output current to fall, and consequently Q23 stops
conducting. The filter output voltage applied to the non-inverting (pin 5) comparator
input therefore starts to fall. When it reaches the level on the inverting input (the collector
saturation voltage of Q19) the comparator reverts to its original state. Q17 is again
allowed to be turned off by the low (-14 V) +ON/OFF line and the voltage at the drain of
Q66 begins to increase slowly towards its normal reference value as capacitor C13
charges.
When the regulator output voltage reaches a value sufficient to again cause the overcurrent condition the process repeats, and this cyclical operation continues until the cause
of the over-current is removed.
Resistor R90 and transistor Q24 comprise a secondary over-current detector, set at
approximately 0.5 A, whose function is to protect the Regulator against a short-circuit
applied to the +PA output. Collector current flowing in Q24 causes the voltage across
2-50
Theory of Operation
A8 High Voltage PCA 2
Zener diode VR39 to increase rapidly towards a limit of 10 V. This voltage is applied to
the non-inverting (pin 5) input of U9 without filtering so that in the event of an overload,
no intentional delay occurs before the comparator changes state and the supply shutsdown.
To provide a safer environment for fault finding of the 220 V amplifier, the high voltage
regulator outputs (±PA) my be reduced to approximately ±45 V by re-routing the drain
terminals of output transistors Q22 and Q34 to the ±45 V regulated supplies on the A3
Motherboard PCA. This is implemented by setting switch S1 to its alternative position
i.e., with the switch actuator set furthest from the connector edge of the A8 High Voltage
PCA.
The operating principles used to derive the Regulator -PA output are identical to those for
the +PA output. The -PA output voltage is set to -188 V or -375 V by low (-14 V) and
high (+14 V) states respectively of control line -HI/LO_V, and is set to zero when the ON/OFF assumes it's low (-14 V) state. Note that the +ON/OFF and -ON/OFF lines are
derived from the same control signal and therefore the +PA and -PA outputs cannot be
set to zero independently.
Heat Sink Temperature Measurement
The temperature of the heatsinks for 220 V amplifier output devices Q25, Q29, and high
voltage regulator output devices Q22 and Q42 are monitored by heatsink mounted
integrated circuit temperature sensors U25, U26, U27 and U28. The sensor output
voltages are multiplexed onto the SMUX line by U19 via U10 for subsequent A-to-D
conversion.
Digital Interface and Control
The digital interface to the A8 High Voltage PCA comprises an 8-bit data bus
(IG_DATA<7..0>), three address lines (ID_ADDR0, ID_ADDR1 and ID_ADDR2), a
board select line (IG_CSO) and a write line (IG_WR*).
When the board select line is low, U7 routes the IG_WR* signal (which is normally held
high) to the clock inputs of 4-bit relay drivers U12 and U13 or one of two 8-bit latches,
U14 and U17, as determined by the state of the three address lines. 8-bit data is clocked
into the latching inputs of U12 and U13 (which are connected to act as a single 8-bit
device), U14 or U17 in response to the IG_WR* line being taken momentarily low, data
being latched on the low to high transition.
The open-collector outputs of U12 and U13 are grouped in pairs, each pair driving the set
and reset coils of one of the four on-board latching relays. The four reset coils are also
connected together via diodes CR49 to CR53 so that all relays can be simultaneously
reset by pulling the RLY_RST* line low.
The outputs of U14 are used to control U10 and U20 directly. Outputs Q5 to Q7 are also
translated by quad comparator U8 to produce the ±14 V signals +ON/OFF, -ON/OFF,
+HI/LO_V and -HI/LO_V. This process introduces an inversion in deriving +ON/OFF
and +HI/LO_V.
Outputs Q0 to Q2 of U17 control the output routing for the heatsink temperature monitor
IC's via U19.
2-51
57LFC/AN
Service Manual
A9 Out-Guard CPU PCA
The CPU manages all of the internal remote functions including: IEEE-488 and RS-232
remote communication, calibration enable, watchdog timer, serial communication with
the FPGA on the A6 Digital Synthesis PCA. See Sheet 1 of the A9 Out-Guard CPU PCA
schematic.
The main processor (U10) is a Motorola 68306 that runs on code stored in flash memory
(See Sheet 2 of the A9 Out-Guard CPU PCA schematic). The processor directs all
internal operations in the Calibrator. It receives commands from the IEEE-488 interface.
The RS-232 interface is used in the factory for special testing.
There are two serial ports. One serial port is used for communication with a host PC. The
other port, AUX, can be used as a programmable serial output port. When the Calibrator
is used with Fluke’s hand held scope meters, the port may be used to control the scope
meter.
The CPU communicates with the A6 Digital Synthesis PCA through serial
communication lines through J1, a 20-pin cable to the A3 Motherboard PCA. All
communication with the A6 Digital Synthesis PCA is through differential transceivers
and transformers. The differential drivers reduce noise coupling between the guarded and
non-guarded CPU circuits. The transformers isolate the guarded and unguarded circuits.
The transformers are found on the A6 Digital Synthesis PCA. See Sheet 7 of the A6
Digital Synthesis PCA schematic.
There are several miscellaneous items to note on the A9 Out-Guard CPU PCA. First,
there is a watchdog timer circuit, U1. If the CPU loses communication with either the
front panel or the A6 Digital Synthesis PCA, the watchdog timer is not signaled which
allows a hard reset to the instrument. Secondly, there is the calibration enable switch.
When a 57LFC is calibrated, it is recommended that the switch be set to inactivate
calibrating the instrument until the normal calibration interval has expired. Finally, a
JTAG port is available to allow programming the flash memory through the CPU when
changes are made to the software. This can only be used by the factory.
Real Time Clock Memory
There is over 640 K bytes of static RAM on the CPU board. The RAM has a bank of
128 k x 16 and a bank of 512 k x 16. The is also 512 k x 16 flash memory in U5 and U6.
At power-up, the flash is moved into RAM. Program execution is then out of RAM. The
real time clock provides the calendar functions for the instrument. If the real-time lock
battery wears out, when power off, the instrument will lose its ability to keep track of the
calibration cycle. See Sheet 2 of the A9 Out-Guard CPU PCA schematic.
IEEE-488 Interface
The TMS9914 IEEE-488 IC is used for all remote IEEE-488 communication. There are
two buffers that provide the correct driver capability for the IEEE-488 bus. In general, the
product complies will all parts of the IEEE-488 standard. Note that U12 and U19 are not
installed. See Sheet 3 of the A9 Out-Guard CPU PCA schematic.
Verification Test Check List.......................................................................... 3-22
3-1
57LFC/AN
Service Manual
3-2
Calibration and Verification
Calibration 3
Calibration
Calibration of the 57LFC is accomplished using two internal calibration procedures.
The first of these is an offset or "zero" calibration and requires no external standards. The
second procedure is used to establish range gains and other constants using external
standards. The first internal procedure will be referred to as "zero" calibration and the
second will be referred to as "main" calibration for the remainder of this discussion. See
Table 3-1 for a list of the equipment required by the main calibration procedure.
The calibration procedures consist of a number of calibration steps. While the user has no
direct access to the procedures or the individual steps that comprise them, an
understanding of their structure makes it easy to write an external computer program to
utilize them. For this reason, the internal procedure architecture is described in the
following section.
Procedure Architecture
There are three parts to a calibration procedure. Every procedure has an entry point, one
or more steps, and an end point. In this section we will describe each of these and its
implications for the programmer writing a calibration application.
Note
In this section, "controller" refers to the computer controlling the
Calibrator. The term "@LFC" refers to the IEEE488 address of the
Calibrator. The examples shown are in pseudo code.
PROC <name> (Defines the procedure entry point)
The procedure name is used to define the start of a calibration procedure. There are three
(3) PROC definitions for the Calibrator: ZERO, MAIN, and DIAG. The name associated
with the PROC declaration is used in conjunction with the CAL_START command to
initiate a calibration procedure. The procedure names are defined below. Note that case is
ignored.
ZERO
ZERO (The offset or zero's calibration procedure as described above.)
print @LFC "cal_start zero"
MAIN
MAIN (The main calibration procedure as described above.)
print @LFC "cal_start main"
DIAG
DIAG (The diagnostics procedure as described in that section).
print @LFC "cal_start diag"
Calibration Steps
There are four types of calibration steps: RUN, INS, REF and NOT.
Whenever a calibration procedure is running the controller may query the Calibrator to
determine which of the four types of steps is currently being executed by the internal
calibration engine. To query the Calibrator for the calibration step type, use the
CAL_STATE? Command. As described below, the controller is expected to take
different actions depending on the internal step type. See the example below:
A run step requires no external intervention (input or output) it simply runs an internal
function to perform some calibration operation. Zero calibration is composed of an entry
point, followed a number of RUN steps and an END.
This step causes the procedure to pause at the current step and an instruction is made
available via the CAL_INFO? command. To resume the procedure, a CAL_NEXT
command must be issued. This step is used to inform the user that some operator
intervention is required, such as an external connection to a measurement standard.
Note
The CAL_INFO? command is not mandatory.
A reference step, like an INS step, causes the procedure to pause and an instruction is
made available via the CAL_INFO? command. Additionally, the controller is expected to
supply a floating point number. This number is typically a reference reading from an
external DMM. As an example, the internal calibration procedure may setup the
Calibrator to source 1.9 V. Then a REF step would prompt the user to go to operate. The
controller would need to send the operate command and command an external DMM to
take a reading. The reading from the DMM would be sent to the Calibrator using a
CAL_NEXT command. The Calibrator would use that value to calculate a new
calibration constant and then would continue to the next step. See the example below:
print @LFC "CAL_INFO?"
input @LFC A$
print A$
(shows "Go to operate and measure the expected value.")
print @LFC "OPER"// Go to operate
INPUT @DMM reading// get measurement from DMM
print @LFC "CAL_NEXT" + reading// send DMM reading to LFC
3-4
NOT
NOT simply means that the calibration procedure in no longer running. If the controller
determines that the NOT step was returned due to a normal termination of the calibration
procedure, a CAL_STORE command MUST be issued to store the newly derived
calibration constants into non volatile memory.
Once the calibration constants are saved, it is a good idea to reset the instrument using a
*RST command
For a complete list of remote commands for calibration see Chapter 3 of the 57LFC/AN Operators Manual.
Calibration and Verification
Verification Tests 3
During calibration, it is a good idea to check the Calibrator fault queue after each
calibration command. This will alert the user to any problems during the calibration. To
check the fault queue, send the command “ERR?” as shown below.
print @LFC "ERR?"
input @LFC A$
print A$
Verification Tests
The verification tests are used as the basis of:
• Final product testing performed in manufacturing
• Automated test system design
• Product acceptance by the end user
This section describes the minimum testing necessary to verify with reasonable certainty
that the Calibrator is totally functional and will meet its published specifications over the
specified environmental conditions and for the specified calibration interval. Any
personnel using the verification tests must be familiar with the operation of the Calibrator
and the have ability to set up and operate the recommended test equipment. While the
verification tests were developed for manual testing, if the test steps listed are followed
and test uncertainty ratios are kept above 3:1, automation of the verification test will meet
the requirements of verifying the product specifications.
This instrument is capable of outputting lethal voltages.
Observe all safety precautions. To avoid shock, the operator
should not electrically contact the Output V or Sense binding
posts during operation. Lethal voltages of up to 230 V ac or dc
may be present.
Whenever the nature of the operation permits, keep one hand
away from the equipment to reduce the hazard of current
flowing through vital organs of the body.
The verification tests are sufficient to insure that the shipped units will meet and/or
exceed published specifications over the specified environmental conditions and
specified calibration interval. All tests limits are based on specifications measured within
o
C +/- 3 oC (room temperature) and humidity less than 80%. Any test that fails will be
23
rerun immediately. If the failure repeats, it will be noted as a failure and testing will
continue with the next step if possible. Failures will be repaired and then the unit will be
retested.
Test Equipment
The equipment listed in Table 3-1 is for reference only. You can substitute any of the
equipment provided adequate measurement accuracy with a test uncertainty ratio of 4:1 if
possible. Only equipment that is calibrated and traceable according to the manufacturer
specifications may be used for performance verification testing.
XWWarning
3-5
57LFC/AN
Service Manual
Table 3-1. Recommended Equipment for Calibration and Verification
Recommended Equipment Recommended Model Purpose
Calibration and Verification
Procedure
Test Lead Kit Fluke 8508A-LEAD or equivalent Cable interconnect assembly
8-1/2 digit DMM Fluke 8508A DMM or equivalent Measure DC Volts, DC Current,
Precision Calibrator Fluke 5720A or equivalent Characterize 8508 for ac voltage
Harmonic Distortion Analyzer Boonton 1130 or equivalent Measure LF harmonic distortion of
Harmonic Distortion Analyzer Agilent ESA 4411A Spectrum
Test Controller Computer with an IEEE-488
Frequency Measurement Fluke 8508A or counter with
Shunt Resistors (5% 1/8 watt
unless noted)
Chapter 3 of the 57LFC/AN Service Manual
Analyzer or equivalent
interface card or equivalent
10 Hz to 100 kHz frequency range
and 25 ppm frequency uncertainty
or equivalent
0.1 (1 W), 10, 100, and 1 k Harmonic testing for AC current
Define procedure test points and
specifications
AC Volts, AC Current, and
Resistance
and ac current measurements
ac voltage and current
Measure harmonic distortion of ac
voltage for f > 30 kHz
Resistor Divider (10% 1/4 W) 2 M/20 k Harmonic Testing
Compliance testing
Calibrator Configuration and Pre-check
The Calibrator must be switched on and powered for at least 30 minutes prior to
verification testing and the air filter inspected for adequate airflow. Refer to filter
inspection and cleaning procedure provided in Chapter 4 for detailed cleaning
instructions.
Verification can only be performed using a controller as the Calibrator has no front panel
controls. Furthermore the Calibrator has no internal hardware adjustments.
When powered correctly the Calibrator front interface panel STANDBY LED indicator
will illuminate (yellow). When in operate, the OPERATE LED will illuminate (green). If
the output voltage goes above 30 V, the warning LED will illuminate (red). If the unit
encounters an output fault, both the yellow and red LEDs will light. For example, if in
current mode and the load is removed, a fault condition will be indicated since the output
compliance voltage will go to a maximum value.
Self-test routines are executed at power up that test the internal controller device and
memory. Any failure at power up will be displayed with both the yellow and red LEDs
lighting. A failure message can be requested over the IEEE-488 bus as part of the
instrument status (see Chapter 3 in the 57LFC/AN Operators Manual for additional
information).
3-6
Calibration and Verification
Verification Tests 3
Confirm Cal Enable (J1) is in the disabled condition before starting the rest of the
verification procedures. If the unit passes all tests. Cover the Cal Enable switch with a
calibration label.
DC Voltage Test
The dc voltage amplitude accuracy test verifies the accuracy of dc voltage at the
Calibrator front panel output terminals. Use the specifications in Chapter 1 to determine
maximum load for testing. Connect the equipment as shown in Figure 3-1 and verify the
Calibrator is within the limits shown in Table 3-2.
FLUKE 57LFC
OPERATE
STANDBY
8508A
Figure 3-1. 8508A Connections to the 57LFC for DC Volts Measurement
apv004f.eps
3-7
57LFC/AN
Service Manual
Table 3-2. DC Volts Measurement Limits
Range Amplitude Reading Upper Limit (V) Lower Limit (V)
200.0E-3 0 2.40E-6 -2.40E-6
200.0E-3 219.0E-3 219.0075E-3 218.9925E-3
200.0E-3 -219.0E-3 -218.9925E-3 -219.0075E-3
2 0 2.40E-6 -2.40E-6
2 2.19 2.19003696 2.18996304
2 -2.19 -2.18996304 -2.19003696
20 0 24.00E-6 -24.00E-6
20 10 10.00017920 9.99982080
20 -10 -9.99982080 -10.00017920
20 21.9 21.9003696 21.8996304
20 -21.9 -21.8996304 -21.9003696
200 0 240.00E-6 -240.00E-6
200 219 219.0057984 218.9942016
200 -219 -218.9942016 -219.0057984
3-8
Calibration and Verification
Verification Tests 3
AC Voltage Tests
AC Voltage Accuracy Test
The ac voltage amplitude accuracy test verifies the accuracy of ac voltage at the
Calibrator front panel terminals. First, use the 5720A to characterize all the points in
Table 3-3. Next, connect the equipment as shown in Figure 3-2 and verify the Calibrator
is within the limits shown in Table 3-3.
FLUKE 57LFC
OPERATE
STANDBY
8508A
Figure 3-2. 8508A Connections to the 57LFC for AC Volts Measurement
The specification for frequency is 100 ppm (0.01%). Connect the 8508A to the Calibrator
output terminals as shown in Figure 3-3. Then set the Calibrator to 2 V at the output
frequencies specified in Table 3-4. Verify that the meter reads within the limits specified
on the test record.
3-10
Calibration and Verification
FLUKE 57LFC
OPERATE
STANDBY
8508A
Figure 3-3. 8508A Connections to the 57LFC for AC Frequency Measurement
Table 3-4. AC Frequency Values
Frequency Value Measured Value Lower Limit Upper Limit
Verification Tests 3
apv006f.eps
11 Hz 10.999296 Hz 11.000704 Hz
1000 Hz 999.936 Hz 1000.064 Hz
10000 Hz 99993.6 Hz 100006.4 Hz
3-11
57LFC/AN
Service Manual
FLUKE 57LFC
OPERATE
STANDBY
8508A
apv007f.eps
Figure 3-4. 8508A Connections to the 57LFC for 4-Wire Ohms
Table 3-5. 4-Wire Ohm Values
Nominal Calibrated Value Measured Value Difference Specification
0 Ω 640E-6 Ω
1 Ω 640E-6 Ω
1.9 Ω 1.280E-3 Ω
10 Ω 2.560E-3 Ω
19 Ω 5.120E-3 Ω
100 Ω 6.40E-3 Ω
190 Ω 12.80E-3 Ω
1.0E+ Ω3 64.0E-3 Ω
1.9E+3 Ω 128.0E-3 Ω
10.0E+3 Ω 640.0E-3 Ω
19.0E+3 Ω 1.280 Ω
100.0E+3 Ω 6.40 Ω
190.0E+3 Ω 12.80 Ω
1.0E+6 Ω 64.0 Ω
1.9E+6 Ω 128.0 Ω
10.0E+6 Ω 640.0 Ω
3-12
19.0E+6 Ω 1280.0 Ω
*Note: Calibrated ohm values are measured and stored during calibration. These values can be accessed
remotely or from the factory test report supplied with the instrument. This measurement assumes four-wire
connection. The measured value is made with a Fluke 8508A or equivalent.
Calibration and Verification
FLUKE 57LFC
OPERATE
STANDBY
8508A
Figure 3-5. 8508A Connections to the 57LFC for 2-Wire Compensated Ohms
Table 3-6. 2-Wire Ohm Values
Nominal Calibrated Value Measured Value Difference Specification
Verification Tests 3
apv008f.eps
0 Ω 0.0013 Ω
1 Ω 0.0013 Ω
1.9 Ω 0.0019 Ω
10 Ω 0.0032 Ω
19 Ω 0.0058 Ω
100 Ω 0.0070 Ω
190 Ω 0.0134 Ω
1.00E+03 Ω 0.0704 Ω
1.90E+03 Ω 0.1344 Ω
1.00E+04 Ω 0.7040 Ω
1.90E+04 Ω 1.4080 Ω
1.00E+05 Ω 7.0400 Ω
1.90E+05 Ω 14.0800 Ω
3-13
57LFC/AN
Service Manual
DC Current Test
The dc current amplitude accuracy test verifies the accuracy of dc current at the
Calibrator output terminals. First, use the 5720A to characterize all the points in Table
3-7. Next, connect the 8508A to the appropriate terminals on the Calibrator (as shown in
Figure 3-6) and verify the Calibrator is within the limits shown in Table 3-7. Maximum
compliance voltage is 4 V in 2.2 A range and 10 V on other ranges.
FLUKE 57LFC
OPERATE
STANDBY
8508A
apv009f.eps
Figure 3-6. 8508A Connections to the 57LFC for DC Current Measurement
Table 3-7. DC Current Readings
Range Amplitude Reading Upper Limit Lower Limit
200.0E-6 000.0E+0 16.00E-9 -16.00E-9
200.0E-6 219.0E-6 219.082880E-6 218.917120E-6
200.0E-6 -219.0E-6 -218.917120E-6 -219.082880E-6
2.0E-3 0.00E+00 40.0E-9 -40.00E-9
2.0E-3 2.19E-3 2.1907328E-3 2.1892672E-3
2.0E-3 -2.19E-3 -2.1892672E-3 -2.1907328E-3
20.0E-3 0.00E+00 200.00E-9 -200.00E-9
20.0E-3 21.90E-3 21.907168E-3 21.892832E-3
20.0E-3 -21.90E-3 -21.892832E-3 -21.907168E-3
200.0E-3 000.0E+0 2.00E-6 -2.00E-6
200.0E-3 219.0E-3 219.0717E-3 218.9283E-3
3-14
200.0E-3 -219.0E-3 -218.9283E-3 -219.0717E-3
2.0 0.00 32.00E-6 -32.00E-6
2.0 2.19 2.1910067 2.1889933
2.0 -2.19 -2.1889933 -2.1910067
Calibration and Verification
Verification Tests 3
AC Current Test
The ac current amplitude accuracy test verifies the accuracy of AC Current at the
Calibrator output terminals. First use the 5720A to characterize all the points in Table 3-
8. Next, connect the equipment as shown in Figure 3-7 and verify the Calibrator is within
the limits shown in Table 3-8. Maximum compliance voltage is 4 V in 2.2 A range and
7 V on other ranges
FLUKE 57LFC
OPERATE
STANDBY
8508A
Figure 3-7. 8508A Connections to the 57LFC for AC Current Measurement
apv010f.eps
3-15
57LFC/AN
Service Manual
Table 3-8. AC Current Limits
Range Amplitude Frequency Reading Upper Limit Lower Limit
Connect the Calibrator to the 8508A as shown in Figure 3-8. Apply the load to the 8508A
terminals. For safety reasons, please observe the power limits of the resistors used in the test. See
Table 3-9 for power limits.
• Apply the maximum dc current output (1.8 Ω load for 4 V compliance voltage) when set
to 2.19 A dc.
• Verify that the current remains at the correct limit by measuring the current as described
in the resistance accuracy test earlier in this Chapter.
FLUKE 57LFC
OPERATE
STANDBY
8508A
1.8
Figure 3-8. 8508A Connections to the 57LFC for Load Current Compliance Test
Table 3-9. Current Output Compliance Limits
Amplitude Frequency Shunt Reading Upper Limit Lower Limit
2.19 A 0 1.8 Ω2.1910067 2.1889933
apv011f.eps
Voltage Output Compliance Test
XWWarning
This instrument is capable of outputting lethal voltages.
Observe all safety precautions while performing this test.
Connect the Calibrator to the 8508A as shown in Figure 3-9. Apply the load to the 8508A
terminals. For safety reasons, please observe the power limits of the resistors used in the
test. Table 3-10 contains the test limits.
• Apply the maximum load (440 Ω for 50 mA) to the dc voltage output when set to
21.9 V dc (using 8508A to measure).
• Verify that the voltage is at the correct limit.
• Apply the maximum load (440 Ω) to the ac voltage output when set to 100 kHz and
21.9 V rms (using 8508A to measure).
• Verify that the voltage is at the correct limit.
• Apply the maximum load (11 kΩ for 20 mA) to the dc voltage output when set to
219 V dc (using 8508A to measure).
•Verify that the voltage is at the correct limit.
3-17
57LFC/AN
Service Manual
• Apply the maximum load (11 kΩ) to the ac voltage output when set to 1 kHz and
219 V rms (using 8508A to measure).
•Verify that the voltage is at the correct limit.
apv012f.eps
Figure 3-9. 8508A Connections to the 57LFC for Voltage Compliance Testing
Table 3-10. Voltage Output Compliance Limits
Range Amplitude Frequency Reading Upper Limit Lower Limit
20 V 21.9 0 21.9003696 V 21.8996304 V
20 V 21.9 100.0E+3 21.9363200 V 21.8636800 V
200 V 219 0 219.005798 V 218.994201 V
200 V 219 1kHz 219.1195 V 218.8805 V
3-18
Calibration and Verification
Verification Tests 3
Harmonic Test Levels for AC Volts
The harmonic ac voltage test verifies that the output ac signal has a limited amount of
noise in the signal. For these tests, the use of the distortion analyzer or spectrum analyzer
is required. Follow the vendor's specifications for setting up those instruments. The
connection used will depend on which test instrument is used. Figure 10 shows the set up
used for a Booton 1130A and Agilent 4411A instrument. The Booton is used below
30 kHz and the Agilent is used above 30 kHz. A set of test limits is provided in
Table 3-11.
FLUKE 57LFC
OPERATE
STANDBY
Resistor Divider
with Optional
Switch Box
S1
2M/20K
Resistor
Divider
Figure 3-10. Harmonic Test Setup
S2
Coax Cables
Booton 1130A
Hi Input
Agilent 4411A
Input
apv013f.eps
3-19
57LFC/AN
Service Manual
Table 3-11. Harmonic Test Values for AC Volts
Maximum
Amplitude Frequency Load Reading
20.0E-3 10.0E+0 0.600%
20.0E-3 45.0E+0 0.485%
20.0E-3 20.0E+3 0.485%
20.0E-3 50.0E+3 0.600%
20.0E-3 100.0E+3 0.700%
200.0E-3 10.0E+0 0.195%
200.0E-3 45.0E+0 0.080%
200.0E-3 20.0E+3 0.080%
200.0E-3 50.0E+3 0.195%
200.0E-3 100.0E+3 0.245%
2.0 10.0E+0 0.160%
Distortion
2.0 45.0E+0 0.045%
2.0 20.0E+3 0.045%
2.0 50.0E+3 0.160%
2.0 100.0E+3 0.210%
20.0 10.0E+0 0.160%
20.0 45.0E+0 0.045%
20.0 20.0E+3 0.045%
20.0 50.0E+3 0.210%
20.0 100.0E+3 0.510%
200.0 10.0E+0 0.155%
200.0 45.0E+0 0.055%
200.0 20.0E+3 0.055%
219.0 50.0E+3 0.805%
118.0 100.0E+3 1.008%
2 10 40 Ω 0.160%
2 100.0E+3 40 Ω 0.210%
3-20
14.2 10 400 Ω 0.164%
14.2 100.0E+3 400 Ω 0.514%
219 50.0E+3 22000 Ω 0.805%
Harmonic AC Current Test
The harmonic ac current test verifies that the output ac signal has a limited amount of
noise in the signal. A distortion analyzer is required for this test. Follow the vendor's
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