Fairchild Semiconductor TMC2242AX1 Datasheet

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Features
• TMC2242A and TMC2242B are pin-compatible with TMC2242
• User selectable interpolate gain, -6 dB or 0 dB (2242B)
• User selectable 2:1 decimation, 1:2 interpolation, and equal-rate filter modes
• Passband ripple <
±
0.01 dB
• Stopband rejection 59.4 dB from 0.28 to 0.50 x f
s
• Cascading two TMC2242A or TMC2242B meets CCIR 601 low-pass filter requirement
• Dedicated 12-bit 2's complement input data port and 16-bit output data port with user-selectable rounding from 9 to 16 bits
• Two's complement or offset binary output format
• Built-in limiter prevents overflow
• Single +5 Volt power supply operation
• Small 44-Lead PLCC and 44-Lead MQFP
Applications
• Low-cost video filtering
• Chrominance bandwidth limiter
• Simple, inexpensive video D/A post-filters
• Reduced cost and complexity for A/D anti-aliasing filters
• High-performance digital low-pass filters
• Digital waveform reconstruction post-filtering
• Telecommunications
• Direct digital synthesis
• Radar
Description
The TMC2242A and TMC2242B are fixed-coefficient lin­ear-phase half-band (low-pass) digital filters. They can be used to halve or double the sampling rate of a digital signal. When used as a decimating post-filter with a double-speed oversampling A/D con verter , they greatly reduce the cost and complexity of anti-aliasing filters required ahead of the A/D converter. When used as an interpolating pre-filter with a double-speed oversampling D/A converter, the TMC2242A and TMC2242B significantly reduce the design complexity and production cost of reconstruction filters used on D/A outputs.
The TMC2242A and TMC2242B user selects the mode of operation (decimate, interpolate, or equal-rate) and round­ing. The TMC2242A and TMC2242B accept 12-bit 2's com­plement data at up to 60 MHz and output saturated (overflow-protected) 2's complement or offset binary data rounded to from 9 to 16 bits. Within the speed grade I/O limit, the output sample rate may be 1/2, 1, or 2 times the input sample rate.
Block Diagram
SI
11-0
CLK
DEC
INT
SYNC
12
12
12
12 16
16
16
SO
15-0
TCO RND
2-0
55 Tap
FIR
Filter
Round
and
Limit
3
Control
OE
Interpolate 0-1-0-1
Decimate, Equal Rate 1-1-1-1
65-2242A-01
TMC2242A/TMC2242B
Digital Half-Band Interpolating/Decimating Filter
12-bit In/16-bit Out, 60 MHz
Rev. 1.2.0
PRODUCT SPECIFICATION TMC2242A/TMC2242B
2
The filter response is flat to within
±
0.01 dB from 0.00 to
0.22 x f
s
, with stopband attenuation greater than 59.4 dB
from 0.28 x f
s
to the Nyquist frequency . The response is 6 dB
down at 0.25 x f
s
. Symmetric-coefficient filters such as the TMC2242A and TMC2242B have linear phase response. Full compliance with the CCIR-601 standard of 12 dB atten­uation at 0.25 x f
s
is achieved by cascading two parts.
The TMC2242A and TMC2242B are fabricated on an advanced submicron CMOS process. They are available in a 44-lead J-lead PLCC package. Performance is guaranteed from 0
°
C to 70
°
C.
Functional Description
The TMC2242A and TMC2242B implement a fixed-coeffi­cient linear-phase Finite Impulse Response (FIR) filter of 55 effective taps, with special rate-matching input and output structures to facilitate 2:1 decimation and 1:2 interpolation. The faster of either the input or output registers will operate at the guaranteed maximum clock rate (speed grade). The total internal pipeline latency from the input of an impulse to the corresponding output peak (digital group delay) is 34 cycles; the 55-value output response begins after 7 clock cycles and ends after 61 cycles.
To perform interpolation, the chip slows the effective input register clock rate to half the output rate. It internally inserts zeroes between the incoming data samples to "pad" the input data rate to match the output rate.
To perform decimation, the chip sets the output register clock rate to half of the input rate. One output is then obtained for every two inputs.
For interpolation, the user should bring SYNC HIGH for at least one clock cycle, returning it LOW with the first desired input data value. When interpolating, the chip will then con­tinue to accept a new data input on each alternate rising edge of the clock. When decimating, the chip will present one out­put value for every two clock cycles. The user may leave SYNC LOW or toggle it once per rising clock edge, with equivalent performance.
The output data format is two's complement if TCO is HIGH, inverted of fset binary if LOW. The user can tailor the output data word width to his/her system requirements using the Rounding control. As shown in Table 4, the output is half-LSB rounded to the resolution selected by the value of RND
2-0
. The asynchronous three-state output enable control
simplifies connection to a data bus with other drivers.
Table 1. Operating Modes
Note:
1. With 15-bit overflow protection. All other modes on both parts limit to 16 bits.
DEC
INT TMC2242A TMC2242B
0 0 Equal Rate Interpolate (0 dB) 0 1 Decimate Decimate 1 0 Interpolate (-6 dB) Interpolate (-6 dB)
1
1 1 Equal Rate Equal Rate
Pin Assignments
65-2242A-02
SO
12
SO
11
SO
10
SO
9
SO
8
GND
V
DD
SO
7
SO
6
SO
5
SO
4
GND V
DD
SI
10
SI
9
SI
8
SI
7
SI
6
SI
5
SI
4
SI
3
V
DD
SO13SO14SO15OE
TCO
DEC
INT
SYNC
CLK
GND
SI
11
SO3SO2SO1SO
0
RND2RND1RND
0
SI0SI1SI
2
GND
7 8 9 10 11 12 13 14 15 16 17
39 38 37 36 35 34 33 32 31 30 29
1819202122232425262728
65432
1
4443424140
TMC2242A TMC2242B
65-2242A-02
SO
12
SO
11
SO
10
SO
9
SO
8
GND
V
DD
SO
7
SO
6
SO
5
SO
4
GND V
DD
SI
10
SI
9
SI
8
SI
7
SI
6
SI
5
SI
4
SI
3
V
DD
SO13SO14SO15OE
TCO
DEC
INT
SYNC
CLK
GND
SI
11
SO3SO2SO1SO
0
RND2RND1RND
0
SI0SI1SI
2
GND
1 2 3 4 5 6 7 8 9 10 11
33 32 31 30 29 28 27 26 25 24 23
1213141516171819202122
4443424140393837363534
TMC2242A TMC2242B
Description
(continued)
44 Lead PLCC
44 Lead MQFP
TMC2242A/TMC2242B PRODUCT SPECIFICATION
3
Pin Descriptions
Pin Name
Pin Number
Pin Function DescriptionPLCC MQFP
Timing Controls
INT
44 38
Interpolate. When INT is LOW and DEC is HIGH, the input data register runs at
1/2 the CLK rate and zeros are inserted in the data stream between valid input values, reducing gain by 6dB. The TMC2242A and TMC2242B interpolate and output results at the full CLK rate.
DEC 139 Decimate. When DEC is LOW and INT is HIGH, the input data register runs at
the full CLK rate. In this mode, the TMC2242A and TMC2242B decimate and output results at 1/2 the CLK rate.
When INT
= DEC, the TMC2242A is in equal rate mode. When both INT and DEC are HIGH, the TMC2242B is likewise in equal-rate mode, but when both INT and DEC are LOW, the TMC2242B interpolates with unity gain.
In equal-rate mode, the input and output sample rates equal the chip clock rate.
SYNC 43 37
Synchronization. Incoming data are synchronized by holding SYNC HIGH on
CLK N–1 and LOW on CLK N when the first input data word is present on SI
11-0
.
If DEC
= INT=1 (equal rate mode), SYNC is inactive. SYNC may be held LOW
until resynchronization is desired, or it may be toggled at 1/2 the CLK rate.
CLK 42 36
Clock. The TMC2242A and TMC2242B operate from a single master clock. All
internal registers, except the output register in decimation mode, are strobed on the rising edge of CLK. All timing parameters are referenced to the rising edge of CLK.
Data Inputs
SI
11-0
40, 37-30, 27-25
34, 31-24, 21-19
Input Data Port. A 12-bit 2's-complement input word is registered by the rising
edge of CLK. In Interpolate Mode, SI
11-0
is registered on every other CLK
(synchronized by SYNC). SI
11
is the MSB.
Data Outputs
SO
15-0
4-11, 14-21
42-44, 1-5, 8-15
Output Data Port. A 16-bit 2's-complement output result is available after the
rising edge of CLK. In Decimate Mode, SO
15-0
is registered on every other CLK
(synchronized by SYNC). SO
15-0
is rounded according to the state of RND
2-0
.
SO
15
is the MSB.
The limiter circuitry ensures that for internal overflow, a valid full-scale output (7FFF or 8000) will be generated. With the TMC2242B in interpolate mode with
-6dB gain, limits are 3FFF and C000 (TCO=1).
Output Controls
OE
341 Output Enable. When LOW, SO
15-0
are enabled. When HIGH, SO
15-0
are in a
high-impedance state. OE
is asynchronous with respect to CLK.
TCO 2 40
Output Format. When TCO is HIGH, output data are in signed 2's-complement
format. When LOW, the output is inverted offset binary.
RND
2-0
22-24 16-18 Rounding Select. These inputs set the position of the effective LSB of the output
result. Outputs below the rounding bit are zeroed (Table 4).
Power
V
DD
13,29,387, 23,
32
Supply Voltage. +5 Volt power inputs. These should come from the same power
source and be decoupled to GND.
GND 12,28,
39,41
6, 22, 33, 35
Ground. Ground inputs should be connected to the system digital ground plane.
PRODUCT SPECIFICATION TMC2242A/TMC2242B
4
Absolute Maximum Ratings
(beyond which the device may be damaged)
1
Notes:
1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.
Operating Conditions
Parameter Conditions Min Max Units
Supply Voltage -0.5 7.0 V Input Voltage -0.5 V
DD
+ 0.5 V
Output Applied Voltage
2
-0.5 V
DD
+ 0.5 V
Externally Forced Current
3,4
-3.0 +6.0 mA Short Circuit Duration Single output in HIGH state to ground 1 sec Operating Temperature (Case) -20 110
°
C
Junction Temperature 140
°
C
Lead Soldering Temperature 10 seconds 300
°
C
Storage Temperature -65 150
°
C
Parameter Conditions Min Nom Max Units
V
DD
Power Supply Voltage 4.75 5.0 5.25 V
f
CLK
Clock frequency TMC2242A, B 30 MHz
TMC2242A-1,B-1 40 MHz TMC2242A-2,B-2 60 MHz
t
PWH
CLK pulse width, HIGH 6 ns
t
PWL
CLK pulse width, LOW 6 ns
t
S
Input Data Set-up Time 6 ns
t
H
Input Data Hold Time 1 ns
V
IH
Input Voltage, Logic HIGH 2.0 V
V
IL
Input Voltage, Logic LOW 0.8 V
I
OH
Output Current, Logic HIGH -2.0 mA
I
OL
Output Current, Logic LOW 4.0 mA
T
A
Ambient Temperature, Still Air 0 70
°
C
TMC2242A/TMC2242B PRODUCT SPECIFICATION
5
Electrical Characteristics
Switching Characteristics
Parameter Conditions Min Typ Max Units
I
DD
Total Power Supply Current
V
DD
= Max, C
LOAD
=25pF, f
CLK
=Max TMC2242A,B 150 mA TMC2242A-1,B-1 195 mA TMC2242A-2,B-2 290 mA
I
DDU
Power Supply Current, Unloaded
V
DD
= Max, OE
= HIGH, f
CLK
=Max TMC2242A,B 120 mA TMC2242A-1,B-1 155 mA TMC2242A-2,B-2 230 mA
I
DDQ
Power Supply Current, Quiescent
V
DD
= Max, CLK = LOW 5 mA
C
PIN
I/O Pin Capacitance 5 pF
I
IH
Input Current, HIGH V
DD
= Max, V
IN
= V
DD
±
10
m
A
I
IL
Input Current, LOW V
DD
= Max, V
IN
= 0 V
±
10
m
A
I
OZH
Leakage Current, HIGH OE
= HIGH, V
OUT
= V
DD
±
10
m
A
I
OZL
Leakage Current, LOW OE
= HIGH, V
OUT
= 0 V ±10 mA
I
OS
Short-Circuit Current VDD = Max, Output = HIGH, one pin to
ground, one second duration max.
-20 -80 mA
V
OH
Output Voltage, HIGH SO15-0, IOH = Max 2.4 V
V
OL
Output Voltage, LOW SO15-0, IOL = Max 0.4 V
Parameter Conditions Min Typ Max Units
t
DO
Output Delay Time C
LOAD
= 25 pF 15 ns
t
HO
Output Hold Time C
LOAD
= 25 pF 2.5 ns
t
ENA
Output Enable Time C
LOAD
= 0 pF 12 ns
t
DIS
Output Disable Time C
LOAD
= 0 pF 12 ns
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