Fairchild Semiconductor TMC22091 Datasheet

www.fairchildsemi.com

TMC22091/TMC22191

Digital Video Encoders/Layering Engine

Features

• All-digital video encoding

• Internal digital oscillators, no crystals required

• Multiple input formats supported
– 24-bit and 15-bit GBR/RGB
–YCBCR422 or 444
– Color indexed

• 30 overlay colors (TMC22191)

• Fully programmable timing

• Supports input pixel rates of 10 to 15 Mpps

• 256 x 8 x 3 color look-up tables (bypassable on
TMC22191)

• 8-bit mask register

• 8-bit composite digital video input

• Hardware and 24-bit data keying

• Synchronizes with TMC22071 Genlocking Video
Digitizer

• 8:8:8 video reconstruction

• SMPTE 170M NTSC or CCIR Report 624 PAL
compatible

• Supports PAL-M and NTSC without pedestal

• Simultaneous S-VIDEO (Y/C) NTSC/PAL output

• 10-bit D/A conversion (three channels)

Logic Symbol

• Controlled edge rates

• 3 power-down modes

• Built-in color bars and modulated ramp test signals

• JTAG (IEEE Std 1149.1-1990) test interface

• Single +5V power supply

• 84 lead PLCC package

• 100 lead MQFP package

Description

The TMC22x91 digital video encoders convert digital com­puter image or graphics data (in RGB, YCBCR, or color
indexed format) or a CCIR-601 signal into a standard analog
baseband television (NTSC or PAL) signal with a modulated
color subcarrier.

Both composite (single lead) and S-VIDEO (separate
chroma and luma) formats are active simultaneously at the
three analog output pins, each of which generates a standard
video-level signal into doubly-terminated 75Ω load.

The TMC22x91 accepts digitized video from the companion
TMC22071 Genlocking Video Digitizer. Soft switching
between video sources is done under either hardware or
programmable data control.

The TMC22191 offers 4-layer keying capability, bypassable
CLUT, and 30 Overlay colors.

BYPASS and OL

OL

D

A

23-0

4-0

PDC

KEY

7-0

7-0
1-0

CS

R/W

24

6

8

8
2

PD

VHSYNC
VVSYNC

INTERFACE

FRAME BUFFER

BYPASS

CVBS

GHSYNC
GVSYNC

GENLOCK

INTERFACE

RESET

INTERFACE

MICROPROCESSOR

on TMC22191 only.

4:0

TMC22x91

DIGITAL

VIDEO

ENCODER

27008A

CHROMA
LUNA
COMPOSITE

V

REF

COMP
R

REF

TDI
TMS
TCK
TDO

LDV
PXCK

The TMC22x91 is fabricated in a submicron CMOS process
and packaged in an 84 Lead Plastic Leadless Chip Carrier, or
in a 100 Lead Metric Quad Flat Pack. Performance is guar­anteed from 0°C to 70°C.

OUTPUT

VIDEO

INTERFACE

ANALOG

INTERFACE

JTAG TEST

CLOCKS

Rev. 1.1.0

TMC22091/TMC22191 PRODUCT SPECIFICATION

Block Diagram

OL

4-0

BYPASS

23-0

KEY
PDC

FORMATTER

MASK, KEY

COMPARATOR

Data Key

PD

VVSYNC

FRAME BUFFER INTERFACE

VHSYNC

G/R/Y MAP
B/G/C

B

R/B/C

R

256 x 8 x 3

COLOR

LOOK-UP

TABLE

BYPASS and OL

R/R-Y

INTER-

B/B-Y

POLATOR
4:2:2/4:4:4

G/Y

on TMC22191 only.

4:0

MATRIX

R-Y
B-Y

LPF

LPF

SYNC,
BLANK

INSERT

CHROMA

MODULATOR

INT

INT

10-bit

D/A

10-bit

D/A

CHROMA

LUMA

GHSYNC
GVSYNC

GENLOCK

INTERFACE

CVBS

7-0

CLOCK CONTROL JTAG

LDV

PXCK

CLOCKS MICROPROCESSOR

Functional Description

The TMC22091 and TMC22191 are totally integrated, fully­programmable digital video encoders with simultaneous
composite and Y/C (S-VIDEO) outputs. The TMC22x91
video outputs are compatible with SMPTE 170M NTSC,
CCIR Report 624 PAL, PAL-M, and NTSC without pedestal
television standards. No external component selection or
tuning is required.

The encoders accept digital image data at the PD port in one
of several formats, which are matrixed into luminance and
chrominance components. The chrominance signals are
modulated onto a digitally synthesized subcarrier. The lumi­nance and chrominance signals are separately interpolated to
twice the pixel rate, and conv erted to analog levels by 10-bit
D/A converters. They are also digitally combined and the
resulting composite signal is output by a third 10-bit D/A
converter. This composite signal may be keyed (pixel rate
switching) with a second composite digital video signal pre­sented to the encoder.

The output video frames may be internally timed by the
TMC22x91, synchronized with the external frame buffer, or
slaved to the companion Genlocking Video Digitizer
(TMC22071). All operational parameters are fully program­mable over a standard microprocessor port.

Table 1 shows the key features that distinguish between the
TMC22091 and TMC22191. All of the information pre­sented in this data sheet applies to both products unless oth­erwise noted. Statements, paragraphs, tables, and figures that
apply to only one or two of the encoders have notation speci­fying the applicable part number.

7:0A1:0

D

RESET

INTERFACE

DIGITAL

SYNC.

GEN.

CS

R/W

INTERFACE

TDI

TCK

TMS

JTAG TEST

SUBCARRIER

SYNTHESIZER

TDO

INT

INTERPOLATION

FILTERS

VIDEO

SWITCH

10-bit

D/A

D/A

REF.

COMPOSITE

V

REF
COMP
R

REF

ENCODED VIDEO OUTPUT

ANALOG

INTERFACE

27006A

Timing

The encoder operates from a single clock at twice the system
pixel rate. This frequency may be set between 20 MHz and
36 MHz (pixel rates of 10 Mpps to 18 Mpps). Within this
range are included CCIR-601, D2, and square-pixel formats,
as well as a variety of computer-specific pixel rates. An array
of programmable timing registers allows the software selec­tion of all pertinent signal parameters to produce NTSC
(with or without 7.5 IRE pedestal) and PAL, and PAL-M
outputs.

Table 1. Comparing the TMC22x91 Encoders

Feature TMC22091 TMC22191

OL

pixel inputs for 30

4-0

No Yes

overlay colors
Number of video layers

2 4

supported
BYPASS input for

No Yes

bypassing CLUTs

Input Formatting

The input section accepts a variety of video and graphics for­mats, including 24-bit GBR and RGB, 15-bit GBR and
RGB, YCBCR422, YCBCR444, and 8-bit color-indexed data
(Figure 1a and 1b).

The input section of the TMC22x91 includes a key compara­tor which monitors the pixel data port with three independent
8-bit comparators, and invokes a video k ey when the selected
registers match the incoming data.

2

PRODUCT SPECIFICATION TMC22091/TMC22191

Mask Register

A Mask Register is provided which is logically ANDed with
incoming color-index data to facilitate pixel animation and
other special graphics effects. The Mask Register is ahead of
the Data Key comparators and is enabled only when color­index input is selected. Mask Register programming and
operation are similar to that of the 171/176 family of graph­ics RAMDACS.

Color Lookup Table

The Color Lookup Table (CLUT) is a 256 x 8 x 3 random­access memory. It provides means for offset, gain, gamma,
and color correction in RGB and YCBCR operating modes. It
provides a full 24-bit color lookup function for color-index
mode. It can be loaded in the same manner as a standard
VGA RAMDAC.

MODE

GBR444

MSB
23

G

7

16

15

G B R

G0B

7

Colorspace Conversion Matrix and
Interpolator

The matrix converts RGB data (whether from RGB inputs or
color-indexed CLUT data) into Y, B-Y, R-Y format for
encoding. In input configurations where the pixel input is
already in Y, B-Y, R-Y format, the matrix is bypassed. When
pixel data is input in YCBCR422 format, the interpolation fil­ters produce YCBCR444 for encoding.

Sync Generator

The TMC22x91 can operate in Master, Genlock, or Slave
modes. In Master and Genlock modes, the encoder internally
generates all timing and sync signals, and provides Horizon­tal Sync, Vertical Sync, and Pixel Data Control (PDC) to the
external frame buffer circuitry. PDC is independently select­able to function as an input or an output. In Genlock mode,
the TMC22x91 timing is controlled by the TMC22071 Gen­locking Video Digitizer over the CVBS
and GHSYNC. The encoder, in turn, produces VHSYNC,
VVSYNC, and PDC for the frame buffer interface.

Format Control Register

8 7

B0R

7

LSB

R

0

0

bus, GVSYNC,

7-0

MSB LSB

00011000

RGB444

YCBCR444

YCBCR422

COLOR INDEX

GBR15

RGB15

R

7

Y

7

Y

7

R G B

Y C
Y C

R0G

Y0C

Y

0

R

G0B

7

CB0R

R7

C

B0

C

R0

P

7

G

B

0

4

R

G

0

4

C

Pixel

B

R

0

4

G

B

0

4

7

B7

C

B7

C

R7

G

4

R

4

B

/

C

B

G B R
R G B

R

B

R

P

R

B

24300A

R0

00010000

0

00011100

00011101

0001X011

0

00011010

0

00010010

0

Figure 1a. Pixel Data Format

3

TMC22091/TMC22191 PRODUCT SPECIFICATION

MODE

GBR444

RGB444

YCBCR444

YCBCR422

COLOR INDEX

RGB15

GBR15

MSB
23

G

7

R

7

Y

7

Y

7

P

7

R

4

G

4

and CR are loaded on alternate LDV cycles

*C

B

G B R
R G B
Y C

Y C

Pixel

R G B

R

0

G B R

G

0

Figure 1b. Pixel Data Format (TMC22191 when CLUTs are Bypassed)

16

G0B

R0G

Y0C

Y

0

P

0

15

7

7

B7

C

B7

P

7

G

4

B

4

In Slave mode, VHSYNC, VVSYNC, and PDC (optional)
are inputs to the TMC22x91. These inputs determine when
new lines, frames, and active picture areas begin. The exter­nal controlling circuitry needs to establish the correct timing
for these signals.

Horizontal and vertical synchronization signals are digitally
generated by the TMC22x91 with controlled rise and fall
times on all sync edges, the beginning and end of active
video, and the burst envelope. All elements of horizontal
sync timing are programmable, as are the frequency, phase,
and duration of color burst.

Video Input

The TMC22x91 accepts genlocked synchronization data and
digital composite video signals from the TMC22071 Gen­locking Video Digitizer over the 8-bit CVBS bus. The
encoder synchronizes its digital subcarrier oscillator to the
video input from the TMC22071 with this data. The compos­ite video data output from the TMC22071 is passed to the
internal video switch for keying with the encoded pixel data.

Chroma Modulator

A 32-bit digital subcarrier synthesizer feeds a quadrature
modulator, producing a digital chrominance signal. The rela­tive phases of the burst and active video portions of the sub­carrier can be individually adjusted to compensate for
external phase errors and to effect a hue control.

Interpolation Filters

Interpolation filters on the luminance and chrominance sig­nals double the pixel rate in preparation for D/A conversion.
This band-limited process greatly simplifies the output filter­ing required following the D/A converters and dramatically
reduces sin(x)/x distortion.

B

B

Pixel

G

0

B

0

Format Control Register

8 7

B0R

7

G0B

7

CB0C

R7

*

CB0C

R7

P

P

7

0

B

4

R

4

C

R

C

R

Pixel

B

R

LSB

0

MSB LSB

R

B

C

R0

*

C

R0

P

0

0

24393A

01011000

0

01010000

0

0101X000

0101X001

0101X011

0

01010010

01011010

An interpolation filter on the CVBS data similarly raises the
sample rate of the video signal, for mixing with the encoded
pixel data.

Composite Video Switch

The Composite Video Switch selects between the composite
video input (CVBS) and the composite encoded pixel data
on a pixel-by-pixel basis, under the control of a key function.

Keying may be managed by hardware or software. The hard­ware key input (KEY pin) directly controls the video switch.
The encoder may be programmed to operate with a data key,
represented by three 8-bit registers that compare with the 24
input bits. They operate in all input modes and may be indi­vidually enabled or disabled.

D/A Converters

The analog outputs of the TMC22x91 are the outputs of
three 10-bit D/A converters, operating at twice the pixel
clock rate. The outputs are capable of driving standard video
levels into a doubly-terminated 75Ω coaxial video cable
(37.5Ω total load). An internal voltage reference is provided
which can be used to provide reference current for the three
D/A converters. For accurate video levels, an external fixed
or variable voltage reference source is recommended. The
video signal levels from the TMC22x91 may be adjusted to
overcome the insertion loss of analog low-pass output filters.

The D/A converters on the TMC22x91 may be powered­down via Control Register 0E bits 5 and 6. The
COMPOSITE D/A is controlled by bit 6 and the LUMA and
CHROMA D/A converters are controlled by bit 5.

4

PRODUCT SPECIFICATION TMC22091/TMC22191

Microprocessor Interface

The microprocessor interface employs a 13 line format. The
RESET pin sets all internal state machines to their initialized
conditions, disables the analog outputs, sets the internal
SRESET bit LOW (reset condition), and places the encoder
in a power-down mode. All register and CLUT data are
maintained in power-down mode. If the HRESET bit is set
HIGH, line 1 field 1 is started when RESET goes HIGH, and
SRESET is ignored. If HRESET is LOW, the encoder
remains idle after RESET goes HIGH until Control Register
bit SRESET

Two address lines are provided and decoded for access to the
internal Control Registers and CLUT. Control Registers and
CLUT are accessed by loading a desired address through the
8-bit D
that address. Both the CLUT and the Control Registers are
self-indexing, allowing continuous reads or writes to succes­sive addresses.

is set HIGH, which initiates line 1 field 1.

port, followed by the desired data read or write for

7-0

JTAG Test Interface

The TMC22x91 includes a standard 4-line JTAG (IEEE Std

1149.1-1990) test interface port, providing access to all digi­tal input/output data pins. This is provided to facilitate com­ponent and board-level testing.

Test/Validation Mode

The TMC22x91 may be configured to produce standard
color bars or a 40 IRE modulated (or unmodulated) video
ramp, independent of any pixel or video data input. Color

bars are useful as an idle system output signal. The test sig­nals may be used to verify proper operation of the analog
video signal chain.

TMC22090/TMC22190 Compatibility

The TMC22090 and TMC22190 are earlier versions of the
TMC22091 and TMC22191, respectively. They lack the fol­lowing features of the newer versions:

1. Selectable Setup (to support NTSC EIA-J video output
for Japan)

2. PAL-M format (for South American applications)

3. Extended EH and SL intervals (to support pixel rates
above 15 Mpps)

4. Individual D/A power-down (to reduce total dissipation
when some outputs are not required)

5. Luminance I/O processing (to reduce flicker in graphics
applications)

These features are controlled by registers 0E and 0F, and
enabled by setting Register OE bit 7 to ONE. If an applica­tion of the TMC22x90 is programmed with this bit set to
ZERO (as recommended in the product documentation) then
the corresponding TMC22x91 will perform identically.
Though the earlier parts continue to be available, it is recom­mended that the newer devices be used in new designs for
the additional flexibility. Older designs may be readily
converted to the newer versions to take advantage of the
added features and lower cost of the later technology.

5

TMC22091/TMC22191 PRODUCT SPECIFICATION

Pin Assignments

84 Lead PLCC

1

84

65-3751-01

Pin Name Pin Name

TDO

1
0
GND

7
6
5
4
3
2
1
0

22

2
1
0

TCK

23

TMS

24

TDI

25

D

26

GND

V

27

DD

BYPASS (TEST)

28

OL4 (TEST)

29

V

30

REF

R

31

REF

A

32

GND

COMPOSITE

33

A

34

GND

LUMA

35

A

36

GND

CHROMA

37

A

38

GND

COMP

39

V

40

DDA

V

41

DDA

V

42

DDA

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

CVBS
CVBS
CVBS
KEY
RESET
CS
R/W
A
A
D
PDC
VHSYNC
VVSYNC
D
D
D
D
D
D
D
D

Pin Name Pin Name

V

43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

V

DDA

CVBS
CVBS
CVBS
CVBS
OL3 (TEST)
OL2 (TEST)
OL1 (TEST)
OL0 (TEST)
PD

23

PD

22

PD

21

PD

20

PD

19

PD

18

PD

17

PD

16

PD

15

PD

14

PD

13

PD

12

64

DD

D

65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84

GND

PD

11

PD

10

PD

9

PD

8

PD

7

PD

6

PD

5

PD

4

PD

3

PD

2

PD

1

PD

0

LDV
PXCK
D

GND

V

DD

GVSYNC
GHSYNC
CVBS

7
6
5
4

3

100 Lead MQFP

100

Note: Pin names in parentheses apply to TMC22091.

Pin Name Pin Name

PD

NC

1

COMPOSITE

2

NC

3

A

4

GND

LUMA

5

A

6

GND

NC

7

CHROMA

8

A

9

GND

COMP

10

NC

1

65-3751-02

11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

NC
V

DDA

V

DDA

V

DDA

V

DDA

V

DDA

CVBS
CVBS
CVBS
CVBS
OL3 (TEST)
OL2 (TEST)
OL1 (TEST)
OL0 (TEST)

26

23

27

PD

22

28

NC

29

NC

30

NC

31

PD

21

32

PD

20

33

PD

19

34

PD

18

35

PD

17

36

PD

16

37

PD

15

38

PD

14

39

PD

13

40

PD

12

41

V

DD

42

D

GND

43

PD

7
6
5
4

11

44

PD

10

45

PD

9

46

PD

8

47

PD

7

48

PD

6

49

PD

5

50

PD

4

Pin Name Pin Name

D

51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75

PD

3

NC
NC
NC
NC
PD

2

PD

1

PD

0

LDV
PXCK
D

GND

V

DD

GVSYNC
GHSYNC
CVBS
CVBS
CVBS
CVBS
NC
KEY
RESET
CS
R/W
A

1

A

0

76

GND

77

PDC

78

NC

79

NC

80

VHSYNC

81

VVSYNC

82

D

7

83

D

6

84

D

5

85

D

4

86

D

3

87

D

2

88

D

1

89

D

0

90

3
2
1
0

TDO

91

TCK

92

TMS

93

TDI

94

D

GND

95

V

DD

96

BYPASS (TEST)

97

OL4 (TEST)

98

V

REF

99

R

REF

100

A

GND

Note: Pin names in parentheses apply to TMC22091.

6

PRODUCT SPECIFICATION TMC22091/TMC22191

Pin Descriptions

Pin Number

84-Lead

Pin Name
Clocks

PXCK 79 60 TTL Master Clock Input. This 20 to 30 MHz clock is internally

LDV 78 59 TTL Pixel Data Load Clock. On each rising edge of LDV, data on

Frame Buffer Interface

PD

23-0

VHSYNC 12 80 TTL Horizontal Sync I/O. In Master and Genlock modes, the

VVSYNC 13 81 TTL Vertical Sync I/O. In separate V and H sync Master and

PDC 11 77 TTL Pixel Data Control. In Master mode, the TMC22x91 forces

KEY 4 70 TTL Hardware Key Input. When the HKEN control bit is set HIGH

PLCC

52-63,

66-77

100-Lead

MQFP

26, 27,

31-40,
43-51,

56-58

Value Pin Function Description

divided by 2 to generate the internal pixel clock, PCK, which a
LOW on RESET forces LOW. PXCK drives the entire
TMC22x91, except the asynchronous microprocessor interface
and the semi-synchronous LDV data input clock. All internal
registers are strobed on the rising edge of PXCK.

are latched into the input preload register, for transfer

PD

23-0

into the input demultiplexer on the next rising edge of PCK.

TTL Pixel Data Inputs. In YCBCR, GBR, RGB, and color-indexed

mode, pixel data enter the TMC22x91 on PD
format is found in Figures 1a and 1b. LDV is the clock that
controls the loading of pixel data.

TMC22x91 outputs horizontal sync on this pin. In Slave modes,
the TMC22x91 accepts and locks to horizontal sync input on
this pin (with vertical sync on VVSYNC). VHSYNC and
VVSYNC must be coincident since they are clocked into the
TMC22x91 on the same rising edge of PXCK.

Genlock modes, the TMC22x91 outputs vertical block sync
(VVSYNC LOW for the 2.5 (PAL) or 3 (NTSC) lines on which
vertical sync pulses occur). In composite sync (H and V sync
on same signal) Master and Genlock modes, the TMC22x91
outputs horizontal sync, vertical sync, and equalization over
this pin. In Slave mode, the TMC22x91 accepts and locks to
vertical sync input on this pin (with horizontal sync on
VHSYNC). VHSYNC and VVSYNC must be coincident such
that they are clocked into the TMC22x91 on the same rising
edge of PXCK.

PDC HIGH when and only when it wants active video from the
frame buffer. During blanking (syncs, equalization, burst, and
porches), it forces PDC LOW, signaling that it will ignore any
data presented over PD
forcing it HIGH allows the TMC22x91 to receive PD during the
active video state.

and hardware key pin, KEY, is HIGH, video data entering on
CVBS
signal is pipelined so the pixel that is presented to the PD port
when the KEY signal is invoked is at the midpoint of the soft
key transition. When HKEN is LOW, KEY is ignored. Like PD
data, KEY is clocked into the TMC22x91 on the rising edge of
LDV.

are routed to the COMPOSITE output. This control

7-0

. When PDC is used as an input,

23-0

. The specific

23-0

7

TMC22091/TMC22191 PRODUCT SPECIFICATION

Pin Descriptions (continued)

Pin Number

84-Lead

Pin Name

OL

4-0

BYPASS

Genlock Interface

GHSYNC 83 64 CMOS Genlock Horizontal Sync. In Genlock mode, the TMC22x91

GVSYNC 82 63 CMOS Genlock Vertical Sync. In Genlock mode, the TMC22x91 will

PLCC

29, 48-51 97, 22-25 TTL Overlay Data Inputs (TMC22191 only). 30 of the 256

28 96 TTL CLUT Bypass Control (TMC22191 only). When BYPASS is

CVBS

7-0

Microprocessor Interface

D

7-0

A

1-0

44-47, 84,

1-3

14-21 82-89 TTL Data I/O Port. All control parameters are loaded into and read

8-9 74-75 TTL µProc Port Controls. As in a RAMDAC, this control governs

100-Lead

MQFP

18-21,

65-68

Value Pin Function Description

locations of the CLUT may be reserved for overlay operation.
These CLUT locations are directly accessed by five input pins,
OL

. OL

4-0

pixel basis and select which of the 30 overlay colors is to be
encoded. When all five OL
occurs.

HIGH, the CLUT is in the pixel data path within the TMC22191.
When BYPASS is LOW, pixel data bypasses the CLUT.
BYPASS is active only for certain modes of the Layering
Control Register (LCR) when the Format Control Register bit 6
is HIGH.

will start a new horizontal line (blank-to-sync-edge transition)
with each falling edge of GHSYNC. In non-genlock modes, the
TMC22x91 ignores GHSYNC. The internal pixel clock, PCK, is
aligned with the falling edge of VHSYNC or GHSYNC (Genlock
mode).

start a new vertical sync sequence at line 1 field 1 whenever
GVSYNC and GHSYNC are coincident such that they are
clocked into the TMC22x91 on the same rising edge of PXCK.
If GVSYNC falls at any other time, the TMC22x91 will assume
that this marks the start of field 2, and will ignore it (in odd-field
sync mode) or (in all-field sync mode) respond by generating a
single vertical sync pulse, followed by 2 (PAL) or 2.5 (NTSC)
lines of vertical sync, keyed to the next falling edge on
GHSYNC. See Interface Control Register bit 0 for odd-field and
all-field operation.

TTL Composite Video Inputs. The encoder receives digitized

video, subcarrier phase, and subcarrier frequency over this 8­bit bus at the PCK rate. This data may be provided by the
companion TMC22071 Genlocking Video Digitizer. In Genlock
mode, the TMC22x91 expects subcarrier phase and frequency
data during each line’s horizontal sync interval, as well as video
data when keying is engaged, transferred at the PCK rate.

back over this 8-bit port. For digital testing, the five lower bits
can also serve as a two-cycle 10-bit data output port. For D/A
converter testing, it can be used as a 10-bit two-cycle input
port, facilitating, for example, ramp-based D/A converter
linearity tests.

whether the microprocessor interface selects a table address
or reads/writes table contents. It also governs setting and
verification of the TMC22x91’s internal operating modes, also
over port D

are entered into the TMC22191 on a pixel-by-

4-0

inputs are LOW, no overlay

4-0

.

7-0

8

PRODUCT SPECIFICATION TMC22091/TMC22191

Pin Descriptions (continued)

Pin Number

84-Lead

Pin Name

CS 6 72 TTL Chip Select. When CS is HIGH, the microprocessor interface

R/W 7 73 TTL Bus Read/Write Control. When R/W and CS are LOW, the

RESET 5 71 TTL Master Reset Input. Bringing RESET LOW sets the software

Video Output

COMPOSITE 33 2 1 V

LUMA 35 5 1 V

CHROMA 37 8 1 V

Analog Interface

V

REF

COMP 39 10 0.1 µF Compensation Capacitor. Connection point for 0.1µf

R

REF

JTAG Test Interface

TDI 25 93 TTL Data Input Port. Boundary scan data input port.
TMS 24 92 TTL Scan Select Input. Boundary scan (HIGH)/normal operation

TCK 23 91 TTL Scan Clock Input. Boundary scan clock.
TDO 22 90 TTL Data Output Port. Boundary scan data output port.

Power Supply

V

DD

V

DDA

D

GND

PLCC

30 98 +1.23 V Voltage Reference Input. External voltage reference input,

31 99 392Ω Current-setting Resistor. Connection point for external

27, 64, 81 41, 62, 95 +5 V Positive digital power supply.

40-43 13-17 +5 V Positive analog power supply.

10, 26, 65, 8042, 61, 76, 940.0 V Digital Ground.

100-Lead

MQFP

Value Pin Function Description

port, D
LOW, the microprocessor can read or write parameters over
D

7-0

data to its assigned working registers.

microprocessor can write to the control registers or CLUT over
D

7-0

contents of any CLUT address or control register over D

reset control bit, SRESET, LOW, forcing the internal state
machines to their starting states and disabling all outputs.
Bringing RESET HIGH synchronizes the internal pixel clock
(PCK = PXCK / 2) to maintain a defined pipeline delay through
the TMC22x91. If HRESET is set HIGH, the encoder is enabled
when RESET goes HIGH. If HRESET is LOW, the host restarts
the TMC22x91 by setting SRESET HIGH. RESET does not
affect the CLUT or the control registers, except SRESET.

NTSC/PAL Video. Analog output of composite D/A converter,

P-P

nominally 1.35 volt peak-to-peak into a 37.5Ω load.
Luminance-only Video. Analog output of luminance D/A

P-P

converter, nominally 1.35 volt peak-to-peak into a 37.5Ω load.
Chrominance-only Video. Analog output of chrominance D/A

P-P

converter, nominally 1.35 volt peak-to-peak into a 37.5Ω load.

internal voltage reference output, nominally 1.235 V.

decoupling capacitor.

current-setting resistor for D/A converters. The resistor (392Ω)
is connected between R
are inversely proportional to the value of R

(LOW) selector.

, is set to HIGH impedance and ignored. When CS is

7-0

. One additional falling edge of CS is needed to move input

. When R/W is HIGH and CS is LOW, it can read the

REF

and A

. Output video levels

GND

REF

.

7-0

.

A

GND

32, 34, 36, 384, 6, 9,

100

0.0 V Analog Ground.

9

PRODUCT SPECIFICATION TMC22091/TMC22191

Pin Descriptions (continued)

Pin Number

84-Lead

Pin Name
Test

TEST 28, 29,

NC N/A 1, 3, 7,

PLCC

48-51

100-Lead

MQFP

22-25,

96-97

11-12,
28-30,
52-55,

69, 78-79

Value Pin Function Description

0.0 V Factory testing (TMC22091 only). Reserved for factory
testing. These pins have no effect on the operation but do
function as JTAG registers. They should be grounded directly
or pulled down to ground with 1kΩ or smaller resistors.

No Connect

Control Registers

The TMC22x91 is initialized and controlled by a set of regis­ters. The registers are organized into 13 categories:

1. Global Control

2. Format Control

3. Interface Control

4. Test Control

5. Key Control

6. Misc. Control

7. Standards Control

8. Layering Control (TMC22191)

9. Key Value

10. Timing

11. Subcarrier

12. Test I/O

13. Mask Register
An external controller loads the Control Registers through a

standard interface port. It also loads the CLUT and reads its

contents or those of the Control Registers. The port is
governed by pins CS, R/W, and A

The Address Register for the CLUT and the Control Register
pointer automatically increment to allow successive writes to
sequential addresses. In the CLUT, the Address Register has
two additional bits which increment in modulo-three to
sequentially access the red, green, and blue portions. All
three colors must be written when any CLUT address is
changed.

The control register autoincrement follows the sequence
indicated in the Control Register Map. When it reaches
address 40, it stops incrementing, allowing multiple reads or
writes of test data from/to the TESTDAT register. To exit the
test mode, reset the Control Register pointer by setting A
D

, and R/W LOW and then bring CS LOW. Address 1F is

7-0

a read-only status register. It is addressed by the autoincre­ment sequencer. Any data may be written into this port at
that time but it will not be stored. When address 50 is
accessed, no autoincrement takes place, allowing multiple
writes to the Mask Register.

1-0

.

1-0

,

10

PRODUCT SPECIFICATION TMC22091/TMC22191

Table 2. Microprocessor Port Control

A

1-0

00 0 Write D

00 1 Read Control Register pointer

01 0 Write D

01 1 Read CLUT Address Pointer on

10 0 Write D

10 1 Read addressed Control

11 0 Write D

11 1 Read addressed CLUT location

R/W Action

pointer

on D

7-0

Pointer

D

7-0

Register

Register on D

location

on D

7-0

into Control Register

7-0

into CLUT Address

7-0

to addressed Control

7-0

7-0

to addressed CLUT

7-0

Table 3. Control Register Map

Reg Bit Name Function
Global Control Register

00 7-5 Reserved
00 4 SRESET Software reset
00 3 PAL Standard select, NTSC

or PAL
00 2 LUMDIS Luminance input disable
00 1 CHRDIS Chrominance input

disable
00 0 HRESET Software reset disable

Format Control Register

01 7 Reserved
01 6 LCREN Layering Control

Register enable

(TMC22191)
01 5 RAMPEN Modulated ramp test
01 4 CB Color bar test
01 3-2 FORMAT PD

select
01 1-0 INMODE PD

select

Interface Control Register

02 7 VITSEN VITS lines enable
02 6 SHCY Short-cycle test mode
02 5-4 TBASE Time-base source select
02 3 SOUT Sync output mode select

input format

23-0

input mode

23-0

Table 3. Control Register Map (continued)

Reg Bit Name Function

02 2 FBDIS Frame buffer signals

disable

02 1 PDCDIR PDC master, slave

select

02 0 FLDLK Field lock select

Test Control Register

03 7 Reserved
03 6 LIMEN Luminance limiter

enable
03 5 TESTEN Test enable
03 4 HOLDEN MSBs/LSBs hold select
03 3 TSTMSB LSBs, MSBs in/out

select
03 2 LUMTST LUMA channel test
03 1 8FSUBR 8-field subcarrier reset

enable
03 0 CHRTST CHROMA channel test

Key Control Register

04 7 Reserved
04 6 HKEN Hardware key enable
04 5 BUKEN Burst key enable
04 4 SKEXT Data key operation

select
04 3 DKDIS Green/red/Y data key

disable
04 2 EKDIS Blue/green/C

disable
04 1 FKDIS Red/blue/CR data key

disable
04 0 SKEN Data key enable

Layering Control Register (TMC22191)

04 7 LAYMODE MSB of Layer

Assignments select
04 6 HKEN Hardware key enable
04 5 BUKEN Burst key enable
04 4 SKEXT Data key operation

select
04 3-1 LAYMODE LSBs of Layer

Assignments select
04 0 SKEN Data key enable

Key Value Registers

05 7-0 DKEY Green/red/Y data key

value
06 7-0 EKEY Blue/green/CB data key

value

data key

B

11

TMC22091/TMC22191 PRODUCT SPECIFICATION

Table 3. Control Register Map (continued)

Reg Bit Name Function

07 7-0 FKEY Red/blue/CR data key

value

08-0D Reserved

Misc. Control Register

0E 7 EFEN Register 0E and 0F

enable

0E 6 COMPD/A COMPOSITE D/A

disable

0E 5 SVIDD/A LUMA/CHROMA D/A

disable

0E 4 FKREN Luminance processing

enabled
0E 3 RATIO Luminance ratio select
0E 2 TFLK Luminance pass

threshold select
0E 1 T512 EH/SL offset select
0E 0 CB100 NTSC/PAL Color Bars

Standards Control Register

0F 7 EFEN Same as Reg 0E bit 7

but read-only

0F 6 SIX25 625/525 line per frame

select

0F 5 PALID Phase alternate line

select

0F 4 SETUP 7.5 IRE Pedestal Enable
0F 3-2 YGAIN Luminance gain settings
0F 1-0 CGAIN Chrominance gain

settings

Timing Registers

10 7-0 SY Horizontal sync tip

length

11 7-0 BR Breezeway length
12 7-0 BU Burst length
13 7-0 CBP Color back porch length
14 7-0 XBP Extended color back

porch 8 LSB

15 7-0 VA Active video 8 LSB
16 7-0 VC Active video start 8 LSB
17 7-0 VB Active video end 8 LSB
18 7-6 XBP Extended color back

porch 2 MSB

18 5-4 VA Active video 2 MSB
18 3-2 VC Active video start 2 MSB
18 1-0 VB Active video end 2 MSB

Table 3. Control Register Map (continued)

Reg Bit Name Function

19 7-0 FP Front porch length
1A 7-0 EL Equalization pulse LOW

length

1B 7-0 EH Equalization pulse HIGH

length

1C 7-0 SL Vertical sync LOW

length

1D 7-0 SH Vertical sync HIGH

length
1E 7-0 CBL Color bar length
1F 7-5 FIELD Field identification
1F 4-0 LTYPE Line type identification

Subcarrier Registers

20 7-0 FREQL Subcarrier frequency 4th

byte (LSBs)

21 7-0 FREQ3 Subcarrier frequency 3rd

byte

22 7-0 FREQ2 Subcarrier frequency

2nd byte

23 7-0 FREQM Subcarrier frequency 1st

byte (MSBs)

24 7-0 SYSPHL Video phase offset LSBs
25 7-0 SYSPHM Video phase offset

MSBs

26 7-0 BURPHL Burst phase offset LSBs
27 7-0 BURPHM Burst phase offset MSBs

28-3F Reserved

Test I/O Register

40 7-0 TESTDAT Test data input/output

Mask Register

50 7-0 MASK Mask register

Y-Component Register

60 7-0 Y Y-component input/

output

Notes:

1. Functions are listed in the order used for reading and
writing.

2. For each register listed above, all bits not listed are
reserved and should be set to zero to ensure proper
operation.

3. The meaning of Register 04 (Key Control Register/Layer­ing Control Register) is determined by Format Control
Register bit 6 (TMC22191).

12

PRODUCT SPECIFICATION TMC22091/TMC22191

Control Register Definitions

Global Control Register (00)

7 6 5 4 3 2 1 0

Reserved SRESET PAL LUMDIS CHRDIS HRESET

Reg Bit Name Function

00 7-5 Reserved.
00 4 SRESET Software reset. When LOW, resets and holds internal state machines and

disables outputs. When HIGH (normal), starts and runs state machines and
enables outputs.

00 3 PAL Video standard select. When LOW, the NTSC standard is generated with 7.5

IRE pedestal. When HIGH, PAL standard video is generated. This bit is ignored
if Register 0E bit 7 is HIGH, enabling the 0E and 0F registers.

00 2 LUMDIS Luminance input disable. When LOW (normal), luminance (Y) data from

external frame buffer is enabled. When HIGH, luminance (Y) data into the
TMC22x91 is forced to 0 IRE but sync pulses continue from the LUMA output.

00 1 CHRDIS Chrominance input disable. When LOW (normal), burst and frame buffer data

into the TMC22x91 are enabled. when HIGH, burst and frame buffer data are
suppressed, enabling monochrome operation.

00 0 HRESET Software reset enable. SRESET

LOW. State machines are reset and held. When HRESET is LOW, RESET may
be taken HIGH at any time. The TMC22x91 is enabled and a new frame is
begun with line 1, field 1 on the next PXCK after SRESET is set HIGH. The D/A
converters are powered down while RESET is LOW. When HRESET is HIGH,
a new frame is begun with line 1, field 1 on the next PXCK after RESET is taken
HIGH. SRESET is ignored. The D/A converters remain active during the reset
sequence.

is forced LOW when the RESET pin is taken

13

TMC22091/TMC22191 PRODUCT SPECIFICATION

Control Register Definitions (continued)

Format Control Register (01)

7 6 5 4 3 2 1 0

Reserved LCREN RAMPEN CB FORMAT INMODE

Reg Bit Name Function

01 7 Reserved.
01 6 LCREN (TMC22191) Layering Control Register enable. When LOW, the Layering

Control Register is not available and Key Control Register functions are
enabled. In this mode, the TMC22191 functions like the TMC22091. When
HIGH, the Layering Control Register takes the place of the Key Control
Register and enables the layering functions. Data loaded into the Key or
Layering Control Registers will remain but have a different meaning if this bit is
changed.

01 5 RAMPEN Modulated ramp test. When LOW (normal), the TMC22x91 encodes and

outputs video corresponding to input data. When RAMPEN and CB
HIGH, an internally generated 40 IRE modulated ramp is produced, preempting
input data.

01 4 CB Color bar test. When HIGH (normal), the TMC22x91 encodes and outputs

video corresponding to input data. When CB, RAMPEN, and Format Control
Register bit 0 are LOW, internally generated color bars are produced,
preempting input data.

01 3-2 FORMAT PD

01 1-0 INMODE PD

When bits 3 and 2 are:
0 0 the CLUT output is interpreted as RGB and is converted to YCBCR.

0 1 is reserved. Bits 3 and 2 must be 00 or 10 when the Layering Control
Register is enabled (TMC22191).
1 0 the CLUT output is interpreted as GBR, and is converted to YCBCR.
1 1 the CLUT output is interpreted as YCBCR.

422, 15-bit, or 8-bit input modes.

input format select. Two bits select RGB, GBR, or YCBCR input data.

23-0

input mode select. These two bits set up the TMC22x91 for either 444,

23-0

are both

14

0 0 24-bit/pixel GBR, RGB, or YCBCR444 data enters from PD
0 1 YCBCR422 data enters from PD
1 0 15-bit/pixel GBR or RGB data from PD
1 1 8-bit/pixel color indexed data enters from PD

Bits 1 and 0 must be 00, 01, or 11 when the Layering Control Register is
enabled (TMC22191).

; CR and CB alternate from PD

23-8

14-0

7-0

.

23-0

15-8

PRODUCT SPECIFICATION TMC22091/TMC22191

Control Register Definitions (continued)

Interface Control Register (02)

7 6 5 4 3 2 1 0

VITSEN SHCY TBASE SOUT FBDIS PDCDIR FLDLK

Reg Bit Name Function

02 7 VITSEN VITS lines enable. When LOW, all UBB lines in the vertical interval are black

burst regardless of input data. When HIGH, all UBB lines in the vertical interval
become UVV active video and are dependent upon input data.

02 6 SHCY Short-cycle test mode. When LOW, normal operation is enabled. when HIGH,

EH (equalization pulse HIGH length) and SL (vertical sync LOW length) are
shortened by 256.

02 5-4 TBASE Time-base source select. These two bits set up the TMC22x91 for either

genlock or frame buffer control of timing. When bits 5 and 4 are:
0 0 the encoder counts out its own time-base from input clock PXCK.

0 1 the encoder locks to synchronizing signals from external genlock.
1 0 the encoder locks to synchronizing signals from frame buffer controller.

02 3 SOUT Sync output mode select. When LOW, VHSYNC

horizontal and vertical sync pulses. When HIGH, composite sync (H and V) is
output on VVSYNC while horizontal sync is output on VHSYNC.

02 2 FBDIS Frame buffer signals enable. When LOW, VVSYNC and VHSYNC outputs to

frame buffer are enabled. When HIGH, VVSYNC and VHSYNC outputs to
frame buffer are disabled.

02 1 PDCDIR PDC master/slave select. When LOW, PDC is an output where the encoder is

requesting data from the frame buffer. When HIGH, PDC is an input, and
directs the encoder to accept data from the frame buffer.

02 0 FLDLK Field lock select. When LOW, (in Slave mode) the encoder locks to each new

field. When HIGH, the encoder locks to field 1 only.

and VVSYNC output separate

15

TMC22091/TMC22191 PRODUCT SPECIFICATION

Control Register Definitions (continued)

Test Control Register (03)

7 6 5 4 3 2 1 0

Reserved LIMEN TESTEN HOLDEN TSTMSB LUMTST 8FSUBR CHRTST

Reg Bit Name Function

03 7 Reserved.
03 6 LIMEN Luminance limiter enable. When LOW, all luminance values are passed to

modulator. when HIGH, luminance values are limited to 101 IRE.

03 5 TESTEN Test enable. When LOW, normal operation is enabled. When HIGH,

TESTDAT
D/A converters (WRITE) for test.

03 4 HOLDEN MSBs/LSBs hold select. When LOW, alternates MSBs and LSBs in test, at

PXCK rate. When HIGH, reads/writes only MSBS or LSBS in test (per
TSTMSB, bit 3)

03 3 TSTMSB LSBS,MSBS hold select. When LOW, connects 2 LSBs to TESTDAT

for testing when TESTEN is HIGH. When HIGH, connects 8 MSBs to
TESTDAT

03 2 LUMTST LUMA channel test. When LOW (normal), the luminance D/A converter is

driven from luminance channel. When HIGH, the luminance D/A converter is
driven from TESTDAT for testing when TESTEN is HIGH.

03 1 8FSUBR 8-field subcarrier reset enable. When LOW, the internal subcarrier generator is

03 0 CHRTST CHROMA channel test. When LOW (normal), the chrominance D/A converter is

reset with frequency and phase data from FREQ, SYSPH, and BURPH
registers every eight fields. When HIGH, the internal subcarrier generator free­runs on the basis of frequency and phase data from the last time it was reset.
When RESET goes LOW, the subcarrier frequency and phase will be reset
from FREQ, SYSPH, and BURPH after field 8.

driven from chrominance channel. When HIGH, the chrominance D/A converter
is driven from TESTDAT when TESTEN is HIGH.

(Register 40) is connected to the composite output (READ) and

7-0

1-0

for testing when TESTEN is HIGH.

7-0

16

PRODUCT SPECIFICATION TMC22091/TMC22191

Control Register Definitions (continued)

Key Control Register (04)

7 6 5 4 3 2 1 0

Reserved HKEN BUKEN SKEXT DKDIS EKDIS FKDIS SKEN

Reg Bit Name Function

04 7 Reserved.
04 6 HKEN Hardware key enable. When LOW, the KEY input pin ignored. When HIGH, the

KEY input pin is enabled.

04 5 BUKEN Burst key enable. When LOW, output video burst is generated on TMC22x91.

When HIGH, output burst is taken from genlock input data.

04 4 SKEXT Data key operation select. When LOW, data keying is allowed only during

active video. When HIGH, keying is allowed during active video and blanking.

04 3 DKDIS Green/red/Y data key disable. When LOW, green/red/Y input data is enabled

for data keying. When HIGH, green/red/Y input data is ignored for data keying.
This function is enabled when Layering Control Register is enabled
(TMC22191).

04 2 EKDIS Blue/green/C

enabled for data keying. When HIGH, Blue/green/CB input data is ignored for
data keying. This function is enabled when Layering Control Register is
enabled (TMC22191).

04 1 FKDIS Red/blue/CR data key disable. When LOW, red/blue/CR input data is enabled

for data keying. When HIGH, red/blue/CR input data is ignored for data keying.
This function is enabled when Layering Control Register is enabled
(TMC22191).

04 0 SKEN Data key enable. When LOW, data keying is disabled. When HIGH, data keying

is enabled.

data key disable. When LOW, Blue/green/CB input data is

B

17

TMC22091/TMC22191 PRODUCT SPECIFICATION

Control Register Definitions (continued)

Layering Control Register (04) (TMC22191)

7 6 5 4 3 2 1 0

LAYMODE HKEN BUKEN SKEXT LAYMODE SKEN

Reg Bit Name Function

04 7 LAYMODE MSB of Layer Assignments select.
04 6 HKEN Hardware key enable. When LOW, the KEY input pin ignored. When HIGH, the

KEY input pin is enabled.

04 5 BUKEN Burst key enable. When LOW, output video burst is generated on TMC22191.

When HIGH, output burst is taken from genlock input data.

04 4 SKEXT Data key operation select. When LOW, data keying is allowed only during

active video. When HIGH, data keying is allowed during active video and

blanking.
04 3-1 LAYMODE Three LSBs of Layer Assignments select.
04 0 SKEN Data key enable. When LOW, data keying is disabled. When HIGH, data keying

is enabled.

Key Value Registers (05-07)

Reg Bit Name Function

05 7-0 DKEY Green/red/Y data key value. Eight bits hold the match value which triggers

keying on red/Y.
06 7-0 EKEY Blue/green/U data key value. Eight bits hold the match value which triggers

keying on green/U.
07 7-0 FKEY Red/blue/V key value. Eight bits hold the match value which triggers keying on

blue/V.

18