Fairchild Semiconductor TMB2193MS100 Datasheet

TMB2193MS100

Demonstration Board for the TMC2193

www.fairchildsemi.com

Features

• 10-bit or 20-bit Parallel YCbCr input

• 24-bit RGB input

• D1, Genlock and Master mode operation

• Composite, S-video and component analog outputs

• Digital Composite output

• Fairchild demo board compatibility

Applications

• Evaluation of TMC2193 DENC

• Evaluation of TMC2072 Genlock interface

• Output for TMC2068P7C Decoder demo board

• System Breadboarding

Block Diagram

RBUS Connector

+5V 0V -5V

96 Way Edge Connector (female)

Digital Inputs:

10 bit D1 24 bit RGB 20 bit YCbCr PXCK

Digital Outputs:

HSYNC VSYNC MPXCK

32

1

FPGA

MCU

TMC2193

Description

The TMB2193MS100 demonstration board provides a ﬂexible base for evaluating the performance of the TMC2193 Digital Video Encoder (DENC). The demonstration board can be driven by either a D1 or Genlock signal, or it can supply the synchronization signals needed to drive a framestore or any MPEG Decoder. Both YCbCr, in either 4:2:2, D1, or 4:4:4 formats, and RGB inputs are supported. The board provides high quality analog composite video, analog S-video, analog component video and digital composite video outputs.

Analog Outputs:

Composite S-Video RGB YPbPr

TMC2072

Analog

LPF

65-B2193-01

Sync

Digital Outputs (Optional):

10 bit DCVBS HSYNC VSYNC PXCK

Preliminary Information

Rev. 0.9.0

PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.

TMB2193MS100 PRODUCT SPECIFICATION

Functional Description

The TMB2193MS100 is designed to demonstrate the performance of the TMC2193 Digital Video Encoder (DENC). For a complete description of the TMC2193, please refer to the TMC2193 data sheet. The TMB2193MS100 is compatible with other Fairchild Demo boards. Typical conﬁgurations are the TMC2067P7C, the TMC2068P7C, and the TMB2193MS100 or the TMB0001MS100 and the TMB2193MS100. The ﬁrst conﬁguration requires an analog composite or S-video input and supplies a re-encoded analog composite or S-video output. The later requires a parallel D1 input and supplies an encoded analog composite or S-video output.

The TMC2193 can be operated in D1, Genlock or Master mode. In the D1 mode the synchronization is derived from the TRS codes embedded in the D1 data stream. The TMB2193MS100 has the TMC2072 Genlock front end, which supplies the HSYNC, VSYNC and subcarrier information to the TMC2193 for the Genlock operation of the encoder. In Master mode the synchronization is driven by

Table 1. Default Control Register Maps

P3 P2 P1 P0 Format Mode Source Output Mode

0 0 0 0 NTSC MASTER Mod. Ramp Composite, S-Video 0 0 0 1 NTSC MASTER 75% CB Composite, YPBPR 0 0 1 0 NTSC MASTER 100% CB Composite, RGB 0 0 1 1 NTSC D1 D1 Composite, YPBPR 0 1 0 0 NTSC D1 D1 Composite, RGB 0 1 0 1 NTSC D1 D1 DCVBS 0 1 1 0 NTSC Genlock 601 Composite, YPBPR 0 1 1 1 NTSC Genlock 601 Composite, RGB 1 0 0 0 PAL MASTER Mod. Ramp Composite, S-Video 1 0 0 1 PAL MASTER 75% CB Composite, YPBPR 1 0 1 0 PAL MASTER 100% CB Composite, RGB

Preliminary Information

1 0 1 1 PAL D1 D1 Composite, YPBPR 1 1 0 0 PAL D1 D1 Composite, RGB 1 1 0 1 PAL D1 D1 DCVBS 1 1 1 0 PAL Genlock 601 Composite, YPBPR 1 1 1 1 PAL Genlock 601 Composite, RGB

the TMC2193, supplying the line (HSYNC (VSYNC or BnT) synchronization signals. With the TMC2193 running in Master mode the TMB2193MS100 demo board interfaces directly to either a MPEG decoder or a video framestore with no additional glue logic.

The TMB2193MS100 has an onboard microcontroller (MCU) to program the TMC2193, the TMC2072, and to conﬁgure the FPGA. All the default register maps are held within the MCU. Table 1 provides a description of each of the default register maps. A control register map is written to the TMC2193, the TMC2072, and to Port 2 of the MCU each time the MRST\ button is pressed. The MCU determines which map to load from the PROG[3-0] (Px) dip switches. The TMC2193, 2072 and the MCU can also be driven by the Raydemo software. The interface is provided by the RBUS connector on the TMB2193MS100 and the TMC2070P7C R-Bus interface board. With this setup the user can conﬁgure the TMC2193, the TMC2072 and the MCU with any IBM compatible PC.

) and ﬁeld

2

PRODUCT SPECIFICATION TMB2193MS100

CPLD Description

The Altera 10K20 CLPD functions as the central matrix for routing the buses to the TMC2193. Eight (8) control pins are connected from port 2 of the MCU to the CLPD. These pins are used to conﬁgure the CPLD and are broken up into 2 buses: FPGA control1 is on pins P2[7:4] and FPGA control2 is on pins P2[3:0]. The 10K20 default conﬁguration routes the 3 buses from the input edge connector and the bus from the framestore header to the pixel data (PD[23:0]) port of the TMC2193. This enables the various input formats of the TMC2193 to be supported. In addition, the PD input can be delayed in respect to the HSIN and VSIN for proper data alignment. Table 2 describes the function of the pixel data formatting.

Table 2. FPGA Control 1

FGPA Control1 bit# Function Description

3-2 PDMODE PD Input

00 10-bit format, A bus 01 20-bit format, C and

B buses

10 24-bit format, C, A,

and B buses

11 10-bit format, A bus

delayed

1-0 PDDEL PD delay

00 0 pxck’s of delay 01 1 pxck’s of delay 10 2 pxck’s of delay 11 3 pxck’s of delay

The FPGA Control 2 bus selects which subcarrier reference signal to be used; either the GRS from the TMC2072 or the xRS signal from bus B of the input edge connector. FGPA Control 2 also selects which set of synchronization signals are to used; either the IXHSYNC and IXVSYNC from the input edge connector or the TMC2072 GHSYNC and GVSYNC.

Table 3. FPGA Control 2

FGPA Control2 bit# Function Description

3-2 No Modes 1 REFSEL CVBS Input

0 B[5:2] bus 1 GENLOCK

0 SYNCSEL HSIN, VSIN Input

0 IXH and IXV 1 GH and GV

FPGA Controls 1 and 2 can be accessed by the Raydemo software. The dialog box exists in the MCU icon of the TMB2193MS100 window. The functions of these controls are purposely left generic to allow for the reconﬁguration of the CPLD.

The 10K20 utilization is approximately 20% of the available logic cells. This allows for additional functions to be implemented in the 10K20 such as notch ﬁlters, interpolation ﬁlters for 4:2:2 to 4:4:4 conversion, simple comb ﬁltering and ancillary data insertion. These are just some of the possibilities.

Preliminary Information

Table 4. Switch, Button, and Jumper Description

Button Description

MRST Resets the AT89C55. When the GLOBAL RESET jumper is in place, the reset line on all

boards connected to the TMB2193MS100 are driven by MRST.

Jumpers Description

GLOBAL RESET When GLOBAL RESET is open, only the TMC2193, the TMC2072, the framestore header

and the AT89C55 receive the reset pulse from MRST. When GLOBAL RESET is closed, the reset line on all boards connected to the TMB2193MS100 are driven by MRST.

CASC INT Cascade Programming Enable.

When CASC INT is open, the AT89C55 automatically initializes the devices after reset. When CASC INT is closed, the AT89C55 will wait for a LOW pulse on the PGM_IN pin

before initializing the devices on the TMB2193MS100.

RBUSEN When RBUSEN is open, the RBUS port is disabled.

When RBUSEN is closed, the RBUS port is enabled.

3

TMB2193MS100 PRODUCT SPECIFICATION

Table 4. Switch, Button, and Jumper Description (continued)

Button Description

JP20, JP21, JP22, JP23

Switches Description

E1 Onboard Clock Selection.

E2 Master Clock Selection.

E3 Output Header Clock Selection.

Dip Switches Description

SA1-0 Configures the bits 2 and 1 of the TMC2193 RBUS chip address. When SAx is ON

CAS Configures the bit 2 of the TMC2072 RBUS chip address. When CAS is ON (down),

ERS Configures the bit 1 of the TMC2072 RBUS chip address. When ERS is ON (down),

P3-0 Control Register Programming.

When JPx is open, the output video is a single 75Ohm termination. When JPx is closed, the output video is a double 75Ohm termination.

Selects either the PXCK from the TMC2072 or the onboard TTL clock oscillator.

When Pass is selected the clock source for the entire board is either the TMC2072 PXCK or the TTL clock oscillator. When IXPCK is selected the clock source for the entire board is the PXCK from the input header.

Selects either PXCK or PXCK

(down), ESAx is in a LOW state. When SAx is OFF (up), ESAx is in a HIGH state.

GSA1 is in a LOW state. When CAS is OFF (up), GSA1 is in a HIGH state.

GSA0 is in a LOW state. When ERS is OFF (up), GSA0 is in a HIGH state.

P3-0 selects which control register map to configure the devices with. Refer to Table 1 Default Control Register Maps for a description.

for the output header.

Setup Procedure

Set E1 to MPXCK and E2 to PASS, enable the onboard TTL clock oscillator as the clock source.

1. Set ESA1-0 to ON (down).

2. Set P3-0 to 0h, P3 is ON (down), P2 is ON (down), P1 is ON (down), and P0 is ON (down).

Preliminary Information

3. Plug in power supply connector and apply power. The LED’s corresponding to +5 Volts and -5 Volts should be illuminated.

4. Reset board by pressing the MRST button.

5. Connect a scope probe to TP25 and adjust R39 until the sync to blank amplitude is 286 mV.

6. Connect a scope probe to TP19 and adjust R36 until the sync to blank amplitude is 286 mV.

7. Connect a scope probe to TP21 and adjust R37 until the sync to blank amplitude is 286 mV.

8. Connect a scope probe to TP23 and adjust R38 until the burst amplitude is 286 mV.

Power Supply Requirements

The TMB2193MS100 board requires 1.5 Amps from the +5 Volt power supply and 0.5 Amps from the -5 Volt power supply. Both the +5 Volt and -5 Volt supplies are connected to the input connector to supply the power requirements of any upstream board. The +5 Volt power supply not only drives TTL logic devices but it also provides the po wer and voltage references to the D/A’s in the TMC2193. Therefore, it is recommended that a bench power supply be used with the cable lengths kept to a minimum.

4

PRODUCT SPECIFICATION TMB2193MS100

0.9.0

of

DCVBS[0..9]

HEADEROUT

DCVBS[0..9]

HSOUT

VSOUT

HSOUT

VSOUT

OPXCK

SCL

SDA

RESET

PGM_OUT

HEADEROUT

POWER

{Schematic}

112Thursday, September 04, 1997

65-B2193-02

675MCLK

CKDRIVE

MPXCK

EPXCK

135MCLK

GPXCK

IXPXCK

GPXCK

IXPXCK

FPXCK

OPXCK

CKDRIVE

MPXCK

DCVBS[0..9]

PD[0..23]

TMC2193

PD[0..23]

ECVBS[0..9]

PD[0..23]

A[0..9]

FPGA

B[0..9]

A[0..9]

VSOUT

HSOUT

ECVBS[0..9]

OLENGI[0..5]

VSIN

OLENG[0..5]

ECVBS[0..9]

OLENG[0..5]

A_DEL[0..9]

B[0..9]

C[0..9]

CVBS[0..7]

A_DEL[0..9]

C[0..9]

CVBS[0..7]

675MCLK

HSIN

VSIN

HSIN

EPXCK

HSIN

VSIN

GHSYNC

GVSYNC

675MCLK

IXHSYNC\

GHSYNC

GVSYNC

EPXCK

EMCU[0..3]

IXHSYNC

IXVSYNC

IXVSYNC\

SDA

SCL

EMCU[0..3]

FMCU[0..7]

IXPXCK

FPXCK

IXPXCK

FPXCK

TMC2193

FPGA

FMCU[0..7]

135MCLK

MCU

PGM_OUT

FMCU[0..7]

EMCU[0..3]

GMCU[0..6]

PGM_IN

VSOUT

RESET

FRESET

SDA

SCL

135MCLK

MCU

RESET\

FRESET\

SCL

TOP

Raytheon Electronics - Semiconductor Division

5580 Morehouse Dr.

San Diego, CA 92121

Title

SDA

TMB2193

B

Size Document Number Rev

Preliminary Information

Date: Sheet

GENLOCK

GHSYNC

GVSYNC

CVBS[0..7]

GMCU[0..6]

SCL

GPXCK

SDA

GENLOCK

B[0..9]

A[0..9]

SCL

HEADERIN

C[0..9]

A_DEL[0..9]

SDA

HSOUT

VSOUT PGM_IN

IXVSYNC

IXHSYNC

MPXCK

IXPXCK

RESET

FRESET

PGM_IN

GMCU[0..6]

HEADERIN

Figure 1.

5

TMB2193MS100 PRODUCT SPECIFICATION

VCC

135MCLK

Y1

27MHz

OUT

U10A 74F74

4

2

D

3

CLK

5

MPXCK

E1 SELECT

5

Q

PR

6

Q

CL

1

12

D

11

CLK

PLACE COMPONENTS ON THIS P AGE CLOSE TO THE GENLOCK.

U10B

10

74F74

9

Q

PR

8

Q

CL

13

C3

0.1µF

675MCLK

GPXCK

VCC

C1

0.1µF

IXPXCK

Preliminary Information

GPXCK

VCC

E2 SELECT

IXPXCK PASS

U2A

12

74F14

VCC

C2

0.1µF

U1A

2

A1

4

A2

6

A3

8

A4

1

G

74F240 U1B

11

A1

13

A2

15

A3

17

A4

19

G

74F240

Raytheon Electronics - Semiconductor Division 5580 Morehouse Drive

San Diego, CA 92121 (619) 457-1000

Title

CKDRIVE.SCH

Size Document Number Rev

TMB2193 0.9.0

B

Date: Sheet of

Friday, February 07, 1997

18

Y1 Y2 Y3 Y4

MPXCK

16

EPXCK

14

FPCXK OPXCK

12

9 7 5 3

912

65-B2193-03

MPXCK EPXCK FPXCK OPXCK

Figure 2.

6

PRODUCT SPECIFICATION TMB2193MS100

0.9.0

of

312Thursday, September 04, 1997

TMB2193

B

Size Document Number Rev

Date: Sheet

65-B2193-04

VCC

PD[0..23]

C9

0.1µF

PD19

PD16

PD17

PD15

PD18

PD13

PD14

PD11

PD12

PD6

PD5

PD7

PD4

PD3

PD1

PD2

PD0

C14

C8

0.1µF

C7

0.1µF

C6

0.1µF

C5

0.1µF

C4

0.1µF

C13

0.1µF

C12

0.1µF

C11

0.1µF

C10

0.1µF

PD8

PD9

PD10

PD20

PD21

VSIN

PD22

HSIN

PD23

ECVBS[0..9]

ECVBS0

ECVBS2

ECVBS1

OLENG[0..5]

OLENG0

ECVBS5

ECVBS4

ECVBS3

OLENG1

OLENG2

OLENG3

ECVBS7

ECVBS6

ECVBS8

OLENG5

OLENG4

ECVBS9

FPGA.SCH

Raytheon Electronics - Semiconductor Division

5580 Morehouse Dr.

San Diego, CA 92121

Title

Preliminary Information

VCC

CVBS5

FMCU4

FMCU6

CVBS3

CVBS4

CVBS6

FMCU7

135

136

DATA

OE3nCS

4

6

CVBS7

131

132

133

131

132

133

CONF_DONE

INIT_DONE14nCE

2

107

A_DEL2

nCASC

DCLK

2

130

CVBS2

120

121

106

EPC1PC8

FMCU5

FMCU3

136

137

138

140

137

138

140

MSEL077MSEL176nSTATUS35nCONFIG74DCLK

U11

R5

1K

R4

1K

R3

1K

R2

1K

R1

1K

1

U4

CVBS1

119

120

nCEO3nWS

142

FMCU1

VCC

CVBS0

GVSYNC

117

118

117

118

nRS

nCS

141

144CS143

FMCU2

OLENG2

OLENG3

GHSYNC

100

101

102

101

102

RDYnBSY11CLKUSR7DATA7

A_DEL9

A_DEL5

FMCU0

C19

0.1µF

OLENG1

OLENG0

99

100

116

PD4

PD23

114

PD3

DATA6

PD22

DATA5

113

PD2

PD21

112

PD1

PD17

PD20

PD18

PD19

DATA1

DATA2

DATA3

DATA4

108

109

110

111

PD0

OLENG5

OLENG4

A_DEL0

A_DEL1A3A_DEL8

A_DEL[0..9]

PD15

PD13

PD16

PD12

PD14

DATA0

TDI

TDO4TCLK1TMS34DEDIN54DEDIN56DEDIN

105

A_DEL5

A_DEL4

A_DEL3

A_DEL2A0A_DEL6

PD8

PD9

C6

A_DEL7

PD6

PD7

124

IXHSYNC\

C8

A_DEL9

PD5

VSIN

HSIN

DEDIN

126

125

FPXCK

IXVSYNC\

A[0..9]

ECVBS3

C5

ECVBS7

ECVBS8

ECVBS9

GCLK0

GCLK155DEV_CLRn

DEV_OE

122

128

C7

PD10

PD11

A2A6A7

A1

ECVBS5

ECVBS6

A_DEL8

C3

C4

ECVBS4

ECVBS2

C9

889910101212131318181919202021212222232326262727282829293030313132

17

A_DEL4

A0

A_DEL3

A_DEL0

A_DEL1

A_DEL6

A_DEL7

GHSYNC

A8A4A9

A5

C2

C1

A2

A1

GVSYNC

GHSYNC

GVSYNC

B5

B6A7

B9

A4

B8

B7

A5

A6

IXHSYNC\

B4

A9

A8

IXVSYNC\

B3

B0

B2

32

B1

IXPXCK

333336363737383839394141424243434444464647474848494951515959606062626363646465656767686869697070727273737878797980808181828283838686878788888989909091919292959596969797989899

FPXCK

IXPXCK

FPXCK

EPF10K10TC144

C0

A3

BYTE

BLASTER

12345678910

JP1

HEADER 5X2

675MCLK

B[0..9]

B2

B0

B1

B9

B3

B5B7B6

B4

C0

B8

C[0..9]

C9

C3C2C1

C8

C7C6C5

C4

CVBS0

CVBS[0..7]

CVBS2

CVBS1

CVBS4

CVBS3

CVBS5

CVBS6

CVBS7

FMCU0

FMCU1

FMCU[0..7]

FMCU2

FMCU3

FMCU5

FMCU4

FMCU7

FMCU6

Figure 3.

7

TMB2193MS100 PRODUCT SPECIFICATION

CR1

CVBS[0..7]

GVSYNC

GHSYNC

GPXCK

1.235V

2 1

65-B2193-05

CVBS[0..7]

C28

C27

GENLOCK.SCH

Title

Size Document Number Rev

1

212

Monday, January 20, 1997

TMB2193 0.9.0

B

Date: Sheet of

R11

3.3K

C31

0.1uF

TP4

GPXCK

TP3

GV

TP2

GH

CVBS3

CVBS4

CVBS5

25

CVBS4

CVBS2

CVBS324CVBS6

CVBS6

30

29

VCC

CVBS7

GVSYNC

GHSYNC

32

33

GHSYNC

GVSYNC

H1

H2

1

17

40

70

34

88

INT

LDV

VALID

COMP

GVSYNC

GHSYNC

GPXCK

CVBS0

CVBS1

CVBS2

85

83

99

80

84

NC

0.1µF

NC

NC78NC79NC

23

CVBS021CVBS122CVBS528CVBS7

VREF

57

RT68RB

C33

82

DDS OUT

6.8pF

75

CBYP

C36

C35

C34

77

PFD IN

0.1uF

GPXCK

45

PXCK

L1

35

31

(BURL)

STUFF EITHER

C36 OR CR1

C40

10µH

C39

C38

0.1µF

C37

0.1µF

62

(FID2)37(FID1)36(FID0)

390pF

150pF

NC56NC59NC

Raytheon Electronics - Semiconductor Division

5580 Morehouse Drive

San Diego, CA 92121

(619) 457-1000

H8

H7

GND

H6

H5

PTH

C26

0.1µF

C25

0.1µF

C24

0.1µF

C23

0.1µF

C22

0.1µF

C21

Preliminary Information

VCC

C20

0.1µF

GMCU[0..6]

GCSGMCU1

GRESET\GMCU0

U5

GRW\GMCU3

GA0GMCU2

GSA1GMCU5

GD0GMCU4

GSA0GMCU6

NC

NC10NC

NC11NC

12

13

14

R7

R6

TP1

15

75

VID_IN

J1

BNC

VIN165VIN261VIN358D0

R8

+

C30

+

C29

1

220

22µF/6.3V

RESET

9

7

GRESET\

R10

GD0

R9

75

2

(SA2)

CS (SCL)5EXT PXCK

A0 (SA0)1(SA1)

R/W (SDA)

3

2

4

33

VCC

GSA1

R12

4.75K

R14

R13

86

4.75K

Y2

VCC

CLK IN

PXCK SEL

94

91

93

1

H3

20MCLK

5

OUT

C32

0.1µF

CLK OUT

20MHz

NC19NC

20

NC

NC66NC

NC71NC53NC

76

JP3AJP4AJP5

SDA

GSA0

SDA

AGND

43

TMC22071AKHC(2072KHC)_2

54

A

JP6BJP7BJP8

STUFF: A for TMC2072

B for TMC22071A

SCL

R15

GA0

DGND

B

33

R16

GCS

GRW\

Figure 4.

8