Fairchild Semiconductor SCANPSC110FSC Datasheet
March 1993
Revised August 2000
SCANPSC110F
SCAN Bridge Hierarchical and Multidrop Addressable
JTAG Port (IEEE1149. 1 System Test Support)
Support)
SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test
General Description
The SCANPSC110F Bridge extends the IEEE St d. 1149.1
test bus into a multidrop test bu s env ironme nt. The adva ntage of a hierarchical approa ch over a single serial scan
chain is improved test throughput and the ability to r emove
a board from the system and retain test access to the
remaining modules. Each SCANPSC110F Bridge supports
up to 3 local scan rings which can be accessed individually
or combined serially. Addressing is accomp lished by loading the instruction register with a value matching that of the
Slot inputs. Backplane and in ter-board testing can easily
be accomplished by par king the local TAP Controllers in
one of the stable TAP Controller state s via a Park instru ction. The 32-bit TC K coun ter en ables built in self te st o pe rations to be performed on one port while other scan chains
are simultaneously tested.
Features
■ True IEEE1149.1 hierarchical and multidrop addressable
capability
■ The 6 slot inputs support up to 59 unique addresses, a
Broadcast Address, and 4 Multi-cast Group Addresses
■ 3 IEEE 1149.1- compatible configurable local scan ports
■ Mode Register allows local TAPs to be bypassed,
selected for insertion into the scan chain in dividually, or
serially in groups of two or three
■ 32-bit TCK counter
■ 16-bit LFSR Signature Compactor
■ L4
■ local TAPs can be 3-stated via the OE
alternate test master to take control of the local TAPs
input to allow an
Ordering Code:
Order Number Package Number Package Description
SCANPSC110FSC M28B 28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Devices also availab le in Tape and Reel. Specify by appending the suffix letter “X” to the o rdering code.
Connection Diagram Pin Descriptions
Names
TCK
TMS
TDI
TDO
TRST
S
(0,5)
OE
TCK
TMS
TDI
TDO
Pin
Backplane Test Clock Input
B
Backplane Test Mode Select Input
B
Backplane Test Data Input
B
Backplane Test Data Output
B
Asynchronous Test Reset Input (Active LOW)
Address Select Port
Local Scan Port Output Enable (Active LOW)
Local Port Test Clock Output
L(1–3)
Local Port Test Mode Select Output
L(1–3)
Local Port Test Data Input
L(1–3)
Local Port Test Data Output
L(1–3)
Description
© 2000 Fairchild Semiconductor Corporation DS011570 www.fairchildsemi.com
TABLE 1. Glossary of Terms
LFSR Linear Feedback Shift Register. When enabled, will generate a 16-bit signature of sampled serial test
data.
LSP Local Scan Port. A four signal port that drives a “local” (i.e. non-backplane) scan chain.
(e.g., TCK
, TMSL1, TDOL1, TDIL1)
L1
Local Local is used to describe IEEE Std. 1149.1 compliant scan rings and the SCANPSC110F Bridge Test
SCANPSC110F
Access Port that drives them. The term “local” was adopted from the system test architecture that the
SCANPSC110F Bridge will most commonly be used in; namely, a system test backplane with a
SCANPSC110F Bridge on each card driving up to 3 “local” scan rings per card. (Each card can contain
multiple SCANPSC110Fs, with 3 local scan ports per SCANPSC110F.)
Park/Unpark Park, parked, unpark, and unparked, are used to describe the state of the LSP controller and the state
of the local TAP controllers (the “local TAP controllers” refers to the TAP controllers of the scan components that make up a local scan ring). Park is also used to describe the action of parking a LSP (transitioning into one of the Parked LSP controller states). It is important to understand that when a LSP
controller is in one of the parked states, TMS
TAP controllers in a given state.
is held constant, thereby holding or “parking” the local
L
TAP Test Access Port as defined by IEEE Std. 1149.1
Selected/Unselected Selected and Unselected refers to the state of the SCANPSC110F Bridge Selection Controller. A
selected SCANPSC110F has been properly addressed and is ready to receive Level 2 protocol. Unselected SCANPSC110Fs monitor the system test backplane, but do not accept Level 2 protocol (except
for the GOTOWAIT instruction). The data registers and LSPs of unselected SCANPSC110Fs are not
accessible from the system test master.
Active Scan Chain The Active Scan Chain refers to the scan chain configuration as seen by the test master at a given
moment. When a SCANPSC110F is selected with all of its LSPs parked, the active scan chain is the
current scan bridge register only. When a LSP is unparked, the active scan chain becomes: TDI
current SCANPSC1 10F registe r
for Unparked configurations of the LSP network.
→ the local s ca n r i ng re g ist e r s → a PAD bit → TDO
. Refer to Table 4
B
Level 1 Protocol Level 1 is the protocol used to address a SCANPSC110F.
Level 2 Protocol Level 2 is the protocol that is used once a SCANPSC110F is selected. Level 2 protocol is IEEE Std.
1149.1 compliant when an individual SCANPSC110F is selected.
PAD A one bit register that is placed at the end of each local scan port scan-chain. The PAD bit eliminates
the prop delay that would be added by the SCANPSC110F LSPN logic between TDI
or TDO
by buffering and synchronizing the TDIL inputs to the falling edge of TCKB, thus allowing data
B
to be scanned at higher frequencies without violating set-up and hold times.
and TDO
Ln
LSB Least Significant Bit, the right-most position in a register (bit 0)
MSB Most Significant Bit, the left-most position in a register
→ the
B
L(n+1)
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TABLE 2. Detailed Pin Description Table
Name I/O (Note 1)
TMS
TTL Input w/Pull-Up Resistor 10 BACKPLANE TEST MODE SELECT: Controls sequencing
B
Pin #
(SOIC & LCC)
through the TAP Controller of the SCANPSC110F Bridge. Also
controls sequencing of the TAPs which are on the three (3) local
scan chains.
TDI
TDO
TTL Input w/Pull-Up Resistor 12 BACKPLANE TEST DATA INPUT: All backplane scan data is
B
3-STATEable, 13 BACKPLANE TEST DATA OUTPUT: This output drives test data
B
32 mA/64 mA Drive,
Reduced-Swing,
supplied to the SCANPSC110F through this input pin.
from the SCANPSC110F and the local TAPs, back toward the scan
master controller.
Output
TCK
TTL Schmitt Trigger Input 11 TEST CLOCK INPUT FROM THE BACKPLANE: This is the mas-
B
ter clock signal that controls all scan operations of the
SCANPSC110F and of the three (3) local scan ports.
TRST
TTL Input w/Pull-Up Resistor 9 TEST RESET: An asynchronous reset signal (active LOW) which
initializes the SCANPSC110F logic.
S
OE
(0–5)
TTL Inputs 2, 3, 4, SLOT IDENTIFICATION: The configuration of these six (6) pins is
5, 6, 7
used to identify (assign a unique address to) each SCANPSC110F
on the system backplane.
TTL Input 1 OUTPUT ENABLE for the Local Sca n Ports, acti ve LOW. When
HIGH, this active-LOW control signal 3-STATEs all three local scan
ports on the SCANPSC110F, to enable an alternate resource to
access one or more of the three (3) local scan chains.
TDO
3-STATEable, 15,19, TEST DATA OUTPUTS: Individual output for each of the three (3)
L(1–3)
24 mA/24 mA 24
local scan ports.
Drive Outputs
TDI
TMS
TCK
V
CC
TTL Inputs w/Pull-Up 18, 23, TEST DATA INPUTS: Individual scan data input for each of the
L(1–3)
Resistors 27
3-STATE able, 16, 20, TEST MODE SELECT OUTPUT S: Individual output for each of the
L(1–3)
24 mA/24 mA 25
Drive Outputs
3-STATE able, 17, 22, LOCAL TEST CLOCK OUTPUTS: Individual output for each of
L(1–3)
24 mA/24 mA 26
Drive Output
three (3) local scan ports.
three (3) local scan ports. TMS
(which is assumed to be present on a connected TMS input, per
the IEEE 1149.1 requirement)
the three (3) local scan ports. These are buffered versions of
TCK
.
B
Power Supply Voltage 8, 28 Power supply pins, 5.0V ±10%.
GND Ground potential 14, 21 Power supply pins 0V.
Note 1: All pins are active HIGH unless otherwise note d.
Description
does not provide a pu ll- up re sis tor
L
SCANPSC110F
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Overview of SCANPSC110F Bridge Functions
SCANPSC110F
FIGURE 1. SCANPSC110F Bridge Architecture
SCANPSC110F BRIDGE ARCHITECTURE
Figure 1 shows the basic architecture of the
SCANPSC110F. The device’s major functional blocks are
illustrated here. The TAP Controller, a 16-state state
machine, is the central contro l for the device. Th e instruction register and various test data registers can be scanned
to exercise the various functions of the SCANPSC110F
(these registers behave as defined in IEEE Std. 1149.1).
The SCANPSC110F selection controller pr ovides th e functionality that allows the 1149.1 protocol to be used in a
multi-drop environm ent. It primarily com pares the address
input to the slot identification and enables the
SCANPSC110F for subsequent scan operations.
The Local Scan Port Network (LSPN) contains multiplexing
logic used to select different port configurations. The LSPN
control block contains the Local Scan Port Controllers
(LSPC) for each Local Scan Port (LSP
This control block receives i nput from the SCANPSC 110F
instruction register, mode register, and the TAP controller.
Each local port contain s all four ( 4) bounda ry scan signals
needed to interface with the local TAPs.
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, LSP2, and LSP3).
1
SCANPSC110F BRIDGE STATE MACHINES
The SCANPSC110F is IEEE 1149.1-compatible, in that it
supports all required 1149.1 operations. In additi on, it supports a higher level of prot ocol, (Leve l 1), th at extends the
IEEE 1149.1 Std. to a multi-drop environment.
In multi-drop scan systems, a sca n tester can select individual SCANPSC110Fs for participation in upc oming scan
operations. SCANPSC110F “selection” is accomplished by
simultaneously scanning a d evice address out to multiple
SCANPSC110Fs. Through an on-chip address matching
process, only those SCANPSC110Fs whose staticallyassigned address matches the scanned-out address
become selected to receive further instructions from the
scan tester. SCANPSC110F selection is done using a
“Level-1” protocol, while follow-on instructions are sent to
selected SCANPSC110Fs by using a “Level-2” protocol.
Overview of SCANPSC110F Bridge Functions (Continued)
FIGURE 2. SCANPSC110F Bridge State Machines
The SCANPSC110F contains three distinct but coupled
state-machines (see Figure 2). The first of these is the
TAP-control state-machine, which is used to drive the
SCANPSC110Fs scan ports in conformance with the
1149.1 Standard (see Figure 17 of appendix). The seco nd
is the SCANPSC110F-selection state -machine (Figure 3).
The third state-mach ine actual ly consist s of three identical
but independent sta te-machines (see Figure 4), o ne per
SCANPSC110F local scan port. Each of these scan portselection state-machin es allow s individ ual lo cal ports to be
inserted into and remov ed from th e SCANPSC 110Fs overall scan chain.
The SCANPSC110F selection state-machi ne performs the
address matching which gives the SCANPSC110F its
multi-drop capability. That logic supports singleSCANPSC110F access, multi-cast, and broadcast. The
SCANPSC110F-selection state-machine implements the
chip’s Level-1 protocol.
SCANPSC110F
KEY
+ = OR
& = AND
ADDR = 6-bit address in the Ins t ruc t ion Register
SLOT = Static addr es s in t he SCANPSC110F Selection Controller
FIGURE 3. State Machine for SCANPSC110F Bridge Selection Controller
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Overview of SCANPSC110F Bridge Functions (Continued)
SCANPSC110F
FIGURE 4. Local SCANPSC110F Bridge Port Configuration State Machine
The SCANPSC110F’s scan port-configuration statemachine is used to control the insertion o f local scan ports
into the overall scan chai n, or the isolation of local ports
from the chain. From th e pe rsp ective of a syste m’s (single )
scan controller, each SCANPSC110F presents only one
scan chain to the m ast er. The SCANPSC110F architectur e
allows one or more of th e SCANPSC110F’s local ports to
be included in the active scan chain.
Each local port can be “parked” in one of four stab le stat es
(Parked-TLR, Parked-RTI, Parked-Pause-DR or ParkedPause-IR), either individually or simultaneously with o ther
local ports. Parking a chain remove s that local chain from
the active scan chain. Conver sely, a parked chain can be
“unparked”, causing the corresponding local port to be
inserted into the active scan chain.
As shown in Figure 4, the SCANPSC110F's three scan
port-configuration state-machines allow each of the part's
local ports to occupy a different state at any given time. For
example, some ports m ay be parked, perhaps in differe nt
states, while other ports participate in scan operations. The
state-diagram shows that some state transitions depend on
the current state of the TAP-control state-ma chine. As an
example, a local port which is presently in the Parked-RTI
state does not beco me unpa rked (i.e., enter the Unparked
state) until the SCANPSC110F receives an UNPARK
instruction and the SCANPSC110F's TAP state-machine
enters the Run-Test/Idle state.
Similarly, certain transitions of the scan port-configuratio n
state-machine can force the SCANPSC110F's TAP-control
state-machine into sp ecific states. For example, when a
local port is in the Unparked state a nd the SCA NPSC 110F
receives a PARKRTI instruction, the Local Port controller
enters the Parked-RTI state in which TMS
LOW until the port is later unparked. While TMS
LOW, all devices on that local scan chain remain in thei r
current TAP State (the RTI TAP controller state in this
example).
The SCANPSC110F's scan port-configuration statemachine implemen ts part of the SC ANPSC110F's Level-2
protocol. In additio n, the SCANPSC110F provides a number of Level-2 instructions for functions other than local
scan port configuratio n. These in structions provide a ccess
to and control of various registers within the
SCANPSC110F. This set instructions includes:
BYPASS CNTRSEL
EXTEST LFSRON
SAMPLE/PRELOAD LFSROFF
IDCODE CNTRON
MODESEL CNTROFF
MCGRSEL GOTOWAIT
LFSRSEL
Figure 5 illustrates how the SCANPSC110F's statemachines interact. The SCANPSC110F-selection statemachine enables or d isables operation of th e chip's three
port-selection state-machines. In SCANPSC110Fs which
are selected via Level-1 protocol (either as individual
SCANPSC110Fs or as members of broadcast or multi- cast
groups), Level-2 proto col commands can be used to park
or unpark local scan ports. Note that most transitions of the
port-configuration state-machines are gated by particular
states of the SCANPS C110F's TAP-control state-machine,
as shown in Figures 4, 5.
will be held
Ln
is held
Ln
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Overview of SCANPSC110F Bridge Functions (Continued)
SCANPSC110F
FIGURE 5. Relationship Between SCANPSC110F Bridge State Machines
Following a hardware reset, the TAP controller statemachine is in the Test-Logic-Reset (TLR) state; the
SCANPSC110F-selection state-machine is in the Wait-For-
Address state; and each of the three por t-selection statemachines is in the Parked-TLR stat e. The SCAN PSC110F
is then ready to receive Level-1 protocol, followed by Level2 protocol.
Tester/SCANPSC110F
Bridge Interface
An IEEE 1149.1 system tester sends instructions to a
SCANPSC110F via that SCANPSC110F’s backplane scanport. Following test logic reset, the SCANPSC110F’s selec-
tion state-machine is in the Wait-For-Address state. When
the SCANPSC110F’s TAP controller is sequenced to the
Shift-IR state, data shifted in through the TDI
shifted into the SCANPSC110F’s instruction register. Note
that prior to successful se lectio n o f a S CAN PSC110F, data
is not shifted out of the instruction register and out through
the SCANPSC110F’s TDO
scan operations. Instead, as each new bit enters the
instruction register’s most-significant bit, data shifted out
from the least-significant bit is discarded.
output, as it is duri ng normal
B
input is
B
When the instruc tion register is u pdated with the address
data, the SCANPSC110F’s address-recognition logic co mpares the six least-sign i fican t bits of the instruction reg i ster
with the 6-bit assig ned address which is statically pre sent
on the S
address is compared with the reserved Broadcast and
Multi-cast addresses. If an ad dress match is detecte d, the
SCANPSC110F-selection state-machine ente rs one of the
two selected states. If the scanned address does not match
a valid single-slot address or one of the reserved broadcast/multi-cast addresses, the SCANPSC110F-selection
state-machine enters the Unselected state.
Note that the SLOT inputs sho ul d not be set to a value corresponding to a multi-cast group, or to the broadcast
address. Also note that the single-SCANPSC110F selection process must be performed for all SCANPSC110Fs
which are subsequently to be addressed in multi-cast
mode. This is requi red because each such device’s Multicast Group Register (MC GR) must be prog rammed with a
multi-cast group n umber, and the MCG R is n ot accessibl e
to the test controller until that SCANPSC110F has first
entered the Selected-Single-SCANPSC110F state.
Once a SCANPSC110F has been selected, L evel-2 pro tocol is used to issue commands an d to access the chip’s
various registers.
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inputs. Simultaneously, the scanned-in
(0–5)
Tester/SCANPSC110FBridge Interface (Continued)
Register Set
The SCANPSC110F Bridge includes a number of re gisters
which are used for SC ANPSC110F selection and configuration, scan data manipulation, and scan -support opera-
SCANPSC110F
tions. These registers can be grouped as shown in Table 3.
The specific fields and functio ns of each of these re gisters
are detailed in the section of this document titled “Data
Register Descriptions”.
TABLE 3. Registers
Register Name BSDL Name Description
Instruction Register INSTRUCTION SCANPSC110F addressing and instruction-decode
Boundary-Scan Register BOUNDARY IEEE Std. 1149.1 required register
Bypass Register BYPASS IEEE Std. 1149.1 required register
Device Identification Register IDCODE IEEE Std. 1149.1 optional register
Multi-Cast Group Register MCGR SCANPSC110F-group address assignment
Mode Register MODE SCANPSC110F local-port configuration and control bits
Linear-Feedback Shift Register LFSR SCANPSC110F scan-data compaction (signature gen er ation )
TCK Counter Register CNTR Local-port TCK clock-gating (for BIST)
Note that when any of these registe rs is sele cted for inse rtion into the SCANPSC110F's scan-chain, scan data
enters through t hat r egister's most- sign ificant b it. Similar ly,
data that is shifted out of the register is fed to the scan
input of the next-downstream device in the scan-chain.
IEEE Std. 1149.1 required register
Addressing Scheme
The SCANPSC110F Bridge architectur e extends the fun ctionality of the IEEE 1149.1 Standard by supplementing
that protocol w ith an addressing scheme whic h allows a
test controller to communicate with specific
SCANPSC110Fs within a network of SCANPSC110Fs.
That network can include both m ulti-drop an d hierarchical
connectivity. In effect, the SCANPSC110F architecture
allows a test controller to dynamically select sp ecific portions of such a network for participation in scan operations.
This allows a complex system to be partitioned into smaller
blocks for testing purposes.
The SCANPSC110F provides two levels of test-network
partitioning capability. First, a test controller can select
entire individual SCANPSC110Fs, specific sets of
SCANPSC110Fs (multi-cast groups), or all
SCANPSC110Fs (broadcast). This SCANPSC110F-selection process is supported by a “Level-1” communication
protocol. Second, within each selected SCANPSC110F, a
test controller can select one or more of the chip 's three
local scan-ports. That is, individual local ports can be
selected for inclusion in the (single) scan-chain which a
SCANPSC110F presents to t he te s t co nt r oll e r. This mechanism allows a controller to select specific terminal scanchains within the over all scan network. The por t-selection
process is supported by a “Level-2” protocol.
Hierarchical Test Support
Multiple SCANPSC110F Bridges can be used to assemble
a hierarchical boundary- scan tree. In su ch a configurat ion,
the system tester can co nfigure the local por ts of a set of
SCANPSC110Fs so as to connect a specific set of local
scan-chains to the active sca n chain. Using this cap ability,
the tester can selectively communicate with specific portions of a target system.
The tester's scan port is conn ected to the backp lane scan
port of a “root” layer of SCANPSC110Fs, each of which can
be selected using multi-drop addressing. A second tier of
SCANPSC110Fs can be connected to th is root layer, by
connecting a local port (LSP) of a root-layer
SCANPSC110F to the backplane port of a second-tier
SCANPSC110F. This process can be continued to construct a multi-level scan hierarchy.
SCANPSC110F local ports which are not cascaded into
higher-level SCAN PSC110Fs can be thou ght of a s the te rminal “leaves” of a scan “tree”. The test ma ster can select
one or more target l eaves by selecti ng a nd conf iguring the
local ports of an appropriate set of SCANPSC110Fs in the
test tree.
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