Fairchild Semiconductor SCANPSC100FSC, SCANPSC100FSCX Datasheet
© 2000 Fairchild Semiconductor Corporation DS010968 www.fairchildsemi.com
December 1991
Revised May 2000
SCANPSC100F Embedded Boundary Scan Controller (IEEE 1149.1 Support)
SCANPSC100F
Embedded Boundary Scan Controller
(IEEE 1149.1 Support)
General Description
The SCANPSC100F is designed to interface a generic parallel processor bus to a se rial scan test bus. It is usef ul in
improving scan throughpu t when applying serial vector s to
system test circuitry and redu ces the software overhead
that is associated with applying serial patterns with a parallel processor. The SCANPSC100F operates by serializing
data from the parallel bus for shi fting through the chain of
1149.1 compliant components (i.e., sc an ch ain ). S ca n da ta
returning from the scan chai n is pla ced on t he para llel po rt
to be read by the host processor. Up to two scan chains
can be directly controlled wi th the SCANPSC1 00F via two
independent TMS pins . Scan control is suppli ed with user
specific patterns which m akes the SCANPSC100F prot ocol-independent. Overflow and underflow conditions are
prevented by stop ping the test clock. A 32 -bit counter is
used to program the number of TCK cycles required to
complete a scan operat ion within the b ounda ry scan chain
or to complete a SCANPSC100F Built-In Self Test (BIST)
operation. SCANPSC100F device drivers and 1149.1
embedded test application code are available with Fairchild’s SCAN Ease software tools.
Features
■ Compatible with IEEE Std. 1149.1 (JTAG) Test Access
Port and Boundary Scan Architecture
■ Supported by Fairchi ld’s SCAN Ease (Embed ded Application Software Enabler) Software
■ Uses generic, asynchronous pr ocessor interface; compatible with a wide range of processors and PCLK frequencies
■ Directly supports up to two 1149.1 scan chains
■ 16-bit Serial Signature Compaction (SSC) at the Test
Data In (TDI) port
■ Automatically produce s pseudo-random patte rns at the
Test Data Out (TDO) port
■ Fabricated on FACT
1.5 µm CMOS process
■ Supports 1149.1 test clock (TCK) frequencies up to
25 MHz
■ TTL-compatible inputs; full-swing CMOS outputs with
24 mA source/sink capability
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Connection Diagram
FACT is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Numb er Package Description
SCANPSC100FSC M28B 28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
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SCANPSC100F
Pin Descriptions
Pin Name Description
RST
(Input) The Reset pin is an asynchronous input that, when LOW, initializes the SCANPSC100. Mode bits,
Shifter/Buffer and CNT32 control logic, TCK Control, and the PPI are all initialized to defined states.
RST
has hysteresis for improved noise immunity.
SCK (Input) The System Clock drives all internal timing. The test clock, TCK, is a gated and buffered version of SCK.
SCK has hysteresis for improved immunity.
OE
(Input) Output Enable 3-STATEs all SSI outputs when HIGH. A 20 kΩ pull-up resistor is connected to
automatically 3-STATE these outputs when this signal is floating.
CE
(Input) Chip Enable, when LOW, enables the PPI for byte transfers. D(7:0) and RDY are 3-STATEd if CE is HIGH.
CE
has hysteresis for improved noise immunity.
R/W
(Input) Read/Write defines a PPI cycle—Read when HIGH, Write when LOW.
R/W
has hysteresis for improved noise immunity.
STB (Input) Strobe is used for timing all PPI byte transfers. D(7:0) are 3-STATEd when STB is HIGH. All other PPI
inputs must meet specified setup and hold times with respect to this signal. STB has hysteresis for noise
improved immunity.
A(2:0) (Input) The Address pins are used to select the register to be written to or read from.
D(7:0) (I/O) Bidirectional pins used to transfer parallel data to and from the SCANPSC100.
INT (Output) Interrupt is used to trigger a host interrupt for any of the defined interrupt events. INT is active HIGH.
RDY
(3-STATE Output)
Ready is used to synchronize asynchronous byte transfers between the host and the SCANPSC100.
When LOW, RDY signals that the addressed register is ready to be accessed RDY is enabled when
CE
is LOW
TDO
(3-STATE Output)
Test Data Out is the serial scan output from the SCANPSC100. TDO is enabled when OE
is LOW.
TMS(1:0)
(3-STATE Output)
The Test Mode Select pins are serial outputs used to supply control logic to the UUT.
TMS(1:0) are enabled when OE
is LOW.
TCK
(3-STATE Output)
The Test Clock output is a buffered version of SCK for distribution in the UUT.
TCK Control logic starts and stops TCK to prevent overflow and underflow conditions.
TCK is enabled when OE
is LOW.
TDI (Input) Test Data In is the serial scan input to the SCANPSC100. A 20 k
Ω pull-up resistor is connected to force
TDI to a logic 1 when the TDO line from the UUT is floating.
FRZ (Input) The Freeze pin is used to asynchronously generate a user-specific pulse on TCK. If the FRZ Enable Mode
bit is set, TCK will be forced HIGH if FRZ goes HIGH. FRZ has hysteresis for improved noise immunity.
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SCANPSC100F
Chip Architecture
The SCANPSC100 is designed to act together with a parallel bus host as a serial test bus master. Parallel data is written by the host to the SCANPSC1 00, which serializes the
data for application to a serial test bus. S erial data re turning from the target scan chain(s) is placed on the processor
port for parallel read s. Sev eral fea tures a re i ncluded in the
SCANPSC100 which m ake scan test communic atio n mo re
convenient and efficient.
Figure 1 shows the major functional blocks of the
SCANPSC100 design. The Parallel Processor Interface
(PPI) is an asynchronous, 8-bit parallel interface which is
used by the host processor to write and read data. The PPI
generates the nece ssary internal data, address, and control signals to complete internal write and read operations.
The Serial Scan I nterface ( SSI) consis ts of a b ank of do uble-buffered parallel/seri al shift registers (i.e., a 2 x 8 bit
FIFO), or Shifter/Buffers. The double buffering improves
efficiency by allowing parallel writes or reads to/from one of
the two 8-bit FIFOs wit hin the shifter /buffer while the other
FIFO is shifting data to/fr om th e scan chain. Three Shifte r/
Buffers are provided for outgoing serial data a nd one for
incoming serial data. Test Data Out (TDO) is for scanning
out test data while the two Test Mode Select signals
(TMS0/1) are used to provi de user specific control data.
Test Data In (TDI) receives serial data from the scan chain.
A local control bloc k is associa ted with each Shifte r/Buffer
to provide shift and load control as well a s providing fu ll or
empty status. The SSI also provides T est Clock (TCK) Control. TCK is stopped and started depending on the status of
the Shifter/Buffers or the 32-bit Counter. By stopping and
starting TCK, scan operations w ill proceed only when the
enabled Shifter/Buffers are ready to send and/or receive
serial data.
The 32-bit Counter (CNT32) is a count-down binary
counter included to assist in controlling the SSI. The initial
state of CNT32 is load ed from the parallel port with four
consecutive writes to its address. When enabled, CNT32 is
used to program the number of TCK s app li ed by the SSI to
the boundary scan chain(s). The value o f CNT32 can also
be used to generate i nterrupts (i.e. , when CNT32 reaches
terminal count) and to trigger SCANPSC100 features, such
as, Auto TMS High (discussed later within this datasheet).
The Mode and Status Registe rs are used to control and
observe the opera tion of the SSI and CNT32 . Each of the
Shifter/Buffers and CNT32 have an associated mode bit
which enables it for participation in on-going operations.
Status bits can be used for polling operations.
FIGURE 1. SCANPSC100 Block Diagram
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SCANPSC100F
Mode and Status Registers
MODE REGISTER 0 (MODE0)
This register is purely a mo de register. All bits are writab le
and readable. The value 00100000 is placed in this register
upon RST
low or a synchronous reset operation.
• Bit 7: This bit enables the TDO shifter/buffer for shift
operations. If this bit is set, the TDO shifter/
buffer will cause TCK to stop if it is empty.
• Bit 6: This bit enables t he TDI shifter/bu ffer for shif t
operations. If this bit is set, the TDI shifter/
buffer will cause TCK to stop if it is full.
• Bit 5: This bit enables the 32-bit counter. If this bit is
set, the counter will cause TCK to stop if has
not been loaded or if i t has reached term inal
count.
• Bit 4: This bit enables the TMS0 shifter/buffer for
shift operations. If this bit is set, the TMS0
shifter/buffer will cause TCK to stop if it is
empty.
• Bit 3: This bit enables the TMS1 shifter/buffer for
shift operations. If this bit is set, the TMS1
shifter/buffer will cause TCK to stop if it is
empty.
• Bit 2: This bit is reserved and should rema in as a
logic 0 during all 'PSC100 operations.
• Bit 1: If this bit is set, T MS will be forced high wh en
the 32-bit counter is at state (00000001)h.
• Bit 0: T his bit causes TDI to be connecte d directly
back through TDO for Loop-Around operations.
MODE REGISTER 1 (MODE1)
This register is purely a mo de register. All bits are writab le
and readable. The value 00000000 is placed in this register
upon RST
low or a synchronous reset operation.
• Bi t 7: If this bit is set and the TDO shifter/ buffer is
not full (i.e., one or both 8-bit TDO FIFOs are
empty), the INT pin will go HIGH.
• Bit 6: If this bit is set and the TDI shifter/buffer is not
empty (i.e., one or both 8-bit TDI FIF Os are
full), the INT pin will go HIGH.
• Bit 5: If this bit is set, and the 32-bit counter is not
loaded or has reached terminal count, the INT
pin will go HIGH.
• Bit 4: This bit signifies that the TD0 shifter /buffer is
reconfigured as a 32-Bit Pseudo Random Pattern Generator. If set, and MODE0 Bit 7 is set,
the TDO shifter/buffer will stop TCK until a
seed value has been written to al l four of the
8-bit LFSR segments.
• Bit 3: This bit signifies that the TD1 shifter /buffer is
reconfigured as a 16-Bit Serial Signature
Compactor. If set, and MODE0 Bit 6 is set, the
TDI shifter/buffer will cause TCK to stop until
a seed value has been written to the tw o TDI
registers.
• Bit 2: If this bit is set, a high value on FRZ will force
TCK high (see TCK Control Section).
• Bits 1 and 0: These bits are used to control Test LoopBack operations according to the following
table.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TDO TDI CNT32 TMS0 TMS1 Auto TMS High Loop-Around
Enable Enable Enable Enable Enable Reserved Enable Enable
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TDO TDI CNT32 PRPG SSC Freeze Test Test
Interrupt Interrupt Interrupt Enable Enable Pin Loop- Loop-
Enable Enable Enable Enable Back Back
MODE1 MODE1 Function
Bit 1 Bit 0
0 0 Normal Operation
0 1 Loop-Back TDO to TDI
1 0 Loop-Back TMS0 to TDI
1 1 Loop Back TMS1 to TDI
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SCANPSC100F
Mode and Status Registers (Continued)
MODE REGISTER 2 (MODE2)
Write:
Read:
This register cont ains both mod e and status bits. Bits 4 –7
are status bits only. Bit 3 is a status bit d uring rea d operations and a mode bit during writ e operations. Bits 0–2 are
mode bits only. Upon RST
low, or a synchronous reset, the
value placed in MO DE2 is 10111000 (Rea d mode ). Lat che s
used to update status bits 3–7 retain their last state upon
RST
and are in an “unknown” state after power-up. To initialize the latches to a known state, they need to be
updated using the Update Status bit (bit 2) or continuous
update bit (bit 3).
• Bit 7: Set high if the TDO shifter/ buffer is not full,
i.e., one or both 8-bit TDO FI FOs are ready to
be written to.
• Bit 6: Set hig h if the TDI shifter/buffer is not empty,
i.e., one or both 8-bit T DI FIFOs are re ady to
be read from.
• Bit 5: Set high if the 32-bit counter has not been
loaded, or has reached terminal count.
• Bi t 4: Set h igh if the TMS0 shifter/buffer is not full,
i.e., one or both 8-bi t TMS0 FIFOs are rea dy
to be written to.
• Bit 3 (Read Cycle):
Set high if the TMS1 shi fter/buffer is not full,
i.e., one or both 8-bi t TMS1 FIFOs are rea dy
to be written to.
• Bit 3 (Write Cycle):
If set, will cause all status bits to be continuously updated.
• Bit 2 (Read Cycle):
Shows the state of the Continuous Update bit
during read operations (Bit 3 during writes).
• Bit 2 (Write Cycle):
If set, will cause a pulse to be issued internally
that will update all status bits. This bit will be
reset upon completion of th e pulse. T he state
of this bit is not readable. It is rese t upo n R ST
low.
• Bit 1: If set, will cause a synchronous reset of all
functions except the parallel interface. The
value of this bit will return to zero when t he
reset operation is complete.
• Bit 0: If set, will cause the 32-bit counter to count for
one SCK cycle (no TCK cycle will be generated). The value of this bit will return to zero
when the single step operation is complete.
PROGRAMMING RESTRICTIONS
Because certain mo de bit s enable shift o perations for certain functions, these mode bits should not be changed
when shift operati ons are in prog ress . The a lignm ent o f al l
registers during shift operations is controlled by a 3-bit
counter in the TCK control block . Enabling or disabling a
function in the middle of a shi ft operation may dis rupt the
logic necessary to keep all shifter/buffers byte-aligned.
For example, if the TDO shi fter/buffer (already loaded) i s
enabled while the 3 -b it cou nte r value is 3, the shifter /bu ffer
will only shift out only five bits of the first byte loaded.
The following bits should not be changed when shift operations are in progress, i.e. , when TCK is enab led (see section on TCK Control).
• MODE0(7:3)
• MODE1(4:3)
• MODE2(0)
Parallel Processor Interface (PPI)
ADDRESS ASSIGNMENT
The following table defines which r egister is selected for
access with the address lines, A(2:0).
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bi t 2 Bit 1 Bit 0
Not Not Not Not Continuous Update Single
Used Used Used Used Update Status Reset Step
CNT32
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TDO TDI CNT32 TMS0 TMS1 Continuous Single
Status Status Status Status Status Update Reset Step
CNT32
A2 A1 A0 R/W Function
0 0 0 0 TDO Shifter/Buffer
0 0 0 1 Counter Register 1
0 0 1 0 TDI Shifter/Buffer
0 0 1 1 TDI Shifter/Buffer
0 1 0 0 TMS0 Shifter/Buffer
0 1 0 1 Counter Register 2
0 1 1 0 TMS1 Shifter/Buffer
0 1 1 1 Counter Register 3
1 0 0 0 32-Bit Counter
1 0 0 1 Counter Register 0
1010MODE0
1011MODE0
1100MODE1
1101MODE1
1110MODE2
1111MODE2
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SCANPSC100F
Parallel Processor Interface (PPI) (Continued)
TIMING WAVEFORMS
FIGURE 2. Write Cycle
FIGURE 3. Read Cycle
Note 1: Valid data is provided on the RDY line a t
PD1
after R/W is asserted LOW or a t
PD2
after valid data is decoded on A2:0. The RDY line will remain HIGH
until the addresse d register is rea dy to participa te in the write o peration. Th is condition only applies w hen writing to a shifter/buffer an d is eliminated (i.e.,
RDY
will go LOW immedia te ly once valid) when using shif t er/buffer status polling (dis c us s ed later in this datasheet ).
Note 2: Valid data will not appear on D7:0 (and RDY
will remain HIGH) until the addressed register is ready to participate in the read operation. When the
addressed regist er bec om es rea dy (i.e. , a byt e is avai lab le to be read), valid data will be p lace d on th e D7:0 b us and the R DY
pin will go LOW allowing t he
bus cycle to continue. This read cycle delay only applies when reading the TDI shifter/buffer and is eliminated when using shifter/buffer status poling.
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SCANPSC100F
Parallel Processor Interface (PPI) (Continued)
TIMING WAVEFORMS (Continued)
FIGURE 4. Consecutive Read/Writes (best case timing)
FIGURE 5. Consecutive Read/Writes (worst case timing)
Note 3: Figures 4, 5: Figure 4 shows the best case bus cycle timing for SCK and STB during consecutive read or write cycles. The rising edge of strobe
occurs a setup time, t
S4
or before the falling edge of SCK. This allows the cycle to be completed within 1.5 clock SCK clock cycles. Figure 5 shows the worst
case bus cycle timing for SCK and STB during consecutive read or write cycles. The rising edge of strobe does not meet the t
S4
requirement betw een ST B
and SCK. Theref ore, the propa gation of the in ternal P SC100 cont rol and r eset signals is delay ed unt il the n ext fall ing edge of SCK. The bus cycle is then
completed 1.5 SCK cycles later creating a total bus cycle time of 2.5 SCK cycles. If worst case timing is considered for bus cycle timing, t
S4
is not a manda-
tory timing specifica tio n.
FIGURE 6. Re ad/Write or Write/Read (best case timing)
FIGURE 7. Read/Write or Write/Read (worst case timing)
Note 4: Figures 6, 7: This diagram shows the timing for a read followed by a write (or write followed by a read). Separate Read and Write data/address
latches and control log ic allow cons ecutive re ad/write or write/read o perations to be overlapp ed (i.e., do n ot need to wait 2 or 3 SCK cycles between bus
cycles). For the best case timing scenario (Figure 6: rising edge of STB to falling edge of SCK greater than tS4), a new bu s c ycle can be performed each SCK
cycle. For the worst timing scenario (Figure 7: rising edge of STB to falling edge of SCK is less than t
S4
), a one SCK cycle delay must be included after each
back to back read/writ e or write/read sequence.
Note 5: Figures 4, 5, 6, 7 assume that the PSC100 register participating in the bus cycle is ready to accept/provide data. For bus cycles involving a PSC100
shifter/buffer(s), the re ady status of a shifter/buffer c an be checke d using the stat us bits in Mod e Register 2 pr ior to the start of the bus cycle. Polling is
required when the RDY
pin is not used to provide a processor “handshake”.
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