Fairchild Semiconductor SCAN18540TSSC, SCAN18540TSSCX Datasheet

© 2000 Fairchild Semiconductor Corporation DS010964 www.fairchildsemi.com

October 1991
Revised May 2000

SCAN18540T Inverting Line Driver with 3-STATE Outputs

SCAN18540T
Inverting Line Driver with 3-STATE Outputs

General Description

The SCAN18540T is a high spee d, low-power line driver
featuring separate data inputs organized into dual 9-bit
bytes with byte-oriente d paired output enable control sig­nals. This device is compliant with IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architecture with the
incorporation of the defined boun dary-scan test logic and
test access port consisting of Test Data Input (TDI), Test
Data Out (TDO), Test Mode Select (TMS), an d Test Clock
(TCK).

Features

■ IEEE 1149.1 (JTAG) compliant

■ Dual output enable signals per byte

■ 3-STATE outputs for bus-oriented applications

■ 9-bit data busses for parity applications

■ Reduced-swing outputs source 32 mA/sink 64 mA

■ Guaranteed to drive 50

Ω transmission line to TTL input

levels of 0.8V and 2.0V

■ TTL compatible inputs

■ 25 mil pitch SSOP (Shrink Small Outline Package)

■ Includes CLAMP and HIGHZ instructions

■ Member of Fairchild’s SCAN pr oducts

Ordering Code:

Connection Diagram Pin Descriptions

Tru th Tables

H = HIGH Voltage Level X = Immaterial
L = LOW Voltage Level Z = High Impedance

Order Number Package Number Package Description

SCAN18540TSSC MS54A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide

Pin Names Description

AI

(0–8)

Input pins, A side

BI

(0–8)

Input pins, B side

AOE

1

, AOE23-STATE Output Enable Input pins, A side

BOE

1

, BOE23-STATE Output Enable Input pins, B side

AO

(0–8)

Output pins, A side

BO

(0–8)

Output pins, B side

Inputs

AO

(0–8)

AOE

1

AOE

2

AI

(0–8)

LL H L
HX X Z
XH X Z

LL L H

Inputs

BO

(0–8)

BOE

1

BOE

2

BI

(0–8)

LL H L
HX X Z
XH X Z

LL L H

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SCAN18540T

Block Diagrams

Byte-A

Tap Controller

Byte-B

Note: BSR stands for Boun dary Scan Register

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SCAN18540T

Description of BOUNDARY-SCAN Circuitry

The scan cells used in the BOUNDARY-SCAN register are
one of the followin g two types de pending upon t heir loca­tion. Scan cell TYPE1 is intended to solely observe system
data, while TYPE2 has the additional ability to control sys­tem data.

Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is locate d at each system output pin as
well as at each of the two internal active-high output enable
signals. AOE controls the activity of the A-outputs while
BOE controls the activity of the B-outputs. Each will acti­vate their respective outputs by loading a logi c high.

The BYPASS register is a single bit shift register stage
identical to scan cell TYPE1. It captures a fixed logic low.

Bypass Register Scan Chain Definition

Logic 0

The INSTRUCTION register is an 8-bit register which cap­tures the default value of 01001101. The two least signifi­cant bits of this captured value (01) are required by IEEE

Std 1149.1. The upper six bits are unique to the
SCAN18540T device. SCAN CMOS Test Access Logic
devices do not include the IEEE 1149.1 optional identifi ca­tion register. Therefore, this un ique captu red value can be
used as a “pseudo ID” code to confirm that the correct
device is placed in the appropriate location in the boundary
scan chain.

Instruction Register Scan Chain Definition

MSB

→LSB

Scan Cell TYPE1

Scan Cell TYPE2

Instruction Code Instruction

00000000 EXTEST
10000001 SAMPLE/PRELOAD
10000010 CLAMP
00000011 HIGH-Z
All Others BYPASS

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SCAN18540T

BOUNDARY-SCAN Register

Scan Chain Definition (42 Bits in Length)