Fairchild Semiconductor SCAN18374TSSC, SCAN18374TSSCX Datasheet

© 2000 Fairchild Semiconductor Corporation DS010963 www.fairchildsemi.com

October 1991
Revised May 2000

SCAN18374T D-Type Flip-Flop with 3-STATE Outputs

SCAN18374T
D-Type Flip-Flop with 3-STATE Outputs

General Description

The SCAN18374T is a h igh speed, low-pow er D-type flip­flop featuring separate D-ty pe inp uts org an iz ed into dual 9­bit bytes with byte-oriented clock and output enable control
signals. This device is compliant with IEEE 1149.1 Stan­dard Test Access Port and BOUNDARY-SCAN Architec­ture with the incorporation of the defined BOUNDARY­SCAN test logic and test access port consisting of Test
Data Input (TDI), Test Data Out (TDO), Test Mode Select
(TMS), and Test Clock (TCK).

Features

■ IEEE 1149.1 (JTAG) Compliant

■ Buffered positive edge-triggered cl ock

■ 3-STATE outputs for bus-oriented applications

■ 9-bit data busses for parity applications

■ Reduced-swing outputs source 32 mA/sink 64 mA

■ Guaranteed to drive 50

Ω transmission line to TTL input

levels of 0.8V and 2.0V

■ TTL compatible inputs

■ 25 mil pitch SSOP (Shrink Small Outline Package)

■ Includes CLAMP and HIGHZ instructions

■ Member of Fairchild’s SCAN Products

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Connection Diagram Pin Descriptions

Tru th Tables

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance



= L-to-H Transition

Order Number Package Number Package Description

SCAN18374TSSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide

Pin Names Description

AI

(0–8)

, BI

(0–8)

Data Inputs
ACP, BCP Clock Pulse Inputs
AOE

1

, BOE

1

3-STATE Output Enable Inputs
AO

(0–8)

, BO

(0–8)

3-STATE Outputs

Inputs

AO

(0–8)

ACP AOE

1

AI

(0–8)

XHXZ



LLL



LHH

Inputs

BO

(0–8)

BCP BOE

1

BI

(0–8)

XHXZ



LLL



LHH

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SCAN18374T

Functional Description

The SCAN18374 consists of two sets of nine edge-trig­gered flip-flops with individual D-type inputs and 3-STATE
true outputs. The buffered clock and buffered Output
Enable pins are co mmon to all flip-flops. Each set of the
nine flip-flops will store the state of their individual D inputs
that meet the setup and hold time requirements on the

LOW-to-HIGH Clock (ACP or BCP) transition. With the
Output Enable (AOE

1

or BOE1) LOW, the contents of the

nine flip-flops are available at the outputs. When the Output
Enable is HIGH, the outputs go to the high impedance
state. Operation of the Output Enable inp ut does not affect
the state of the flip-flo ps.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Block Diagrams

Byte-A

Note: BSR stands for Boun dary Scan Register

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SCAN18374T

Block Diagrams (Continued)

Tap Controller

Byte-B

Note: BSR stands for Bounda ry Sc an Register

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SCAN18374T

Description of Boundary-Scan Circuitry

The scan cells used in the BOUNDARY-SCAN register are
one of the follow ing two types depending upon their loca­tion. Scan cell TYPE1 is intended to solely observe system
data, while TYPE2 has the additional ability to control sys­tem data.

Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is located at each system output pin as
well as at each of the two internal active-high output enable
signals. AOE controls the activit y of the A-outputs while
BOE controls the activity of the B-outputs. Each will acti­vate their respective outputs by loading a logic high.

The BYPASS register is a single bit shift register stage
identical to scan cell TYPE1. It captures a fixed logic low.

Bypass Register Scan Chain Definition

Logic 0

The INSTRUCTION register is an eight-bit register which
captures the value 00111101.

The two least significant bits of this captured value (01) are
required by IEEE Std 1149.1. The upper six bits are unique
to the SCAN18374T device. SCAN CMOS Test Access
Logic devices do not include the IEEE 1149.1 optional
identification register. Therefore, this unique captured
value can be used as a “pseudo ID” code to confirm that
the correct device is pla ced in the appropria te location in
the boundary scan chain.

Instruction Register Scan Chain Definition

MSB

→ LSB

Scan Cell TYPE1

Scan Cell TYPE2

Instruction Code Instruction

00000000 EXTEST
10000001 SAMPLE/PRELOAD
10000010 CLAMP
00000011 HIGHZ
All Others BYPASS