Fairchild Semiconductor SCAN182541ASSCX, SCAN182541ASSC Datasheet
SCAN182541A
Non-Inverting Line Driver
with 25
Ω Series Resistor Outputs
SCAN182541A Non-Inverting Line Driver with 25
January 1993
Revised August 2000
General Description
The SCAN182541A is a high performance BiCMOS line
driver featuring se pa rate da ta i npu ts o rga nize d i nt o d ual 9bit bytes with byte-oriented paired output enable control
signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary-Scan architecture
with the incorporation of th e defined Boundary-Scan test
logic and test access port consisting of Test Data Input
(TDI), Test Data Out (TDO), Test Mode Select (TMS), and
Test Clock (TCK).
Features
■ IEEE 1149.1 (JTAG) Compliant
■ High performance BiCMOS technology
Ω series resistor outputs elim inate need for external
■ 25
terminating resistors
■ Dual output enable signals per byte
■ 3-STATE outputs for bus-oriented applications
■ 25 mil pitch SSOP (Shrink Small Outline Package)
■ Includes CLAMP, IDCODE and HIGHZ instructions
■ Additional instructions SAMPLE-IN, SAMPLE-OUT and
EXTEST-OUT
■ Power up 3-STATE for hot insert
■ Member of Fairchild’s SCAN Products
Ordering Code:
Order Number
SCAN182541ASSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Devices also availab l e in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Package
Number
Package Description
Connection Diagram Pin Descriptions
Names
AI
(0–8)
BI
(0–8)
AOE
AOE
BOE
BOE
AO
BO
Pin
Input Pins, A Side
Input Pins, B Side
,
3-STATE Output Enable Input Pins, A Side
1
2
,
3-STATE Output Enable Input Pins, B Side
1
2
Output Pins, A Side
(0–8)
Output Pins, B Side
(0–8)
Description
Ω
Series Resistor Outputs
© 2000 Fairchild Semiconductor Corporation DS011543 www.fairchildsemi.com
Truth Tables
†AOE
1
LLHH
HXXZ
SCAN182541A
XHXZ
LLLL
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Block Diagrams
Inputs
†AOE
AO
AI
2
(0–8)
(0–8)
†BOE
Inputs
†BOE
1
BI
2
(0–8)
BO
(0–8)
LLHH
HXXZ
XHXZ
LLLL
Z = High Impedance
† = Inactive-to-ac ti ve tr ans ition must occur to enable outputs upon
power-up.
Byte A
Tap Controller
Byte B
Note: BSR stands for Boun dary Scan Register.
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Description of BOUNDARY-SCAN Circuitry
The scan cells used in the BOUNDARY-SCAN register are
one of the followin g two types de pending upon t heir location. Scan cell TYPE1 is intended to solely observe system
data, while TYPE2 has the additional ability to control system data.
Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is locate d at each system output pi n as
well as at each of the two internal active-high output enable
signals. AOE controls the activity of the A-outputs while
BOE controls the activity of the B-outputs. Each will activate their respectiv e outputs by loading a logi c high.
The BYPASS register is a single bit shift register stage
identical to scan cell TYPE1. It captures a fixed logic low.
Bypass Register Scan Chain Definition
SCAN182541A Product IDCODE
(32-Bit Code per IEEE 1149.1)
Version Entity
0000 111111 000000100100000001111 1
MSB LSB
Logic 0
Part ManufacturerRequired b
y
Number ID 1149.1
Scan Cell TYPE1
The INSTRUCTION r egist er is a n 8-b it r egister whic h captures the default val ue of 10 000001 (SA MPLE/PRE LOAD)
during the CAPTURE-IR inst ruct ion comm and. Th e benef it
of capturing SAMPLE/PRELOAD as the default instruction
during CAPTURE-IR is that the user is no longer required
to shift in the 8-bit instruction for SAMPLE/P RELOAD . The
sequence of: CAPTURE-IR
update the SAMPLE/PRELOAD instruction. For more information refer to the section on instruction definitions.
MSB
→LSB
SCAN182541A
→EXIT1-IR→ UPDATE-IR will
Instruction Register Scan Chain Definition
Instruction Code Instruction
00000000 EXTEST
10000001 SAMPLE/PRELOAD
10000010 CLAMP
00000011 HIGH-Z
01000001 SAMPLE-IN
01000010 SAMPLE-OUT
00100010 EXTEST-OUT
10101010 IDCODE
11111111 BYPASS
All Others BYPASS
Scan Cell TYPE2
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Description of BOUNDARY-SCAN Circuitry (Continued)
BOUNDARY-SCAN Register
Scan Chain Definition (42 Bits in Length)
SCAN182541A
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