Fairchild Semiconductor SCAN18245TSSC, SCAN18245TSSCX Datasheet

© 2000 Fairchild Semiconductor Corporation DS010961 www.fairchildsemi.com

October 1991
Revised May 2000

SCAN18245T Non-Inverting Transceiver with 3-STATE Outputs

SCAN18245T
Non-Inverting Transceiver with 3-STATE Outputs

General Description

The SCAN18245T i s a h i gh spe ed, l ow- pow e r bidi r ectio nal
line driver featuring separate data inputs organized into
dual 9-bit bytes with byte-oriented output enable and direc­tion control signals. This device is compliant with IEEE

1149.1 Standard Test Access Port and Boundary Scan
Architecture with the incorporation of the defined boundary­scan test logic and test access por t con sistin g of Test Data
Input (TDI), Test Data Out (TDO), Test Mode Select (TMS),
and Test Clock (TCK).

Features

■ IEEE 1149.1 (JTAG) Compliant

■ Dual output enable control signals

■ 3-STATE outputs for bus-oriented applications

■ 9-bit data busses for parity applications

■ Reduced-swing outputs source 32 mA/sink 64 mA

■ Guaranteed to drive 50

Ω transmission line to TTL input

levels of 0.8V and 2.0V

■ TTL compatible inputs

■ 25 mil pitch SSOP (Shrink Small Outline Package)

■ Includes CLAMP and HIGHZ instructions

■ Member of Fairchild’s SCAN Products

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Connection Diagram Pin Descriptions

Order Number Package Number Package Description

SCAN18245TSSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide

Pin Names Description

A1

(0–8)

Side A1 Inputs or 3-STATE Outputs

B1

(0–8)

Side B1 Inputs or 3-STATE Outputs

A2

(0–8)

Side A2 Inputs or 3-STATE Outputs

B2

(0–8)

Side B2 Inputs or 3-STATE Outputs

G1

, G2 Output Enable Pins

DIR1, DIR2 Direction of Data Flow Pins

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SCAN18245T

Truth Table

H= HIGH Voltage Level
L= LOW Voltage Level

X= Immaterial
Z= High Impedance

Functional Description

The SCAN18245 consists of tw o sets of nin e non-inv ertin g
bidirectional buffers wit h 3-STATE outputs and is intended
for bus-oriented applications. Direction pins (DIR1 and
DIR2) LOW enab les data from B Ports to A Ports, when

HIGH enables data from A Por ts to B Ports. The Output
Enable pins (G1

and G2) when HIGH disa bles both A and

B Ports by placing them in a high impedance condition.

Block Diagrams

A1, B1, G1 and DIR1

Note: BSR stands for Boun dary Scan Register.

A2, B2, G2 and DIR2

Note: BSR stands for B oundary Scan Register.

Tap Controller

Inputs

A1 (0–8) B1 (0–8)

Inputs

A2 (0–8) B2 (0–8)

G1

DIR1 G2 DIR2

LLH

← HLLH← H

LLL

← LLLL← L

LHH

→ HLHH→ H

LHL

→ LLHL→ L

HXZ Z HXZ Z

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SCAN18245T

Description of Boundary-Scan Circuitry

The scan cells used in the BOUNDARY-SCAN register are
one of the followin g two types de pending upon t heir loca­tion. Scan cell TYPE1 is intended to solely observe system
data, while TYPE2 has the additional ability to control sys­tem data. (See IEEE Standard 1149.1 Figure 10–11 for a
further description of scan cell TYPE1 and Figure 10–12 for
a further description of scan cell TYPE2.)

Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is locate d at each system output pin as
well as at each of the two internal active-high output enable
signals. AOE controls the activity of the A-outputs while
BOE controls the activity of the B-outputs. Each will acti­vate their respective outputs by loading a logi c high.

The BYPASS register is a single bit shift register stage
identical to scan cell TYPE1. It captures a fixed logic low.

Bypass Register Scan Chain Definition

Logic 0

The INSTRUCTION register is an eight-bit register which
captures the value 00111101.

The two least significant bits of this captured value (01) are
required by IEEE Std 1149.1. The upper six bits are unique
to the SCAN18245T device. SCAN CMOS Test Access
Logic devices do not include the IEEE 1149.1 optional
identification register. Therefore, this unique captured
value can be used as a “pseudo ID” co de to confirm that
the correct device is p laced in the appropria te location in
the boundary scan chain.

Instruction Register Scan Chain Definition

MSB

→ LSB

Scan Cell TYPE1

Scan Cell TYPE2

Instruction Code Instruction

00000000 EXTEST
10000001 SAMPLE/PRELOAD
10000010 CLAMP
00000011 HIGHZ
All Others BYPASS

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SCAN18245T

Boundary-Scan Register

Scan Chain Definition (80 Bits in Length)