Fairchild Semiconductor NM25C041EM8, NM25C041LM8X, NM25C041M8X, NM25C041N, NM25C041M8 Datasheet

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NM25C041 Rev. D.1

NM25C041 4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface

(SPI) Synchronous Bus)

March 1999

NM25C041 4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface (SPI™) Synchronous Bus)

General Description

The NM25C041 is a 4096-bit MODE 1 SPI (Serial Peripheral Interface) CMOS EEPROM which is designed for high-reliability non-volatile data storage applications. The SPI interface features a byte-wide format (all data is transferred in 8-bit words) to interface with the Motorola 68HC11 microprocessor, or equivalent, at a 2.1MHz clock transfer rate. (This interface is considered the fastest serial communication method.) This 4-wire SPI interface allows the end user full EEPROM functionality while keeping pin count and space requirements low for maximum PC board space utilization.

The SPI interface requires four I/O pins on each EEPROM device: Chip Select (CS), Clock (SCK), Serial Data In (SI), and Serial Data Out (SO), as well as 2 other control pins: Write Protect (WP) and HOLD (HOLD). The Write Protect pin can be used to disable the Write operation and the HOLD pin is used to interrupt the SI datastream and place the device in a Hold state during microprocessor instruction generation. Please refer to the following diagrams and description for more details.

All programming cycles are completely self-timed and do not require an ERASE, or similar setup, before programming any cells. Programming can be performed in 3 modes, address (byte) write, page (4 addresses/bytes) write or partial page write. Furthermore, the EEPROM is provided with 4 levels of write protection wherein the data, once programmed, cannot be altered. This is controlled

Block Diagram

by the Status Register and is described in greater detail within this datasheet. In order to prevent spurious programming, the EEPROM has both a Write Enable command, which is immediately disabled after each programming operation, and a Write Protect (WP) pin, which must be pulled HIGH to program.

Features

■ 2.1 MHz clock rate @ 2.7V to 5.5V

■ 4096 bits organized as 512 x 8

■ Multiple chips on the same 3 wire bus with separate chip

select lines

■ Self-timed programming cycle

■ Simultaneous programming of 1 to 4 bytes at a time

■ Status register can be polled during programming to monitor

RDY/BUSY

■ Both the Write Protect (WP) pin and 'auto-write disable after programming' provides hardware and software write protection

■ Block write protect feature to protect against accidental writes

■ Endurance: 1,000,000 data changes

■ Data retention greater than 40 years

■ Packages available: 8-pin DIP and 8-pin SO

DS800002-1

SPI™ is a trademark of Motorola Corporation.

Instruction

Decoder

Control Logic

and Clock

Generators

High Voltage

Generator

and

Program

Timer

Instruction

Program Enable

Data In/Out Register

8 Bits

Data Out

Buffer

Non-Volatile

Status Register

Decoder 1 of 512

Address Counter/ Register

EEPROM Array

4096 Bits (512 x 8)

Read/Write Amps

HOLD

SCK

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NM25C041 Rev. D.1

NM25C041 4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface

(SPI) Synchronous Bus)

Connection Diagram

Dual-In-Line Package (N)

and SO Package (M8)

Top View

Pin Names

CS Chip Select Input

SO Serial Data Output WP Write Protect V

Ground

SI Serial Data Input

SCK Serial Clock Input

HOLD Suspends Serial Data

Power Supply

Ordering Information NM 25 C XX LZ E XX Letter Description

Package N 8-pin DIP

M8 8-pin SO

Temp. Range None 0 to 70°C

V -40 to +125°C E -40 to +85°C

Voltage Operating Range Blank 4.5V to 5.5V

L 2.7V to 4.5V LZ 2.7V to 4.5V and

<1µA Standby Current

Density/Mode 041 4K, mode 1

C CMOS

Interface 25 SPI

NM Fairchild Non-Volatile

Memory

SO WP V

HOLD SCK SI

8 7 6 5

1 2 3 4

DS800002-2

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NM25C041 Rev. D.1

NM25C041 4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface

(SPI) Synchronous Bus)

Absolute Maximum Ratings (Note 1)

Ambient Storage Temperature -65°C to +150°C All Input or Output Voltages +6.5V to -0.3V

with Respect to Ground Lead Temperature (Soldering, 10 sec.) +300°C ESD Rating 2000V

Operating Conditions

Ambient Operating Temperature

NM25C041 0°C to +70°C NM25C041E -40°C to +85°C NM25C041V -40°C to +125°C

Power Supply (VCC)

NM25C041 4.5V to 5.5V

DC and AC Electrical Characteristics 4.5V ≤ VCC ≤ 5.5V

Symbol Parameter Conditions Min Max Units

Operating Current CS = V

3mA

CCSB

Standby Current CS = V

50 µA

Input Leakage VIN = 0 to V

-1 1 µA

Output Leakage V

OUT

= GND to V

-1 1 µA

Input Low Voltage -0.3 VCC * 0.3 V

Input High Voltage 0.7 * V

VCC + 0.3 V

Output Low Voltage IOL = 1.6 mA 0.4 V

Output High Voltage IOH = -0.8 mA VCC - 0.8 V

SCK Frequency 2.1 MHz

Input Rise Time 2.0 µs

Input Fall Time 2.0 µs

CLH

Clock High Time (Note 2) 190 ns

CLL

Clock Low Time (Note 2) 190 ns

CSH

Min CS High Time (Note 3) 240 ns

CSS

CS Setup Time 240 ns

DIS

Data Setup Time 100 ns

HDS

HOLD Setup Time 90 ns

CSN

CS Hold Time 240 ns

DIN

Data Hold Time 100 ns

HDN

HOLD Hold Time 90 ns

Output Delay CL = 200 pF 240 ns

Output Hold Time 0 ns

HOLD to Output Low Z 100 ns

Output Disable Time CL = 200 pF 240 ns

HOLD to Output High Z 100 ns

Write Cycle Time 1–4 Bytes 10 ms

Capacitance (Note 4) T

= 25°C, f = 2.1/1 MHz

Symbol Test Typ Max Units

OUT

Output Capacitance

38pF

Input Capacitance 2 6 pF

AC Test Conditions

Output Load CL = 200 pF Input Pulse Levels 0.1 * VCC - 0.9 * V

Timing Measurement Reference Level 0.3 * VCC - 0.7 * V

Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Note 2: The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, t

CLH

+ t

CLL

must be equal to or greater than 1/fOP. For

example, if the 2.1MHz period = 476ns and t

CLH

= 190ns, t

CLL

must be 286ns.

Note 3: CS must be brought high for a minimum of t

CSH

between consecutive instruction cycles.

Note 4: This parameter is periodically sampled and not 100% tested.

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