Fairchild Semiconductor NDB4050L, NDP4050L Datasheet
NDP4050L / NDB4050L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
April 1996
These logic level N-Channel enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process has been especially tailored to minimize on-state
resistance, provide superior switching performance, and
withstand high energy pulses in the avalanche and
commutation modes. These devices are particularly suited for
low voltage applications such as automotive, DC/DC
converters, PWM motor controls, and other battery powered
circuits where fast switching, low in-line power loss, and
resistance to transients are needed.
15A, 50V. R
Low drive requirements allowing operation directly from logic
drivers. V
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
175°C maximum junction temperature rating.
High density cell design for extremely low R
= 0.1Ω @ VGS = 5V
DS(ON)
< 2.0V.
GS(TH)
DS(ON)
.
TO-220 and TO-263 (D2PAK) package for both through hole
and surface mount applications.
_______________________________________________________________________________
D
G
S
Absolute Maximum Ratings T
= 25°C unless otherwise noted
C
Symbol Parameter NDP4050L NDB4050L Units
V
DSS
V
DGR
V
GSS
Drain-Source Voltage 50 V
Drain-Gate Voltage (RGS < 1 MΩ)
50 V
Gate-Source Voltage - Continuous ± 16 V
- Nonrepetitive (tP < 50 µs) ± 25
I
D
Drain Current - Continuous 15 A
- Pulsed 45
P
D
Total Power Dissipation @ TC = 25°C
50 W
Derate above 25°C 0.33 W/°C
TJ,T
T
L
© 1997 Fairchild Semiconductor Corporation
Operating and Storage Temperature -65 to 175 °C
STG
Maximum lead temperature for soldering
275 °C
purposes, 1/8" from case for 5 seconds
NDP4050L Rev. B / NDB4050L Rev. C
Electrical Characteristics (T
= 25°C unless otherwise noted)
C
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE AVALANCHE RATINGS (Note 1)
W
DSS
I
AR
Single Pulse Drain-Source Avalanche
VDD = 25 V, ID = 15 A 40 mJ
Energy
Maximum Drain-Source Avalanche Current 15 A
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
Drain-Source Breakdown Voltage
DSS
Zero Gate Voltage Drain Current
VGS = 0 V, ID = 250 µA
VDS = 50 V, V
GS
= 0 V
TJ =125°C
Gate - Body Leakage, Forward
VGS = 16 V, VDS = 0 V
Gate - Body Leakage, Reverse VGS = -16 V, VDS= 0 V -100 nA
50 V
250 µA
1 mA
100 nA
ON CHARACTERISTICS (Note 1)
V
R
I
g
D(on)
GS(th)
DS(ON)
FS
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
TJ =125°C
Static Drain-Source On-Resistance VGS = 5 V, ID = 7.5 A 0.085 0.1
TJ =125°C
VGS = 10 V, ID = 15 A
On-State Drain Current VGS = 5 V, VDS = 10 V 15 A
Forward Transconductance
VDS = 10 V, ID = 7.5 A
1 1.5 2 V
0.65 1.1 1.5
Ω
0.14 0.16
0.07 0.08
3 8 S
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 170 200 pF
Reverse Transfer Capacitance 50 100 pF
VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
510 600 pF
SWITCHING CHARACTERISTICS (Note 1)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
Turn - On Delay Time
Turn - On Rise Time 151 250 nS
Turn - Off Delay Time 35 100 nS
VDD = 30 V, ID = 15 A,
VGS = 5 V, R
R
= 51 Ω
GS
GEN
= 51 Ω,
Turn - Off Fall Time 61 150 nS
g
gs
gd
Total Gate Charge
Gate-Source Charge 2 nC
Gate-Drain Charge 6.1 nC
VDS = 48 V,
ID = 15 A, VGS = 5 V
9 20 nS
11 17 nC
NDP4050L Rev. B / NDB4050L Rev. C
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