Fairchild Semiconductor NDH854P Datasheet
NDH854P
P-Channel Enhancement Mode Field Effect Transistor
General Description Features
May 1997
SuperSOTTM-8 P-Channel enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance
and provide superior switching performance. These devices
are particularly suited for low voltage applications such as
notebook computer power management and other battery
powered circuits where fast switching, low in-line power loss,
-5.1 A, -30 V. R
R
Proprietary SuperSOTTM-8 package design using copper
lead frame for superior thermal and electrical capabilities.
High density cell design for extremely low R
Exceptional on-resistance and maximum DC current
capability.
= 0.032 Ω @ VGS = -10 V
DS(ON)
= 0.052 Ω @ VGS = -4.5V.
DS(ON)
DS(ON)
.
and resistance to transients are needed.
____________________________________________________________________________________________
5
6
7
8
4
3
2
1
Absolute Maximum Ratings T
Symbol Parameter NDH854P Units
V
DSS
V
GSS
I
D
P
D
TJ,T
THERMAL CHARACTERISTICS
R
JA
θ
R
θJC
© 1997 Fairchild Semiconductor Corporation
Drain-Source Voltage -30 V
Gate-Source Voltage ±20 V
Drain Current - Continuous (Note 1a) -5.1 A
- Pulsed -15
Maximum Power Dissipation (Note 1a) 1.8 W
(Note 1b)
(Note 1c)
Operating and Storage Temperature Range -55 to 150 °C
STG
Thermal Resistance, Junction-to-Ambient (Note 1a) 70 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 20 °C/W
= 25°C unless otherwise noted
A
1
0.9
NDH854P Rev.D
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -30 V
Zero Gate Voltage Drain Current
VDS = -24 V, V
GS
= 0 V
-1 µA
TJ = 55oC -10 µA
I
I
GSSF
GSSR
Gate - Body Leakage, Forward
VGS = 20 V, VDS = 0 V
Gate - Body Leakage, Reverse VGS = -20 V, VDS= 0 V -100 nA
100 nA
ON CHARACTERISTICS (Note 2)
V
GS(th)
Gate Threshold Voltage
VDS = VGS, ID = -250 µA
-1 -1.4 -2 V
TJ = 125oC -0.8 -1.1 -1.6
R
I
g
DS(ON)
D(on)
FS
Static Drain-Source On-Resistance
On-State Drain Current
Forward Transconductance
VGS = -10 V, ID = -5.1 A
TJ = 125oC
VGS = -4.5 V, ID = -4.7 A
VGS = -10 V, VDS = -5 V
VGS = -4.5 V, VDS = -5 V
VDS = - 10 V, ID = -5.1 A
0.026 0.032
0.038 0.057
0.044 0.052
-15 A
-5
12 S
Ω
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 735 pF
VDS = -15 V, VGS = 0 V,
f = 1.0 MHz
Reverse Transfer Capacitance 290 pF
1220 pF
SWITCHING CHARACTERISTICS (Note 2)
t
D(on)
t
r
t
D(off)
t
f
Q
g
Q
gs
Q
gd
Turn - On Delay Time VDD = -10 V, ID = -1 A,
V
= -10 V, R
Turn - On Rise Time 16 30 ns
GEN
GEN
= 6 Ω
15 30 ns
Turn - Off Delay Time 72 140 ns
Turn - Off Fall Time 48 95 ns
Total Gate Charge VDS = -10 V,
Gate-Source Charge 4 nC
ID = -5.1 A, VGS = -10 V
39 55 nC
Gate-Drain Charge 8 nC
NDH854P Rev.D
Electrical Characteristics (T
TJ−
T
TJ−
T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Notes:
1. R
design while R
P
Typical R
Maximum Continuous Drain-Source Diode Forward Current -1.5 A
Drain-Source Diode Forward Voltage
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
(t)
D
is determined by the user's board design.
CA
θ
A
=
(t)
R
θ
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
JA
θ
a. 70oC/W when mounted on a 1 in2 pad of 2oz copper.
b. 125oC/W when mounted on a 0.026 in2 pad of 2oz copper.
c. 135oC/W when mounted on a 0.005 in2 pad of 2oz copper.
A
2
=
R
+R
θ
JC
(t)
= I
× R
DS(ON)@T
D
(t)
θ
CA
J
1a
VGS = 0 V, IS = -1.5 A
1b
(Note 2)
1c
-0.74 -1.2 V
is guaranteed by
JC
θ
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDH854P Rev.D
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