Fairchild Semiconductor NDH8521C Datasheet
NDH8521C
Dual N & P-Channel Enhancement Mode Field Effect Transistor
General Description Features
May 1997
These dual N- and P-Channel enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance
and provide superior switching performance. These devices
are particularly suited for low voltage applications such as
notebook computer power management and other battery
powered circuits where fast switching, low in-line power loss,
and resistance to transients are needed.
N-Ch 3.8 A, 30 V, R
R
P-Ch -2.7 A, -30 V,R
R
=0.033Ω @ VGS=10 V
DS(ON)
=0.05 Ω @ VGS=4.5 V
DS(ON)
=0.07 Ω @ VGS=-10 V
DS(ON)
=0.115 Ω @ VGS=-4.5 V.
DS(ON)
Proprietary SuperSOTTM-8 package design using copper lead
frame for superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
________________________________________________________________________________
5
6
7
8
4
3
2
1
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter N-Channel P-Channel Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 30 -30 V
Gate-Source Voltage ±20 ±20 V
Drain Current - Continuous (Note 1) 3.8 -2.7 A
- Pulsed 10.5 -8
P
D
TJ,T
Power Dissipation for Single Operation (Note 1) 0.8 W
Operating and Storage Temperature Range -55 to 150 °C
STG
THERMAL CHARACTERISTICS
R
θJA
R
θJC
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note 1) 156 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W
NDH8521C Rev.C
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Type Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA N-Ch 30 V
VGS = 0 V, ID = -250 µA
Zero Gate Voltage Drain Current VDS = 24 V, V
VDS = -24 V, V
= 0 V N-Ch 1 µA
GS
TJ = 55oC
= 0 V P-Ch -1 µA
GS
TJ = 55oC
P-Ch -30 V
10 µA
-10 µA
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V All 100 nA
Gate - Body Leakage, Reverse
VGS = -20 V, VDS= 0 V
All -100 nA
ON CHARACTERISTICS (Note 2)
V
R
GS(th)
DS(ON)
Gate Threshold Voltage
Static Drain-Source On-Resistance
VDS = VGS, ID = 250 µA
TJ = 125oC
VDS = VGS, ID = -250 µA
TJ = 125oC
VGS = 10 V, ID = 3.8 A
N-Ch 1 1.67 2 V
0.8 1.04 1.6
P-Ch -1 -1.6 -2
-0.8 -1.2 -1.6
N-Ch 0.027 0.033
Ω
TJ = 125oC 0.04 0.063
VGS = 4.5 V, ID = 3.2 A
0.041 0.05
VGS = -10 V, ID = -2.7 A P-Ch 0.062 0.07
TJ = 125oC
0.088 0.125
VGS = -4.5 V, ID = - 2.1 A 0.102 0.115
I
D(on)
On-State Drain Current
VGS = 10 V, VDS = 5 V
N-Ch 10.5 A
VGS = 4.5 V, VDS = 5 V 9
VGS = -10 V, VDS = -5 V
P-Ch -8
VGS = -4.5 V, VDS = -5 V -3
g
FS
Forward Transconductance
VDS = 5 V, ID = 3.8 A
N-Ch 9 S
VDS = -5 V, ID = -2.7 A P-Ch 5.5
DYNAMIC CHARACTERISTICS
C
iss
Input Capacitance N-Channel
VDS = 15 V, VGS = 0 V,
f = 1.0 MHz
C
oss
C
rss
Output Capacitance N-Ch 310 pF
P-Channel
Reverse Transfer Capacitance N-Ch 125 pF
VDS = -15 V, VGS = 0 V,
f = 1.0 MHz
N-Ch 500 pF
P-Ch 560
P-Ch 340
P-Ch 130
NDH8521C Rev.C
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Type Min Typ Max Units
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
D(on)
r
D(off)
f
Turn - On Delay Time N-Channel
VDD = 10 V, ID = 1 A,
V
= 10 V, R
Turn - On Rise Time N-Ch 15 28 ns
GEN
GEN
= 6 Ω
P-Channel
Turn - Off Delay Time N-Ch 20 35 ns
VDD = -10 V, ID = -1 A,
V
= -10 V, R
GEN
GEN
= 6 Ω
N-Ch 10 18 ns
P-Ch 13 25
P-Ch 16 30
P-Ch 35 70
Turn - Off Fall Time N-Ch 9 18 ns
P-Ch 40 80
Q
g
Q
gs
Q
gd
Total Gate Charge N-Channel
VDS = 15 V,
ID = 3.8 A, VGS = 10 V
N-Ch 18 25 nC
P-Ch 19 27
Gate-Source Charge N-Ch 1.8 nC
P-Channel
Gate-Drain Charge N-Ch 4.2 nC
VDS = -15 V,
ID = -2.7 A, VGS = -10 V
P-Ch 3.8
P-Ch 4.7
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
Maximum Continuous Drain-Source Diode Forward Current N-Ch 0.67 A
P-Ch -0.67
V
Notes:
1. R
SD
design while R
Drain-Source Diode Forward Voltage
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
is determined by the user's board design.
CA
θ
VGS = 0 V, IS = 0.67 A
VGS = 0 V, IS = -0.67 A
(Note2)
(Note2)
N-Ch 0.72 1.2 V
P-Ch -0.74 -1.2
is guaranteed by
JC
θ
T
(t)
P
=
D
R
Scale 1 : 1 on letter size paper.
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
J−TA
θJA
T
J−TA
=
(t)
R
θJC+RθCA
2
= I
(t)×R
D
(t)
DS(O N ) T
Typical R
for single device operation using the board layout shown below on 4.5"x5" FR-4 PCB in a still air environment:
JA
J
θ
156oC/W when mounted on a 0.0025 in2 pad of 2oz copper.
NDH8521C Rev.C
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