Fairchild Semiconductor NDH8520C Datasheet
December 1996
NDH8520C
Dual N & P-Channel Enhancement Mode Field Effect Transistor
General Description Features
These dual N- and P-Channel enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance
and provide superior switching performance. These devices
are particularly suited for low voltage applications such as
notebook computer power management and other battery
powered circuits where fast switching, low in-line power loss,
and resistance to transients are needed.
___________________________________________________________________________________
N-Channel 2.8 A, 30 V,R
R
=0.1Ω @ VGS=4.5 V P-Channel -2.2 A,-30 V,
DS(ON)
R
=0.11Ω @ VGS=-10 V
DS(ON)
R
=0.18 Ω @ VGS=-4.5 V.
DS(ON)
=0.07Ω @ VGS=10 V
DS(ON)
Proprietary SuperSOTTM-8 package design using copper lead
frame for superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current capability.
5
6
7
4
3
2
8
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter N-Channel P-Channel Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 30 -30 V
Gate-Source Voltage ±20 ±20 V
Drain Current - Continuous (Note 1) 2.8 -2.2 A
- Pulsed 10 -10
P
D
TJ,T
Power Dissipation for Single Operation (Note 1) 0.8 W
Operating and Storage Temperature Range -55 to 150 °C
STG
THERMAL CHARACTERISTICS
R
θ
R
θ
Thermal Resistance, Junction-to-Ambient (Note 1) 156 °C/W
JA
Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W
JC
1
© 1997 Fairchild Semiconductor Corporation
NDH8520C Rev.B
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Type Min Typ Max Units
OFF CHARACTERISTICS
BV
I
I
I
DSS
DSS
GSSF
GSSR
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA N-Ch 30 V
VGS = 0 V, ID = -250 µA
Zero Gate Voltage Drain Current VDS = 24 V, V
VDS = -24 V, V
= 0 V N-Ch 1 µA
GS
TJ = 55oC
= 0 V P-Ch -1 µA
GS
TJ = 55oC
P-Ch -30 V
10 µA
-10 µA
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V All 100 nA
Gate - Body Leakage, Reverse
VGS = -20 V, VDS= 0 V
All -100 nA
ON CHARACTERISTICS (Note 2)
V
R
GS(th)
DS(ON)
Gate Threshold Voltage
Static Drain-Source On-Resistance
VDS = VGS, ID = 250 µA
TJ = 125oC
VDS = VGS, ID = -250 µA
TJ = 125oC
VGS = 10 V, ID = 2.8 A
N-Ch 1 1.6 2.8 V
0.8 1.2 2
P-Ch -1 -1.5 -3
-0.8 -1.2 -2.2
N-Ch 0.05 0.07
Ω
TJ = 125oC 0.07 0.125
VGS = 4.5 V, ID = 2.3 A
0.077 0.1
VGS = -10 V, ID = -2.2 A P-Ch 0.1 0.11
TJ = 125oC
0.14 0.2
VGS = -4.5 V, ID = -1.7 A 0.17 0.18
I
D(on)
On-State Drain Current
VGS = 10 V, VDS = 5 V
N-Ch 10 A
VGS = 4.5 V, VDS = 5 V 3
VGS = -10 V, VDS = -5 V
P-Ch -10
VGS = -4.5 V, VDS = -5 V -4
g
FS
Forward Transconductance
VDS = 10 V, ID = 2.8 A
N-Ch 5.8 S
VDS = -10 V, ID = -2.2 A P-Ch 3.8
DYNAMIC CHARACTERISTICS
C
iss
Input Capacitance N-Channel
VDS = 15 V, VGS = 0 V,
f = 1.0 MHz
C
oss
C
rss
Output Capacitance N-Ch 170 pF
P-Channel
Reverse Transfer Capacitance N-Ch 55 pF
VDS = -15 V, VGS = 0 V,
f = 1.0 MHz
N-Ch 270 pF
P-Ch 340
P-Ch 218
P-Ch 100
NDH8520C Rev.B
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Type Min Typ Max Units
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
D(on)
r
D(off)
f
Turn - On Delay Time N-Channel
VDD = 10 V, ID = 1 A,
V
= 10 V, R
Turn - On Rise Time N-Ch 15 28 ns
GEN
GEN
= 6 Ω
P-Channel
Turn - Off Delay Time N-Ch 15 28 ns
VDD = -10 V, ID = -1 A,
V
= -10 V, R
GEN
GEN
= 6 Ω
N-Ch 8 15 ns
P-Ch 8 15
P-Ch 18 35
P-Ch 28 50
Turn - Off Fall Time N-Ch 5 10 ns
P-Ch 20 35
Q
g
Q
gs
Q
gd
Total Gate Charge N-Channel
VDS = 15 V,
ID = 2.8 A, VGS = 10 V
N-Ch 9.4 17 nC
P-Ch 10.9 14.5
Gate-Source Charge N-Ch 0.8 nC
P-Channel
Gate-Drain Charge N-Ch 3 nC
VDS = -15 V,
ID = -2.2 A, VGS = -10 V
P-Ch 1.4
P-Ch 3.6
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
Maximum Continuous Drain-Source Diode Forward Current N-Ch 0.67 A
P-Ch -0.67
V
Notes:
1. R
SD
design while R
Drain-Source Diode Forward Voltage
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
is determined by the user's board design.
CA
θ
VGS = 0 V, IS = 0.67 A
VGS = 0 V, IS = -0.67 A
(Note2)
(Note2)
N-Ch 0.7 1.2 V
P-Ch -0.76 -1.2
is guaranteed by
JC
θ
T
P
(t) =
D
R
Typical R
JA
θ
156oC/W when mounted on a 0.0025 in2 pad of 2oz copper.
Scale 1 : 1 on letter size paper.
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
T
J−TA
θJ A
for single device operation using the board layout shown below on 4.5"x5" FR-4 PCB in a still air environment:
J−TA
=
R
(t)
θJ C+RθCA
2
= I
(t )×R
D
(t)
DS(ON)@T
J
NDH8520C Rev.B
Typical Electrical Characteristics: N-Channel
15
V =10V
GS
12
D
I , DRAIN-SOURCE CURRENT (A)
7.0
9
6
3
0
0 0.5 1 1.5 2 2.5 3
6.0
5.0
4.5
4.0
3.5
V , DRAIN-SOURCE VOLTAGE (V)
DS
Figure 1. N-Channel On-Region Characteristics.
1.6
I = 2.8A
D
V = 4.5V
1.4
1.2
DS(ON)
R , NORMALIZED
0.8
DRAIN-SOURCE ON-RESISTANCE
0.6
GS
1
-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)
J
3.0
2.5
V = 3.5V
GS
2
4.0
4.5
1.5
DS(on)
R , NORMALIZED
1
DRAIN-SOURCE ON-RESISTANCE
0.5
0 3 6 9 12 15
I , DRAIN CURRENT (A)
D
5.0
6.0
7.0
10
Figure 2. N-Channel On-Resistance Variation with Gate
Voltage and Drain Current.
2
V = 10 V
GS
1.5
1
DS(on)
0.5
R , NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
0
0 3 6 9 12 15
I , DRAIN CURRENT (A)
D
T = 125°C
J
25°C
-55°C
Figure 3. N-Channel On-Resistance Variation with
Temperature.
10
V = 10V
DS
8
6
4
D
I , DRAIN CURRENT (A)
2
0
0 1 2 3 4 5
V , GATE TO SOURCE VOLTAGE (V)
GS
T = -55°C
J
125°C
Figure 5. N-Channel Transfer
Characteristics.
25°C
Figure 4. N-Channel On-Resistance Variation with Drain
Current and Temperature.
1.2
V = V
DS
GS
I = 250µA
1.1
1
0.9
th
V , NORMALIZED
0.8
GATE-SOURCE THRESHOLD VOLTAGE
0.7
-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)
J
D
Figure 6. N-Channel Gate Threshold Variation
with Temperature.
NDH8520C Rev.B
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