Fairchild Semiconductor NDH8447 Datasheet
NDH8447
P-Channel Enhancement Mode Field Effect Transistor
General Description Features
May 1996
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance. These devices are particularly
suited for low voltage applications such as notebook computer
-4.4A, -30V. R
R
High density cell design for extremely low R
= 0.053 @ VGS = -10V
DS(ON)
= 0.095Ω @ VGS = -4.5V
DS(ON)
DS(ON).
Enhanced SuperSOTTM-8 small outline surface mount
package with high power and current handling capability.
power management and other battery powered circuits where
fast switching, low in-line power loss, and resistance to
transients are needed.
____________________________________________________________________________________________
5
6
7
8
4
3
2
1
SuperSOTTM-8
Absolute Maximum Ratings T
= 25°C unless otherwise note
A
Symbol Parameter NDH8447 Units
V
DSS
V
GSS
I
D
Drain-Source Voltage -30 V
Gate-Source Voltage -20 V
Drain Current - Continuous (Note 1a) -4.4 A
- Pulsed -20
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 1.8 W
(Note 1b)
(Note 1c)
Operating and Storage Temperature Range -55 to 150 °C
STG
1
0.9
THERMAL CHARACTERISTICS
R
θ
R
θ
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note 1a) 70 °C/W
JA
Thermal Resistance, Junction-to-Case (Note 1) 20 °C/W
JC
NDH8447 Rev. C1
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -30 V
Zero Gate Voltage Drain Current
VDS = -24 V, V
GS
= 0 V
TJ = 55°C
-1 µA
-10 µA
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -20 V, VDS= 0 V
-100 nA
ON CHARACTERISTICS (Note 2)
V
R
I
g
GS(th)
DS(ON)
D(on)
FS
Gate Threshold Voltage VDS = VGS, ID = -250 µA -1 -1.5 -3 V
TJ = 125°C
-0.7 -1.2 -2.2
Static Drain-Source On-Resistance VGS = -10 V, ID = -4.4 A 0.045 0.053
0.075 0.11
0.08 0.095
-15 A
7 S
On-State Drain Current
Forward Transconductance
TJ = 125°C
VGS = -4.5 V, ID = -3.4 A
VGS = -10 V, VDS = -5 V
VDS = -10 V, ID = -4.4 A
Ω
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 430 pF
VDS = -15 V, V
f = 1.0 MHz
GS
= 0 V,
Reverse Transfer Capacitance 160 pF
670 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
g
gs
gd
Turn - On Delay Time VDD = -15 V, ID = -1 A,
V
= -10 V, R
Turn - On Rise Time 15 25 ns
GEN
GEN
= 6 Ω
11 20 ns
Turn - Off Delay Time 36 50 ns
Turn - Off Fall Time 27 40 ns
Total Gate Charge VDS = -15 V,
Gate-Source Charge 2.8 nC
ID = -4.4 A, VGS = -10 V
20 30 nC
Gate-Drain Charge 6 nC
NDH8447 Rev. C1
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Notes:
1. R
design while R
P
Typical R
Scale 1 : 1 on letter size paper
Maximum Continuous Drain-Source Diode Forward Current -1.5 A
Drain-Source Diode Forward Voltage
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
(t)
D
is determined by the user's board design.
CA
θ
T
=
R
JA
θ
a. 70oC/W when mounted on a 1 in2 pad of 2oz cpper.
b. 125oC/W when mounted on a 0.026 in2 pad of 2oz copper.
c. 135oC/W when mounted on a 0.005 in2 pad of 2oz copper.
T
J−TA
θJA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
J−TA
=
(t)
R
θJC+RθCA
2
= I
(t) ×R
DS(ON ) T
D
(t)
J
1a
VGS = 0 V, IS = -1.5 A
1b
(Note 2)
1c
-0.8 -1.2 V
is guaranteed by
JC
θ
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDH8447 Rev. C1
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