Fairchild Semiconductor NDH833N Datasheet
February 1997
NDH833N
N-Channel Enhancement Mode Field Effect Transistor
General Description Features
SuperSOTTM-8 N-Channel enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance
and provide superior switching performance. These devices
are particularly suited for low voltage applications such as
battery powered circuits or portable electronics where fast
switching, low in-line power loss, and resistance to transients
7.1 A, 20 V. R
R
Proprietary SuperSOTTM-8 package design using copper
lead frame for superior thermal and electrical capabilities.
High density cell design for extremely low R
Exceptional on-resistance and maximum DC current
capability.
are needed.
___________________________________________________________________________________________
= 0.020 Ω @ VGS = 4.5 V
DS(ON)
= 0.025 Ω @ VGS = 2.7 V.
DS(ON)
DS(ON)
.
5
6
7
8
4
3
2
1
Absolute Maximum Ratings T
= 25°C unless otherwise note
A
Symbol Parameter NDH833N Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 20 V
Gate-Source Voltage ±8 V
Drain Current - Continuous (Note 1a) 7.1 A
- Pulsed 24
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 1.8 W
(Note 1b)
(Note 1c)
Operating and Storage Temperature Range -55 to 150 °C
STG
1
0.9
THERMAL CHARACTERISTICS
R
JA
θ
R
JC
θ
Thermal Resistance, Junction-to-Ambient (Note 1a) 70 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 20 °C/W
© 1997 Fairchild Semiconductor Corporation
NDH833N Rev. C
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
I
I
DSS
DSS
GSSF
GSSR
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 20 V
Zero Gate Voltage Drain Current
VDS = 16 V, V
GS
= 0 V
TJ= 55°C
1 µA
10 µA
Gate - Body Leakage, Forward VGS = 8 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -8 V, VDS= 0 V
-100 nA
ON CHARACTERISTICS (Note 2)
V
R
I
g
GS(th)
DS(ON)
D(on)
FS
Gate Threshold Voltage VDS = VGS, ID = 250 µA 0.4 0.62 1 V
TJ= 125°C
0.3 0.4 0.8
Static Drain-Source On-Resistance VGS = 4.5 V, ID = 7.1 A 0.015 0.02
0.022 0.036
0.018 0.025
24 A
35 S
On-State Drain Current
Forward Transconductance
TJ= 125°C
VGS = 2.7 V, ID = 6.7 A
VGS = 10 V, VDS = 5 V
VDS = 5 V, ID = 7.1 A
Ω
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 750 pF
VDS = 10 V, V
f = 1.0 MHz
GS
= 0 V,
Reverse Transfer Capacitance 265 pF
1540 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
g
gs
gd
Turn - On Delay Time VDD = 5 V, ID = 1 A,
V
= 4.5 V, R
Turn - On Rise Time 35 70 ns
GEN
GEN
= 6 Ω
12 20 ns
Turn - Off Delay Time 110 200 ns
Turn - Off Fall Time 60 120 ns
Total Gate Charge VDS = 10 V,
Gate-Source Charge 8 nC
ID = 7.1 A, VGS = 10 V
97 140 nC
Gate-Drain Charge 33 nC
NDH833N Rev. C
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Notes:
1. R
θ
design while R
P
D
Typical R
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
Maximum Continuous Drain-Source Diode Forward Current 1.5 A
Drain-Source Diode Forward Voltage
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
(t)
is determined by the user's board design.
CA
θ
T
=
R
JA
θ
a. 70oC/W when mounted on a 1 in2 pad of 2oz cpper.
b. 125oC/W when mounted on a 0.026 in2 pad of 2oz copper.
c. 135oC/W when mounted on a 0.005 in2 pad of 2oz copper.
T
J−TA
=
(t)
R
θJ A
θ
J C
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
J−TA
+R
2
= I
(t) × R
DS(ON ) T
D
(t)
θ
CA
J
1a
VGS = 0 V, IS = 1.5 A (Note 2)
1b
1c
0.65 1.2 V
is guaranteed by
JC
θ
NDH833N Rev. C
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