Dual N & P-Channel Enhancement Mode Field Effect Transistor
General Description Features
January 1999
These dual N- and P -Channel enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance and provide superior switching
performance. These devices are particularly suited for low
voltage applications such as notebook computer power
management and other battery powered circuits where fast
switching, low in-line power loss, and resistance to
transients are needed.
N-Ch 3.8 A, 20 V, R
R
P-Ch -2.7 A, -20V, R
R
=0.035 Ω @ VGS= 4.5 V
DS(ON)
=0.045 Ω @ VGS=2.7 V
DS(ON)
=0.07Ω @ VGS= -4.5 V
DS(ON)
=0.095 Ω @ VGS= -2.7 V.
DS(ON)
Proprietary SuperSOTTM-8 package design using copper
lead frame for superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
Maximum Continuous Drain-Source Diode Forward CurrentN-Ch0.67A
P-Ch-0.67
V
SD
Notes:
1. R
by design while R
Drain-Source Diode Forward VoltageVGS = 0 V, IS = 0.67 A
VGS = 0 V, IS = -0.67 A
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
is determined by the user's board design.
CA
θ
(Note2)N-Ch0.651.2V
(Note2)P-Ch-0.7-1.2
is guaranteed
JC
θ
T
(t)
P
=
D
R
Typical R
JA
θ
156oC/W when mounted on a 0.0025 in2 pad of 2oz copper.