Fairchild Semiconductor NDH831N Datasheet
NDH831N
N-Channel Enhancement Mode Field Effect Transistor
General Description Features
July 1996
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance. These devices are particularly
suited for low voltage applications such as notebook computer
power management and portable electronics where fast
5.8A, 20V. R
R
High density cell design for extremely low R
Enhanced SuperSOTTM-8 small outline surface mount
package with high power and current handling capability.
= 0.03Ω @ VGS = 4.5V
DS(ON)
= 0.04Ω @ VGS = 2.7V.
DS(ON)
DS(ON)
.
switching, low in-line power loss, and resistance to transients
are needed.
____________________________________________________________________________________________
5
6
7
8
4
3
2
1
Absolute Maximum Ratings TA = 25°C unless otherwise noted
Symbol Parameter NDH831N Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 20 V
Gate-Source Voltage 8 V
Drain Current - Continuous (Note 1a) 5.8 A
- Pulsed 20
P
D
Maximum Power Dissipation (Note 1a) 1.8 W
(Note 1b) 1
(Note 1c) 0.9
TJ,T
Operating and Storage Temperature Range -55 to 150 °C
STG
THERMAL CHARACTERISTICS
R
JA
θ
R
JC
θ
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note 1a) 70 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 20 °C/W
NDH831N Rev. D
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 20 V
Zero Gate Voltage Drain Current
VDS = 16 V, V
GS
= 0 V
TJ= 55°C
1 µA
10 µA
Gate - Body Leakage, Forward VGS = 8 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -8 V, VDS= 0 V
-100 nA
ON CHARACTERISTICS (Note 2)
V
R
I
g
GS(th)
DS(ON)
D(on)
FS
Gate Threshold Voltage VDS = VGS, ID = 250 µA 0.4 0.6 1 V
TJ= 125°C
0.3 0.35 0.8
Static Drain-Source On-Resistance VGS = 4.5 V, ID = 5.8 A 0.022 0.03 W
0.03 0.54
0.027 0.04
20 A
5
14 S
On-State Drain Current
Forward Transconductance
TJ= 125°C
VGS = 2.7 V, ID = 5 A
VGS = 4.5 V, VDS = 5 V
VGS = 2.7 V, VDS = 5 V
VDS = 10 V, ID = 5.8 A
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance VDS = 10 V, V
Output Capacitance 430 pF
f = 1.0 MHz
GS
= 0 V,
720 pF
Reverse Transfer Capacitance 155 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
Turn - On Delay Time
Turn - On Rise Time 30 50 ns
VDD = 6 V, ID = 1 A,
V
= 4.5 V, R
GEN
GEN
= 6 Ω
Turn - Off Delay Time 55 80 ns
Turn - Off Fall Time 20 40 ns
g
gs
gd
Total Gate Charge
Gate-Source Charge 1.8 nC
Gate-Drain Charge 5.5 nC
VDS = 5 V,
ID = 5.8 A, VGS = 4.5 V
10 20 ns
19.5 28 nC
NDH831N Rev. D
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Notes:
1. R
θ
design while R
P
Typical R
Maximum Continuous Drain-Source Diode Forward Current 1.5 A
Drain-Source Diode Forward Voltage
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
(t)
D
is determined by the user's board design.
CA
θ
T
=
R
qJA
a. 70oC/W when mounted on a 1 in2 pad of 2oz copper.
b. 125oC/W when mounted on a 0.026 in2 pad of 2oz copper.
c. 135oC/W when mounted on a 0.005 in2 pad of 2oz copper.
T
J−TA
=
(t)
R
θJ A
θ
J C
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
J−TA
+R
2
= I
(t) × R
DS(ON ) T
D
(t)
θ
CA
J
VGS = 0 V, IS = 1.5 A (Note 2)
0.75 1.2 V
is guaranteed by
JC
θ
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
1a
1b
1c
NDH831N Rev. D
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