Fairchild Semiconductor NDH8301N Datasheet
NDH8301N
Dual N-Channel Enhancement Mode Field Effect Transistor
General Description Features
December 1996
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance. These
devices are particularly suited for low voltage applications such
as notebook computer power management, and other battery
powered circuits where fast switching, and low in-line power
loss are needed in a very small outline surface mount package.
3 A, 20 V. R
R
= 0.06 Ω @ VGS = 4.5 V
DS(ON)
= 0.075 Ω @ VGS = 2.7 V.
DS(ON)
Proprietary SuperSOTTM-8 package design using copper
lead frame for superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
____________________________________________________________________________________________
5
6
7
8
4
3
2
1
Absolute Maximum Ratings T
Symbol Parameter
V
DSS
V
GSS
I
D
Drain-Source Voltage 20 V
Gate-Source Voltage 8 V
Drain Current - Continuous (Note 1) 3 A
- Pulsed 15
P
D
TJ,T
Maximum Power Dissipation (Note 1 ) 0.8 W
Operating and Storage Temperature Range -55 to 150 °C
STG
THERMAL CHARACTERISTICS
R
JA
θ
R
JC
θ
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note 1) 156 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W
= 25°C unless otherwise note
A
NDH8301N
Units
NDH8301N Rev.E
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 20 V
Zero Gate Voltage Drain Current
VDS = 16 V, V
GS
= 0 V
1 µA
TJ = 55oC 10 µA
I
GSSF
I
GSSR
Gate - Body Leakage, Forward
VGS = 8 V, VDS = 0 V
Gate - Body Leakage, Reverse VGS = -8 V, VDS= 0 V -100 nA
100 nA
ON CHARACTERISTICS (Note 2)
V
GS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
0.4 0.7 1 V
TJ = 125oC 0.3 0.45 0.8
R
DS(ON)
Static Drain-Source On-Resistance
VGS = 4.5 V, ID = 3 A
0.047 0.06
Ω
TJ = 125oC 0.07 0.11
0.059 0.075
5
I
g
D(on)
FS
VGS = 2.7 V, ID = 2.6 A
On-State Drain Current VGS = 4.5 V, VDS = 5 V 15 A
VGS = 2.7 V, VDS = 5 V
Forward Transconductance VDS = 5 V, ID = 3 A 10 S
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 220 pF
VDS = 10 V, VGS = 0 V,
f = 1.0 MHz
Reverse Transfer Capacitance 85 pF
415 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
g
gs
gd
Turn - On Delay Time VDD = 5 V, ID = 1 A,
Turn - On Rise Time 25 45 ns
VGS = 4.5 V, R
GEN
= 6 Ω
8 15 ns
Turn - Off Delay Time 30 55 ns
Turn - Off Fall Time 8 15 ns
Total Gate Charge VDS = 10 V,
Gate-Source Charge 0.9 nC
ID = 3 A, VGS = 4.5 V
10 15 nC
Gate-Drain Charge 3.5 nC
NDH8301N Rev.E
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Notes:
1. R
design while R
P
D
Typical R
Scale 1 : 1 on letter size paper.
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
Maximum Continuous Drain-Source Diode Forward Current 0.67 A
Drain-Source Diode Forward Voltage
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
(t)
is determined by the user's board design.
CA
θ
T
=
R
JA
θ
θJ A
J−TA
T
=
(t)
R
θ
J C
J−TA
+R
2
= I
(t) × R
DS(ON ) T
D
(t)
θ
CA
J
for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
VGS = 0 V, IS = 0.67 A (Note 2)
156oC/W when mounted on a 0.0025 in2 pad of 2oz copper.
0.7 1.2 V
is guaranteed by
JC
θ
NDH8301N Rev.E
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