Fairchild Semiconductor NDC7002N Datasheet
NDC7002N
Dual N-Channel Enhancement Mode Field Effect Transistor
General Description Features
March 1996
These dual N-Channel enhancement mode power field
effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process has been designed to minimize
on-state resistance, provide rugged and reliable
performance and fast switching. These devices is
particularly suited for low voltage applications requiring a
0.51A, 50V, R
High density cell design for low R
= 2Ω @ VGS=10V
DS(ON)
DS(ON)
.
Proprietary SuperSOTTM-6 package design using copper
lead frame for superior thermal and electrical capabilities.
High saturation current.
low current high side switch.
____________________________________________________________________________________________
4
5
6
3
2
1
SOT-6 (SuperSOTTM-6)
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter NDC7002N Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 50 V
Gate-Source Voltage - Continuous 20 V
Drain Current - Continuous (Note 1a) 0.51 A
- Pulsed 1.5
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 0.96 W
(Note 1b)
(Note 1c)
Operating and Storage Temperature Range -55 to 150 °C
STG
0.9
0.7
THERMAL CHARACTERISTICS
R
θ
R
θ
Thermal Resistance, Junction-to-Ambient (Note 1a) 130 °C/W
JA
Thermal Resistance, Junction-to-Case (Note 1) 60 °C/W
JC
© 1997 Fairchild Semiconductor Corporation
NDC7002N.SAM
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 50 V
Zero Gate Voltage Drain Current
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
VDS = 40 V, V
GS
= 0 V
VGS = 20 V, VDS = 0 V
VGS = -20 V, VDS= 0 V
TJ = 125°C
1 µA
500
100 nA
-100 nA
ON CHARACTERISTICS (Note 2)
V
GS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
1 1.9 2.5 V
TJ = 125°C 0.8 1.5 2.2
R
DS(ON)
Static Drain-Source On-Resistance
VGS = 10 V, ID = 0.51 A
TJ = 125°C
1 2
1.7 3.5
Ω
VGS = 4.5 V, ID = 0.35 A 1.6 4
I
g
D(on)
On-State Drain Current
FS
Forward Transconductance VDS = 10 V, ID = 0.51 A 400 mS
VGS = 10 V, VDS = 10 V
1.5 A
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 13 pF
Reverse Transfer Capacitance 5 pF
VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
20 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
g
gs
gd
Turn - On Delay Time VDD = 25 V, ID = 0.25 A,
Turn - On Rise Time 6 20
VGS = 10 V, R
GEN
= 25 Ω
6 20 nS
Turn - Off Delay Time 11 20
Turn - Off Fall Time 5 20
Total Gate Charge
Gate-Source Charge 0.19 nC
VDS = 25 V,
ID = 0.51 A, VGS = 10 V
1 nC
Gate-Drain Charge 0.33 nC
NDC7002N.SAM
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS
I
S
I
SM
V
SD
Notes:
1. R
P
design while R
Typical R
Maximum Continuous Source Current 0.51 A
Maximum Pulse Source Current (Note 2) 1.5 A
Drain-Source Diode Forward Voltage VGS = 0 V, IS = 0.51 A (Note 2) 0.8 1.2 V
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
(t)
D
is determined by the user's board design.
CA
θ
T
=
R
θ
a. 130oC/W when mounted on a 0.125 in2 pad of 2oz cpper.
b. 140oC/W when mounted on a 0.005 in2 pad of 2oz cpper.
c. 180oC/W when mounted on a 0.0015 in2 pad of 2oz cpper.
T
J−TA
=
(t)
R
θJ A
θ
J C
for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
JA
J−TA
+R
2
= I
(t) × R
DS(O N ) T
D
(t)
θ
CA
J
1a 1b
1c
is guaranteed by
JC
θ
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDC7002N.SAM
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