Fairchild Semiconductor NDC652P Datasheet
March 1996
NDC652P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
These P-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance. These devices are
particularly suited for low voltage applications such as
notebook computer power management and other
battery powered circuits where fast high-side switching,
and low in-line power loss are needed in a very small
outline surface mount package.
____________________________________________________________________________________________
-2.4A, -30V. R
R
= 0.18Ω @ VGS = -4.5V
DS(ON)
= 0.11Ω @ VGS = -10V.
DS(ON)
Proprietary SuperSOTTM-6 package design using copper
lead frame for superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
4
5
6
3
2
1
Absolute Maximum Ratings T
Symbol Parameter NDC652P Units
V
V
I
D
P
TJ,T
THERMAL CHARACTERISTICS
R
R
Drain-Source Voltage -30 V
DSS
Gate-Source Voltage - Continuous -20 V
GSS
Drain Current - Continuous -2.4 A
- Pulsed -10
Maximum Power Dissipation (Note 1a) 1.6 W
D
STG
JA
θ
JC
θ
(Note 1b)
(Note 1c)
Operating and Storage Temperature Range -55 to 150 °C
Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 30 °C/W
= 25°C unless otherwise noted
A
1
0.8
© 1997 Fairchild Semiconductor Corporation
NDC652P Rev. D1
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -30 V
Zero Gate Voltage Drain Current
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
VDS = -24 V, V
GS
= 0 V
VGS = 20 V, VDS = 0 V
VGS = -20 V, VDS= 0 V
TJ = 55oC
1 µA
10 µA
100 nA
-100 nA
ON CHARACTERISTICS (Note 2)
V
R
GS(th)
DS(ON)
Gate Threshold Voltage
VDS = VGS, ID = -250 µA
TJ = 125oC
Static Drain-Source On-Resistance VGS = -4.5 V, ID = -2.4 A 0.16 0.18
TJ = 125oC
-1 -1.5 -3 V
-0.7 -1.2 -2.2
Ω
0.22 0.36
VGS = -10 V, ID = -3.1 A 0.09 0.11
I
g
D(on)
On-State Drain Current
FS
Forward Transconductance VDS = -10 V, ID = -2.4 A 3 S
VGS = -4.5 V, VDS = -5 V
-5 A
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 180 pF
VDS = -15 V, V
f = 1.0 MHz
GS
= 0 V,
Reverse Transfer Capacitance 60 pF
290 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
Turn - On Delay Time
Turn - On Rise Time 26 35 ns
VDD = -15 V, ID = -1 A,
V
= -4.5 V, R
GEN
GEN
= 6 Ω
Turn - Off Delay Time 22 30 ns
Turn - Off Fall Time 19 30 ns
g
gs
gd
Total Gate Charge
Gate-Source Charge 1.5 nC
Gate-Drain Charge 3.3 nC
VDS = -15 V,
ID = -2.4 A, VGS = -10 V
13 20 ns
10.5 20 nC
NDC652P Rev. D1
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS
I
S
V
SD
Notes:
1. R
design while R
P
Typical R
Scale 1 : 1 on letter size paper
Continuous Source Diode Current -1.3 A
Drain-Source Diode Forward Voltage
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
D
is determined by the user's board design.
CA
θ
T
(t)
=
R
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
JA
θ
a. 78oC/W when mounted on a 1 in2 pad of 2oz cpper.
b. 125oC/W when mounted on a 0.01 in2 pad of 2oz cpper.
c. 156oC/W when mounted on a 0.003 in2 pad of 2oz cpper.
θJ A
J−TA
T
=
(t)
R
θJ C+RθCA
J−TA
2
= I
(t) × R
DS(ON)T
D
(t)
J
1a
VGS = 0 V, IS = -1.3 A (Note 2)
1b
1c
-0.8 -1.2 V
is guaranteed by
JC
θ
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDC652P Rev. D1
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