Fairchild Semiconductor NDC632P Datasheet
NDC632P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
June1996
These P-Channel logic level enhancement mode
power field effect transistors are produced using
Fairchild's proprietary, high cell density, DMOS
technology. This very high density process is
especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage
applications such as notebook computer power
management and other battery powered circuits
where fast high-side switching, and low in-line power
loss are needed in a very small outline surface
-2.7A, -20V. R
R
= 0.14Ω @ VGS = -4.5V
DS(ON)
= 0.2Ω @ VGS = -2.7V.
DS(ON)
Proprietary SuperSOTTM-6 package design using copper
lead frame for superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
mount package.
___________________________________________________________________________________________
4
5
6
3
2
1
SuperSOTTM-6
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter NDC632P Units
V
V
I
D
Drain-Source Voltage -20 V
DSS
Gate-Source Voltage - Continuous -8 V
GSS
Drain Current - Continuous -2.7 A
- Pulsed -10
P
TJ,T
Maximum Power Dissipation (Note 1a) 1.6 W
D
STG
(Note 1b)
(Note 1c)
1
0.8
Operating and Storage Temperature Range -55 to 150 °C
THERMAL CHARACTERISTICS
R
R
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
JA
θ
Thermal Resistance, Junction-to-Case (Note 1) 30 °C/W
JC
θ
NDC632P Rev. B1
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -20 V
Zero Gate Voltage Drain Current
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
VDS = -16 V, V
GS
= 0 V
VGS = 8 V, VDS = 0 V
VGS = -8 V, VDS= 0 V
TJ = 55oC
-1 µA
-10 µA
100 nA
-100 nA
ON CHARACTERISTICS (Note 2)
V
R
GS(th)
DS(ON)
Gate Threshold Voltage
VDS = VGS, ID = -250 µA
TJ = 125oC
Static Drain-Source On-Resistance VGS = -4.5 V, ID = - 2.7 A 0.1 0.14
TJ = 125oC
-0.4 -0.7 -1 V
-0.3 -0.5 -0.8
Ω
0.145 0.28
VGS = -2.7 V, ID = - 2.2 A 0.152 0.2
I
D(on)
On-State Drain Current
VGS = -4.5 V, VDS = -5 V
-10 A
VGS = -2.7 V, VDS = -5 V -4
g
FS
Forward Transconductance
VDS = -10 V, ID = - 2.7 A
6 S
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance VDS = -10 V, V
Output Capacitance 260 pF
f = 1.0 MHz
GS
= 0 V,
550 pF
Reverse Transfer Capacitance 75 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
Turn - On Delay Time
Turn - On Rise Time 40 60 ns
VDD = -5 V, ID = -1 A,
V
= -4.5 V, R
GEN
GEN
= 6 Ω
Turn - Off Delay Time 25 40 ns
Turn - Off Fall Time 17 30 ns
g
gs
gd
Total Gate Charge
Gate-Source Charge 1.7 nC
Gate-Drain Charge 1.8 nC
VDS = -5 V,
ID = -2.7 A, VGS = -4.5 V
10 20 ns
8.7 15 nC
NDC632P Rev. B1
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS
I
S
V
SD
Notes:
1. R
Scale 1 : 1 on letter size paper
Continuous Source Diode Current -1.3 A
Drain-Source Diode Forward Voltage
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
design while R
(t)
P
D
Typical R
is determined by the user's board design.
CA
θ
T
=
R
JA
θ
a. 78oC/W when mounted on a 1 in2 pad of 2oz copper.
b. 125oC/W when mounted on a 0.01 in2 pad of 2oz copper.
c. 156oC/W when mounted on a 0.003 in2 pad of 2oz copper.
T
J−TA
=
(t)
R
θJ A
θJ C+RθCA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
J−TA
2
= I
(t) × R
DS(ON)T
D
(t)
J
1a
VGS = 0 V, IS = -1.3 A (Note 2)
1b
1c
-0.77 -1.2 V
is guaranteed by
JC
θ
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDC632P Rev. B1
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