Fairchild Semiconductor NC7SV57, NC7SV58 Datasheet
NC7SV57 • NC7SV58
NC7SV57 • NC7SV58 TinyLogic
June 2002
Revised January 2003
TinyLogic
ULP-A Universal Configurable
2-Input Logic Gates
General Description
The NC7SV57 and NC7SV58 are universal configurable
2-input logic gates from Fairchild’s Ultra Low Power
(ULP-A) Series of TinyLogic
tions that require e xtreme high speed, hig h drive and low
power. This product is designed for a wide low voltage
operating range (0.9V to 3.6V V
require more drive and speed than the TinyLogic ULP
series, but still offer best in class low power operation.
Each device is capable of being configured for 1 of 5
unique 2-input logic fu nctions. Any p ossible 2 -input combinatorial logic func tion can be i m ple men ted as show n in t he
Function Selection Table. Device functionality is selected
by how the device is wired at the board level. Figure 1
through Figure 10 illustrate how to connect the NC7SV57
and NC7SV58 respectivel y for the desired logic function.
All inputs have been implemented with hysteresis.
The NC7SV57 and NC7 SV58 are uniquely de signed for
optimized power and speed, and are fabricated with an
advanced CMOS techno logy to a c hieve high-speed operation while maintaining low CMOS power dissipation.
. ULP-A is ideal for applica-
) and applications that
CC
Features
■ 0.9V to 3.6V VCC supply operation
CC
CC
CC
CC
CC
from 0.9V to 3.6V
CC
■ 3.6V overvoltage tolerant I/O’s at V
■ Extremely High Speed t
PD
2.5 ns typ for 2.7V to 3.6V V
3.1 ns typ for 2.3V to 2.7V V
4.0 ns typ for 1.65V to 1.95V V
6.0 ns typ for 1.4V to 1.6V V
8.0 ns typ for 1.1V to 1.3V V
23.0 ns typ for 0.9V V
CC
■ Power-Off high impedance inputs and outputs
■ High Static Drive (I
±24 mA @ 3.00V V
±18 mA @ 2.30V V
±6 mA @ 1.65V V
±4 mA @ 1.4V V
±2 mA @ 1.1V V
±0.1 mA @ 0.9V V
OH/IOL
CC
CC
CC
CC
CC
CC
)
■ Uses patented Quiet Series noise/EMI reduction
circuitry
■ Ultra small MicroPak
leadfree package
■ Ultra low Dynamic Power
ULP-A Universal Configurable 2-Input Logic Gates
Ordering Code:
Order Number
NC7SV57P6X MAA06A V57 6-Lead SC70, EIAJ SC88, 1.25mm Wide 3k Units on Tape and Reel
NC7SV57L6X MAC06A H3 6-Lead MicroPak, 1.0mm Wide 5k Units on Tape and Reel
NC7SV58P6X MAA06A V58 6-Lead SC70, EIAJ SC88, 1.25mm Wide 3k Units on Tape and Reel
NC7SV58L6X MAC06A H4 6-Lead MicroPak, 1.0mm Wide 5k Units on Tape and Reel
Battery Life vs. V
TinyLogic, MicroPak, and Quiet Series are trademarks of Fairchild Semiconductor Corp oration.
© 2003 Fairchild Semiconductor Corporation DS500671 www.fairchildsemi.com
Package Product Code
Number Top Mark
Supply Voltage
CC
Package Description Supplied As
TinyLogic ULP and ULP -A with up to 50% les s power consumption can
extend your battery lif e significantly.
Battery Life = (V
Where, P
device
Assumes ideal 3.6V Lithium Ion battery with current rating of 900mAH and
derated 90% and device freque nc y at 10MHz, with C
= (I
battery
*I
* VCC) + (C
CC
battery
*.9)/(P
PD
)/24hrs/day
device
+ CL) * V
CC
2
* f
= 15 pF load
L
Pin Descriptions
Pin Name Description
, I1, I
I
0
2
YOutput
Data Inputs
Function Table
Inputs NC7SV57 NC7SV58
I
2I1I0
NC7SV57 • NC7SV58
LLL H L
LLH L H
LHL H L
LHH L H
HLL L H
HLH L H
HHL H L
HHH H L
H = HIGH Logic Level
L = LOW Logic Level
Y = (I0)•(I2)+(I1)•(I2)Y = (I0)•(I2)+(I1)•(I2)
Connection Diagrams
Pin Assignments for SC70
(Top View)
Pin One Orientation Diagram
Function Selection Table
2-Input Logic Function
2-Input AND NC7SV57 Figure 1
2-Input AND
with inverted input
2-Input AND
with both inputs inverted
2-Input NAND NC7SV58 Figure 6
2-Input NAND
with inverted input
2-Input NAND
with both inputs inverted
2-Input OR NC7SV58 Figure 9
2-Input OR
with inverted input
2-Input OR
with both inputs inverted
2-Input NOR NC7SV57 Figure 4
2-Input NOR
with inverted input
2-Input NOR
with both inputs inverted
2-Input XOR NC7SV58 Figure 10
2-Input XNOR NC7SV57 Figure 5
Device Connection
Selection Configuration
NC7SV58 Figures 7, 8
NC7SV57 Figure 4
NC7SV57 Figures 2, 3
NC7SV58 Figure 9
NC7SV57 Figures 2, 3
NC7SV58 Figure 6
NC7SV58 Figures 7, 8
NC7SV57 Figure 1
AAA represents Product Code Top Mark - see ordering cod e
Note: Orientation of Top Mark determines Pin One location. Read the top
product code mark lef t to right, Pin One is the lo w er left pin (see diagram ).
Pad Assignments for MicroPak
(Top Thru View)
www.fairchildsemi.com 2
Logic Configurations NC7SV57
Figure 1 through Figure 5 show the logical functions that can be implemented using the NC7SV57. The diagrams show the
DeMorgan’s equivalent logic duals for a given 2-input function. Next to the logical implementation is the board level physical
implementation of how the pins of the function should be connected.
FIGURE 1. 2-Input AND Gate FIGURE 2. 2-Input NAND with Inverted A Input
FIGURE 3. 2-Input NAND with Inverted B Input FIGURE 4. 2-Input NOR Gate
NC7SV57 • NC7SV58
FIGURE 5. 2-Input XNOR Gate
3 www.fairchildsemi.com
Logic Configurations NC7SV58
Figure 6 throu gh Figure 10 s how the lo gical fun ctions th at can b e implemen ted us ing the NC 7SV58. The diag rams sho w
the DeMorgan’s equiva lent logic duals for a given 2- input function. Next to the logical implementation is th e board level
physical implementation of how the pins of the function should be connected.
NC7SV57 • NC7SV58
FIGURE 6. 2-Input NAND Gate FIGURE 7. 2-Input AND with Inverted A Input
FIGURE 8. 2-Input AND with Inverted B Input FIGURE 9. 2-Input OR Gate
FIGURE 10. 2-Input XOR Gate
www.fairchildsemi.com 4
Loading...