Fairchild Semiconductor MM74HC393N, MM74HC393SJ, MM74HC393SJX, MM74HC393CW, MM74HC393M Datasheet

September 1983
Revised February 1999

MM74HC393 Dual 4-Bit Binary Counter

© 1999 Fairchild Semiconductor Corporation DS005337.prf www.fairchildsemi.com

MM74HC393
Dual 4-Bit Binary Counter

General Description

The MM74HC393 counter ci rcui ts contain indep endent rip­ple carry counters and utilize advanced silicon-gate CMOS
technology. The MM74HC393 contains two 4-bit ripple
carry binary counters, which ca n be cascaded to create a
single divide-by-256 counter.

Each of the two 4-bit counters is incremented on the HIGH­to-LOW transition (negati ve edge) of the clock input, and
each has an independ ent clear input. When clear is set
HIGH all four bits of each counter are set to a low level.
This enables count truncation a nd allows t he implem enta­tion of divide-by-N counter configurations.

Each of the counters outputs can drive 10 low power
Schottky TTL equivalent lo ads. This count er is functio nally

as well as pin equivalent to the 74LS393. All inputs are pro­tected from damage due t o static discharge by diodes to
V

CC

and ground.

Features

■ Typical operating frequency: 50 MHz

■ Typical propagation delay: 13 ns (Ck to Q

A

)

■ Wide operating supply voltage range: 2–6V

■ Low input current: <1 µA

■ Low quiescent suppl y current: 80 µA maximum (74HC

Series)

■ Fanout of 10 LS-TTL loads

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering cod e.

Connection Diagram

Pin Assignments for DIP, SOIC, SOP and TSSOP

Top View

Order Number Package Number Package Description

MM74HC393M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74HC393SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC393MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC393N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

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MM74HC393

Absolute Maximum Ratings

(Note 2)
(Note 1)

Recommended Operating
Conditions

Note 1: Absolute Maximum Ratings are those values beyond which dam-

age to the device may occur.

Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temper ature dera ting — plas tic “N” packa ge: −

12 mW/°C from 65 °C to 85°C.

DC Electrical Characteristics (Note 4)

Note 4: For a power supply of 5V ±1 0% the worst c ase ou tput volta ges (VOH, and VOL) occur for HC at 4.5V. Thus the 4. 5V valu es shoul d be use d when

designing with this supply. Worst case V

IH

and VIL occur at V

CC

= 5.5V and 4.5V res pectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage c ur-

rent (I

IN

, ICC, and IOZ) occur for CMOS at the higher voltage and so th e 6. 0V values should be used.

Supply Voltage (VCC) −0.5 to +7.0V
DC Input Voltage (V

IN

) −1.5 to V

CC

+1.5V

DC Output Voltage (V

OUT

) −0.5 to V

CC

+0.5V

Clamp Diode Current (I

IK

, IOK) ±20 mA

DC Output Current, per pin (I

OUT

) ±25 mA

DC V

CC

or GND Current, per pin (ICC) ±50 mA

Storage Temperature Range (T

STG

) −65°C to +150°C

Power Dissipation (P

D

)
(Note 3) 600 mW
S.O. Package only 500 mW

Lead Temperature (T

L

)
(Soldering 10 seconds) 260°C

Min Max Units

Supply Voltage (V

CC

)26V

DC Input or Output Voltage

(V

IN

, V

OUT

)0V

CC

V

Operating Temperature Range (T

A

) −40 +85 °C

Input Rise or Fall Times

(t

r

, tf) V

CC

= 2.0V 1000 ns

V

CC

= 4.5V 500 ns

V

CC

= 6.0V 400 ns

Symbol Parameter Conditions

V

CC

TA = 25°CTA = −40 to 85°CTA = −55 to 125°C

Units

Typ Guaranteed Limits

V

IH

Minimum HIGH Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V

6.0V 4.2 4.2 4.2 V

V

IL

Maximum LOW Level 2.0V 0.5 0.5 0.5 V
Input Voltage 4.5V 1.35 1.35 1.35 V

6.0V 1.8 1.8 1.8 V

V

OH

Minimum HIGH Level V

IN

= VIH or V

IL

Output Voltage |I

OUT

| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V

4.5V 4.5 4.4 4.4 4.4 V

6.0V 6.0 5.9 5.9 5.9 V

V

IN

= VIH or V

IL

|I

OUT

| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V

|I

OUT

| ≤ 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V

V

OL

Maximum LOW Level V

IN

= VIH or V

IL

Output Voltage |I

OUT

| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V

4.5V 0 0.1 0.1 0.1 V

6.0V 0 0.1 0.1 0.1 V

V

IN

= VIH or V

IL

|I

OUT

| ≤ 4.0 mA 4.5V 0.2 0.26 0.33 0.4 V

|I

OUT

| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V

I

IN

Maximum Input V

IN

= VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA

Current

I

CC

Maximum Quiescent V

IN

= VCC or GND 6.0V 8.0 80 160 µA

Supply Current I

OUT

= 0 µA

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MM74HC393

AC Electrical Characteristics

V

CC

= 5V, T

A

= 25°C, C

L

= 15 pF, tr = t

f

= 6 ns

AC Electrical Characteristics

C

L

= 50 pF, tr = t

f

= 6 ns (unless otherwise specified)

Note 5: CPD determines the no load dynamic power con s um ption, PD = CPD V

CC

2

f + ICC VCC, and the no load dynam ic cu rrent consumption,

I

S

= CPD VCCf + ICC.

Symbol Parameter Conditions Typ

Guaranteed

Limit

Units

f

MAX

Maximum Operating Frequency 50 30 MHz

t

PHL

, t

PLH

Maximum Propagation Delay, Clock A to Q

A

13 20 ns

t

PHL

, t

PLH

Maximum Propagation Delay, Clock A to Q

B

19 35 ns

t

PHL

, t

PLH

Maximum Propagation Delay, Clock A to Q

C

23 42 ns

t

PHL

, t

PLH

Maximum Propagation Delay, Clock A to Q

D

27 50 ns

t

PHL

Maximum Propagation Delay, Clear to any Q 15 28 ns

t

REM

Minimum Removal Time −25ns

t

W

Minimum Pulse Width Clear or Clock 10 16 ns

Symbol Parameter Conditions

V

CC

TA = 25°CTA = −40 to 85°CTA = −55 to 125°C

Units

Typ Guaranteed Limits

f

MAX

Maximum Operating 2.0V 5 4 3
Frequency 4.5V 27 21 18 MHz

6.0V 31 24 20 MHz

t

PHL

, t

PLH

Maximum Propagation 2.0V 45 120 150 180 ns
Delay Clock A to Q

A

4.5V 15 24 30 35 ns

6.0V 13 21 26 31 ns

t

PHL

, t

PLH

Maximum Propagation 2.0V 68 190 240 285 ns
Delay Clock A to Q

B

4.5V 23 38 47 57 ns

6.0V 20 32 40 48 ns

t

PHL

, t

PLH

Maximum Propagation 2.0V 90 240 300 360 ns
Delay Clock A to Q

C

4.5V 30 48 60 72 ns

6.0V 26 41 51 61 ns

t

PHL

, t

PLH

Maximum Propagation Delay 2.0V 100 290 360 430 ns
Clock to Q

D

4.5V 35 58 72 87 ns

6.0V 30 50 62 75 ns

t

PHL

Maximum Propagation 2.0V 54 165 210 250 ns
Delay Clear to any Q 4.5V 18 33 41 49 ns

6.0V 15 28 35 42 ns

t

REM

Minimum Clear 2.0V 25 25 25 ns
Removal Time 4.5V 5 5 5 ns

6.0V 5 5 5 ns

t

W

Minimum Pulse Width 2.0V 30 80 100 120 ns
Clear or Clock 4.5V 10 16 20 24 ns

6.0V 9 14 18 20 ns

t

THL

, t

TLH

Maximum Output 2.0V 30 75 95 110 ns
Rise and Fall Time 4.5V 8 15 19 22 ns

6.0V 7 13 16 19 ns

tr, t

f

Maximum Input 1000 1000 1000 ns
Rise and Fall Time 500 500 500 ns

400 400 400 ns

C

PD

Power Dissipation (per counter) 42 pF
Capacitance (Note 5)

C

IN

Maximum Input Capacitance 5 10 10 10 pF