Fairchild Semiconductor HUF76131SK8 Datasheet

Data Sheet January 2003

HUF76131SK8

10A, 30V, 0.013 Ohm, N-Channel, Logic
Level UltraFET Power MOSFET

This N-Channel powe r MOSFET is

®

manufac tured using the innovative
UltraFET process. This advanced

process technology achieves the
lowest possible on-resistance per silicon area, resulting in
outstanding performance. This device is capab le of
withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in appli cations where power
efficiency is important, such as switching regulators,
switchi ng converters, motor drivers, relay drivers , low­voltage bus switches, and power manage me nt i n po rtab le
and battery-operated products.

Formerly developmental ty pe TA76131.

Ordering Information

PART NUMBER PACKAGE BRAND

HUF76131SK8 MS-012AA 76131SK8

NOTE: When ordering, use the e ntire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF76131SK8T.

Features

• Logic Level Gate Drive

• 10A, 30V

• Ultra Low On-Resistance, r

• Temperatur e Compensating PSPICE

DS(ON)

= 0.013Ω

®

Model

• Thermal Impedance SPICE Model

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

• Related Literature

- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”

Symbol

SOURCE(1)

SOURCE(2)

SOURCE(3)

DRAIN(8)

DRAIN(7)

DRAIN(6)

Packaging

JEDEC MS-012AA

BRANDING DASH

1

2

GATE(4)

5

3

4

DRAIN(5)

©2003 Fairchild Semiconductor Corporation HUF76131SK8 Rev. B1

HUF76131SK8

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

A

HUF76131SK8 UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gat e Voltage (R

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

GS

Drain Curr e nt

Continuous (Figure 2) (Notes 2, 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

CAUTION: Stresses above those listed in “Absolute Maximum Rati ngs” may cause permane nt damage to the device. This is a stress only rating and oper ation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

DSS

DGR

GS

D

DM

AS

D

, T

J

STG

L

pkg

30 V
30 V

±20 V

10

Figure 5

Figure 6

2.5

0.02

-55 to 150

300
260

A

W

W/oC

o

C

o

C

o

C

NOTE:

= 25oC to 150oC.

1. T

J

Electrical Specifications T

= 25oC, Un less Othe rwise Specified

A

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain t o Source Breakdown Voltage BV
Gate to Source Threshold Voltage V

GS(TH)VGS

Zero Gat e V ol tag e D rain Current I

Gate to Sour c e Le ak ag e C urr e nt I
Drain to Source On Resistance r

DS(ON)ID

Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t
Total Gate Charg e Q

g(TOT)VGS

Gate Charge at 5V Q
Threshold Gate Ch ar g e Q
Gate to Source Gate Charg e Q
Gate to Drai n “M ill er ” C ha r ge Q
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance Junction to Ambient R

DSSID

DSS

GSS

ON

r

f

OFF

g(5)

g(TH)

gs

gd

ISS
OSS
RSS

θJA

= 250µA, VGS = 0V (Figure 11) 30 - - V

= VDS, ID = 250µA (Figure 10) 1 - - V

VDS = 25V, VGS = 0V - - 1 µA

= 25V, VGS = 0V, TA = 150oC - - 250 µA

V

DS

VGS = ±20V - - ±100 nA

= 10A, VGS = 4.5V (Figures 9,14) - 0.017 0.018 Ω
= 10A, VGS = 5V - 0.015 0.017 Ω

I

D

= 10A, VGS = 10V - 0.011 0.013 Ω

I

D

VDD = 15V, ID ≅ 10 A , RL = 1.5Ω, VGS = 5V,
R

= 6.8Ω

GS

(Figur e 15 )

- - 115 ns

-15-ns

-61-ns

-33-ns

-36-ns

- - 105 ns

= 0V to 10V VDD = 15V, ID ≅ 10A,

R

=1.5Ω, I

VGS = 0V to 5V - 22 26 nC
VGS = 0V to 1V - 1.53 1.85 nC

L

(Figur e 13 )

g(REF)

= 1.0mA

-3947nC

-4.00- nC

-9.50- nC

VDS = 25V, VGS = 0V, f = 1MHz
(Figur e 12 )

-1605- pF

-685- pF

-115- pF

Pad Area = 0.76 in2 (Note 2) - - 50

2

Pad Area = 0.054 in
Pad Area = 0.0115 in

(See TB 377) - - 143.4oC/W

2

(See TB37 7) - - 17 7.3oC/W

o

C/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Vol tage V

SD

Reverse Recovery Time t
Reverse Recovered Charge Q

RR

NOTES:

o

C/W measured using FR-4 board with 0.76 in2 footprint at 10 seconds.

2. 50

3. 177.3

©2003 Fairchild Semiconductor Corporation HUF76131SK8 Rev. B1

o

C/W measured using FR-4 board with 0.0115 in2 footprint at 1000 seconds.

ISD = 10A - - 1.25 V

= 2.3A - - 1.1 V

I

SD

ISD = 2.3A, dISD/dt = 100A/µs--57ns

rr

ISD = 2.3A, dISD/dt = 100A/µs--81nC

Typical Performance Curves

HUF76131SK8

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

125

TA, AMBIENT TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT

TEMPERATURE

10

DUTY CYCLE - DESCENDING ORDER

0.5

0.2

0.1

1

0.05

0.02

0.01

0.1

, NORMALIZED

JA

θ

Z

0.01

THERMAL IMPEDANCE

0.001

-5

10

-4

10

SINGLE PULSE

-3

10

-2

10

t, RECTANGULAR PULSE DURATION (s)

12

10

8

6

4

, DRAIN CURRENT (A)

D

I

2

0

25 50 75 100 125 150

TA, AMBIENT TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

AMBIENT TEMPERATURE

P

DM

t

1

t

JA

1/t2

x R

10

2

+ T

JA

θ

2

10

NOTES:
DUTY FACTOR: D = t

PEAK TJ = PDM x Z

-1

10

0

1

10

θ

A

3

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

500

TJ = MAX RATED
T

= 25oC

A

100

100µs

OPERATION IN THIS

10

, DRAIN CURRENT (A)

D

I

AREA MAY BE
LIMITED BY r

1

DS(ON)

V

DSS(MAX)

= 30V

10 1001

V

, DRAIN TO SOURCE VOLT AGE (V)

DS

1ms

10ms

1000

100

VGS = 5V

FOR TEMPERATURE S
ABOVE 25

10

, PEAK CURRENT (A)

CURRENT AS FOLLOWS:

DM

I

I = I

25

1

-5

10

10

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

o

C DERATE PEAK

150 - T

A

125

-4

-3

10

t, PULSE WIDTH (s)

TA = 25oC

-2

10

10

-1

10

0

10

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

©2003 Fairchild Semiconductor Corporation HUF76131SK8 Rev. B1

1