Fairchild Semiconductor HUF76121P3, HUF76121S3S Datasheet

HUF76121P3, HUF76121S3S

Data Sheet January 2003

47A, 30V, 0.021 Ohm, N-Channel, Logic
Level UltraFET Power MOSFETs

These N-Channel pow er MOSFETs
are manufactured using the
innovati ve UltraFET™ process.

This advanced process technology
achieves the lowest possible on-resistance per silicon ar ea,
resultin g in outstanding performance. This device is capab le
of withstanding hi gh energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was design ed for use in applicati ons where power
efficiency is important, such as switching regulators,
switchi ng converters, motor drivers, relay drivers , low­voltage bus switches, and power manage me nt i n po rtab le
and battery-operated products.

Formerly developmental ty pe TA76121.

Ordering Information

PART NUMBER PACKAGE BRAND

HUF76121P3 TO-220AB 76121P
HUF76121S3S TO-263AB 76121S

NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-263AB variant in tape and reel, e.g., HUF76121S3ST.

Features

• Logic Level Gate Drive

• 47A, 30V

• Ultra Low On-Resistance, r

• Temperatur e Compensating PSPICE

• Temperatur e Compensating SABER

DS(ON)

= 0.021Ω

®

Model

©

Model

• Thermal Impedance SPICE Model

• Thermal Impedance SABER Model

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

• Related Literature

- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”

Symbol

D

G

S

Packaging

DRAIN

(FLANGE)

JEDEC TO-220AB JEDEC TO-263AB

SOURCE

DRAIN

GATE

GATE

SOURCE

(FLANGE)

DRAIN

©2003 Fairchild Semiconductor Corporation HUF76121P3, HUF76121S3S Rev. C1

HUF76121P3, HUF76121S3S

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gat e Voltage (R

= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

GS

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

DSS

DGR

GS

30 V
30 V

±20 V

Drain Curr e nt

Continuous (T

Continuous (TC = 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

= 25oC, VGS = 10V) (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

C

Continuous (TC = 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

, T

J

STG

D
D
D

DM

AS

D

47
25
24

Figure 4

Figures 6, 17,18

75

0.6

-40 to 150

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

CAUTION: Stresses above those listed in “Absolute Maximum Rati ngs” may cause permane nt damage to the device. This is a stress only rating and oper ation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

300
260

A
A
A

W

W/oC

o

C

o

C

o

C

NOTE:

= 25oC to 150oC.

1. T

J

Electrical Specifications T

= 25oC, Unless Otherwise Specified

A

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

OFF STATE SPECIFICATIONS

Drain t o Source Breakdown Voltage BV
Zero Gat e V ol tag e D rain Curre nt I

Gate to Sour c e Le ak ag e C urr e nt I

ON STATE SPECIFICATIONS

Gate to Source Threshold Voltage V
Drain to Source On Resistance r

GS(TH)VGS

DS(ON)ID

THERMAL SPECIFICATIONS

Thermal R esis ta nc e Ju ncti on to Case R
Thermal Resistance Junction to Ambient R
SWITCHING SPECIFICATIONS (V

GS

= 4.5V)
Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t

DSSID

DSS

GSS

θJC

θJA

ON

r

f

OFF

= 250µA, VGS = 0V (Figure 12) 30 - - V
VDS = 25V, VGS = 0V - - 1 µA
V

= 25V, VGS = 0V, TC = 150oC--250µA

DS

VGS = ±20V - - ±100 nA

= VDS, ID = 250µA (Figur e 11) 1 - 3 V

= 47A, VGS = 10V (Figures 9, 10) - 0.01 5 0.021 Ω
I

= 25A, VGS = 5V (Figure 9) - 0.019 0.028 Ω

D

I

= 24A, VGS = 4.5V (Figure 9) - 0.021 0.031 Ω

D

(Figur e 3) - - 1. 66
TO-22 0 and TO-263 - - 62

VDD = 15V, ID ≅ 24A, RL = 0.63Ω,
V

= 4.5V, RGS = 10.0Ω

GS

(Figures 15, 21 , 22)

--265ns

-15-ns

o

o

C/W
C/W

-160- ns

-14-ns

-31-ns

--70ns

©2003 Fairchild Semiconductor Corporation HUF76121P3, HUF76121S3S Rev. C1

HUF76121P3, HUF76121S3S

Electrical Specifications T

= 25oC, Unless Otherwise Specified (Continue d)

A

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

SWITCHING SPECIFICATIONS (VGS = 10V)

Turn-On Time t
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t
Turn-Off Time t

GATE CHARGE SPECIFICATIONS

Total Gate Charg e Q
Gate Charge at 5V Q
Threshold Gat e Ch arg e Q
Gate to Source Gate Charg e Q
Gate to Drai n “M ill er ” C ha r ge Q

CAPACITANCE SPECIFICATIONS

ON

d(ON)

d(OFF)

OFF

g(TOT)VGS

g(5)

g(TH)

VDD = 15V, ID ≅ 47A, RL = 0.32Ω,
V
(Figures 16, 21 , 22)

r

f

VGS = 0V to 5V - 13 16 nC
VGS = 0V to 1V - 1.0 1.2 nC

gs

gd

= 10V, RGS = 12.5Ω

GS

= 0V to 10V VDD = 15V, ID ≅ 25A,

R

= 0.6Ω

L

I

= 1.0mA

g(REF)

(Figures 14, 1 9, 20)

--80ns

-6-ns

-47-ns

-47-ns

-42-ns

--135ns

-2430nC

-2.50- nC

-7.80- nC

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C

ISS

OSS

RSS

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Vol tage V
Reverse Recovery Time t
Reverse Recovered Charge Q

SD

rr

RR

Typical Performance Curves

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

TA, AMBIENT TEMPERATURE (oC)

FIGURE 1. NORMALIZED PO WER DISSIPATION vs CASE

TEMPERATURE

125

VDS = 25V, VGS = 0V, f = 1MHz

-850- pF

(Figur e 13 )

-465- pF

-100- pF

ISD = 25A - - 1.25 V
ISD = 25A, dISD/dt = 100A/µs--65ns
ISD = 25A, dISD/dt = 100A/µs - - 100 nC

50

40

30

VGS = 4.5V

20

, DRAIN CURRENT (A)

D

I

10

0

25

50 75 100 125 150

TC, CASE TEMPERATURE (oC)

VGS = 10V

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

©2003 Fairchild Semiconductor Corporation HUF76121P3, HUF76121S3S Rev. C1

HUF76121P3, HUF76121S3S

Typical Performance Curves (Continued)

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

θJC

Z

THERMAL IMPEDANCE

SINGLE PULSE

0.01

-5

10

-4

10

-3

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

-2

10

t, RECT ANGULAR PULSE DURATION (s)

NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z

-1

10

P

DM

t

1

t

2

1/t2

x R

JC

θ

10

+ T

JC

C

θ

0

1

10

, PEAK CURRENT (A)

DM

I

1000

100

1000

100

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

40

-5

10

VGS = 10V

VGS = 5V

-4

10

-3

10

10

-2

t, PULSE WIDTH (s)

FIGURE 4. PEAK CURRENT CAPABILITY

TJ = MAX RATED

= 25oC

T

C

100µs

500

100

TC = 25oC

FOR TEMPERATURES
ABOVE 25
CURRENT AS FOLLOWS:

-1

10

If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0
t

= (L/R) ln [ (IAS*R)/(1.3*RATED BV

AV

o

C DERATE PEAK

25

0

10

- VDD)

DSS

150 - T

125

- VDD) +1]

I = I

DSS

STARTING TJ = 25oC

C

1

10

10

10

, DRAIN CURRENT (A)

D

I

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

1

1 10 100

DS(ON)

, DRAIN TO SOURCE VOLTAGE (V)

V

DS

BV

DSS MAX

= 30V

1ms

10ms

, AVALANCHE CURRENT (A)
I

STARTING TJ = 150oC

AS

1

0.001 0.01 0.1 1 10 100
tAV, TIME IN AVALANCHE (ms)

NO TE: Refer to Fairchild App lication Notes AN9321 and AN9322.

FIGURE 5. FORWARD BIAS SAFE OPERATING AREA

©2003 Fairchild Semiconductor Corporation HUF76121P3, HUF76121S3S Rev. C1

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABIL ITY