Fairchild Semiconductor HUF76113SK8 Datasheet

Data Sheet January 2003

HUF76113SK8

6.5A, 30V, 0.030 Ohm, N-Channel, Logic
Level UltraFET Power MOSFET

This N-Channel powe r MOSFET i s
manufactured using the innovative
UltraFET™ process. This advanced

process technology achieves the
lowest possible on-resistance per silicon area, resulting in
outstanding performance. This device is capable of
withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators, switching
converters, motor drivers, relay drivers, low-voltage bus
switches, and power management in portable and battery­operated products.

Formerly developmental ty pe TA76113.

Ordering Information

PART NUMBER PACKAGE BRAND

HUF76113SK8 MS-012AA 76113SK8

NOTE: When ordering, use the e ntire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF76113SK8T.

Features

• Logic Level Gate Drive

• 6.5A, 30V

• Ultra Low On-Resistance, r

• Temperatur e Compensating PSPICE

DS(ON)

= 0.030Ω

®

Model

• Temperatur e Com pensating SABER™ Model

• Thermal Impedance SPICE Model

• Thermal Impedance SABER Model

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

• Related Literature

- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”

Symbol

NC(1)

SOURCE(2)

DRAIN(8)

DRAIN(7)

Packaging

JEDEC MS-012AA

BRANDING DASH

1

2

SOURCE(3)

GATE(4)

5

3

4

DRAIN(6)

DRAIN(5)

©2003 Fairchild Semiconductor Corporation HUF76113SK8 Rev. B1

HUF76113SK8

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

A

HUF76113SK8 UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (R

= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

GS

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

DSS

DGR

GS

30 V
30 V

±20 V

Drain Current

Continuous (T

Continuous (TA= 100oC, VGS = 5V) (Note 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

= 25oC, VGS = 10V) (Figure 2) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . I

A

Continuous (TA= 100oC, VGS = 4.5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

ASB

Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

, T

J

STG

D
D
D

DM

D

6.5

2.0

2.0

Figure 4

Figure 6

2.5
20

-55 to 150

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

Package Body for 10s, See Te chbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

CAUTION: Stresses above those listed in “Absolute Maximum Rati ngs” may cause permane nt damage to the device. This is a stress only rating and oper ation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

300
260

A
A
A

W

mW/oC

o

C

o

C

o

C

NOTES:

= 25oC to 125oC.

1. T

J

o

C/W measured using FR-4 board with 0.76 in2 footprint at 10 seconds.

2. 50

o

C/W measured using FR-4 board with 0.0115 in2 footprint at 10 00 sec on ds .

3. 177

Electrical Specifications T

= 25oC, Unless Otherwise Specified

A

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

OFF STATE SPECIFICATIONS

Drain t o Source Breakdown Voltage BV
Zero Gat e V ol tag e D rain Current I

Gate to Sour c e Le ak ag e C urr e nt I

ON STATE SPECIFICATIONS

Gate to Source Threshold Voltage V
Drain to Source On Resistance r

THERMAL SPECIFICATIONS

Thermal Resistance Junction to Ambient R

SWITCHING SPECIFICATIONS (V

GS

= 4.5V)
Turn-On Time t
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t
Turn-Off Time t

DSSID

DSS

VDS = 25V, VGS = 0V - - 1 µA
V

GSS

GS(TH)VGS

DS(ON)ID

VGS = ±20V - - ±100 nA

I

D

ID = 2.0A, VGS = 4.5V (Fi gure 9) - 0.03 3 0.041 Ω

θJA

Pad Area = 0.76 in2 (Note 2) - - 50
Pad Area = 0.054 in2 (See TB337) - - 143
Pad Area = 0.0115 in

ON

d(ON)

d(OFF)

OFF

VDD = 15V, ID ≅ 2.0A, RL = 7.5Ω,
V
(Figur e 15 )

r

f

= 250µA, VGS = 0V (Figure 12) 30 - - V

= 25V, VGS = 0V, TA = 150oC--250µA

DS

= VDS, ID = 250µA (Figur e 11) 1 - 3 V
= 6.5A, VGS = 10V (Figures 9, 10) - 0.025 0.03 0 Ω
= 2.0A, VGS = 5V (Figure 9) - 0.03 1 0.038 Ω

o
o

2

(See TB 337) - - 177

o

--100ns

= 4.5V, RGS = 15Ω

GS

-16-ns

-50-ns

-28-ns

-34-ns

--91ns

C/W
C/W
C/W

©2003 Fairchild Semiconductor Corporation HUF76113SK8 Rev. B1

HUF76113SK8

Electrical Specifications T

= 25oC, Unless Otherwise Specified

A

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

SWITCHING SPECIFICATIONS (VGS = 10V)

Turn-On Time t
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t
Turn-Off Time t

GATE CHARGE SPECIFICATIONS

Total Gate Charg e Q
Gate Charge at 5V Q
Threshold Gate Ch arg e Q
Gate to Source Gate Charg e Q
Gate to Drai n “M ill er ” C ha r ge Q

CAPACITANCE SPECIFICATIONS

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C

ON

d(ON)

d(OFF)

OFF

g(TOT)VGS

g(5)

g(TH)

ISS
OSS
RSS

VDD = 15V, ID ≅ 6.5A, RL = 2.31Ω,
V
(Figur e 16 )

r

f

VGS = 0V to 5V - 10 12 nC
VGS = 0V to 1V - 0.65 0.78 nC

gs

gd

VDS = 25V, VGS = 0V, f = 1MHz
(Figur e 13 )

= 10V, RGS = 16Ω

GS

= 0V to 10V VDD = 15V, ID ≅ 2.0A,

R

= 7.5Ω

L

I

= 1.0mA

g(REF)

(Figures 14)

--59ns

-6.5-ns

-33-ns

-45-ns

-40 -ns

--126ns

-17.521nC

-1.10- nC

-5.40- nC

-585- pF

-327- pF

-73-pF

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Vol tage V

Reverse Recovery Time t
Reverse Recovered Charge Q

Typical Performance Curves

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

TA, AMBIENT TEMPERATURE (oC)

SD

rr

RR

ISD =6.5A - - 1.25 V

= 2.0A 1.10 V

I

SD

ISD = 2.0A, dISD/dt = 100A/µs--47ns
ISD = 2.0A, dISD/dt = 100A/µs--52nC

8

V

125

= 10V, R

JA

θ

GS

= 177oC/W

6

4

V

= 4.5V, R

GS

, DRAIN CURRENT (A)

2

D

I

0

25 50 75 100 125

TA, AMBIENT TEMPERATURE (oC)

JA

θ

= 50oC/W

150

FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT

TEMPERATURE

©2003 Fairchild Semiconductor Corporation HUF76113SK8 Rev. B1

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

AMBIENT TEMPERATURE

Typical Performance Curves (Continued)

10

DUTY CYCLE - DESCENDING ORDER

0.5

0.2

0.1

1

0.05

0.02

0.01

0.1

, NORMALIZED

JA

θ

Z

0.01

THERMAL IMPEDANCE

0.001

500

100

-5

10

VGS = 10V

-4

10

VGS = 5V

SINGLE PULSE

-3

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

HUF76113SK8

-2

10

-1

10

t, RECTANGULAR PULSE DURATION (s)

0

10

P

NOTES:
DUTY FACTOR: D = t

PEAK TJ = PDM x Z

1

10

TC = 25oC

FOR TEMPERATURE S
ABOVE 25

o

C DERATE PEAK

CURRENT AS FOLLOWS:

I = I

25

R

JA

θ

DM

1/t2

x R

JA

θ

10

150 - T

125

= 50oC/W

t

1

t

2

+ T

JA

θ

2

A

A

3

10

10

, PEAK CURRENT (A)

TRANSCONDUCTANCE
MAY LIMIT CURRENT

DM

I

IN THIS REGION

1

-5

10

-4

10

-3

10

FIGURE 4. PEAK CURRENT CAPABILITY

500

100

10

, DRAIN CURRENT (A)

D

I

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

1

DS(ON)

V

DSS(MAX)

10

, DRAIN TO SOURCE VOLTAGE (V)

V

DS

TJ = MAX RATED

= 25oC

T

A

100µs

1ms

10ms

= 30V

FIGURE 5. FORWARD BIAS SAFE OPERATING AREA

-2

10

t, PULSE WIDTH (s)

1001

R

= 50oC/W

JA

θ

10

-1

100

10

0

10

If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0
t

= (L/R)ln[(IAS*R)/(1.3*RATED BV

AV

1

10

2

10

- VDD)

DSS

- VDD) +1]

DSS

STARTING TJ = 25oC

STARTING TJ = 150oC

, AVALANCHE CURRENT (A)

AS

I

1

0.01

0.1

1 10 100

tAV, TIME IN AVALANCHE (ms)

NO TE: Refer to Fairchild Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING

CAPABILITY

3

10

©2003 Fairchild Semiconductor Corporation HUF76113SK8 Rev. B1