Fairchild Semiconductor HUF76113DK8 Datasheet

Data Sheet January 2003

HUF76113DK8

6A, 30V, 0.032 Ohm, Dual N-Channel,
Logic Level UltraFET Power MOSFET

This N-Channel powe r MOSFET i s

®

manufactured using the innovative
UltraFET process. This advanced

process technology achieves the
lowest possible on-resistance per silicon area, resulting in
outstanding performance. This device is capable of
withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators, switching
converters, motor drivers, relay drivers, low-voltage bus
switches, and power management in portable and battery­operated products.

Formerly developmental ty pe TA76113.

Ordering Information

PART NUMBER PACKAGE BRAND

HUF76113DK8 MS-012AA 76113DK8

NOTE: When ordering, use the e ntire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF76113DK8T.

Features

• Logic Level Gate Drive

• 6A, 30V

• Ultra Low On-Resistance, r

• Temperatur e Compensating PSPICE

• Temperatur e Compensating SABER

DS(ON)

= 0.032Ω

®

Model

™

Model

• Thermal Impedance SPICE Model

• Thermal Impedance SABER Model

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

• Related Literature

- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”

Symbol

D1(8)
D1(7)

S1(1)

G1(2)

Packaging

JEDEC MS-012AA

BRANDING DASH

1

2

D2(6)
D2(5)

S2(3)

G2(4)

5

3

4

©2003 Fairchild Semiconductor Corporation HUF76113DK8 Rev. B1

HUF76113DK8

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

A

HUF76113DK8 UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (R

= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

GS

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

DSS

DGR

GS

30 V
30 V

±20 V

Drain Current

Continuous (T

Continuous (TA= 100oC, VGS = 5V) (Note 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

= 25oC, VGS = 10V) (Figure 2) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . I

A

Continuous (TA= 100oC, VGS = 4.5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

, T

J

STG

D
D
D

DM

AS

D

6

1.8

1.7

Figure 4

Figure 6

2.5

0.02

-55 to 150

Maximum Temperat ure for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

CAUTION: Stresses above those listed in “Absolute Maximum Rati ngs” may cause permane nt damage to the device. This is a stress only rating and oper ation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

300
260

A
A
A

W

W/oC

o

C

o

C

o

C

NOTES:

= 25oC to 125oC.

1. T

J

2. 50oC/W measured using FR-4 board at 1 second.

o

C/W measured using FR-4 board with 0.006 in2 footprint at 1000 seconds.

3. 228

Electrical Specifications T

= 25oC, Unless Othe rw is e Spec ifi ed

A

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

OFF STATE SPECIFICATIONS

Drain t o Source Breakdown Voltage BV
Zero Gat e V ol tag e D rain Current I

Gate to Sour c e Le ak ag e C urr e nt I

ON STATE SPECIFICATIONS

Gate to Source Threshold Voltage V
Drain to Source On Resistance r

GS(TH)VGS

DS(ON)ID

THERMAL SPECIFICATIONS

Thermal Resistance Junction to Ambient R

SWITCHING SPECIFICATIONS (V

GS

= 4.5V)
Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t

DSSID

DSS

GSS

θJA

ON

r

f

OFF

= 250µA, VGS = 0V (Figure 12) 30 - - V
VDS = 25V, VGS = 0V - - 1 µA
V

= 25V, VGS = 0V, TC = 150oC--250µA

DS

VGS = ±20V - - ±100 nA

= VDS, ID = 250µA (Figure 11) 1 - 3 V

= 6A, VGS = 10V (Figures 9, 10) - 0.026 0.032 Ω
I

= 1.8A, VGS = 5V (Figure 9) - 0.033 0.041 Ω

D

I

= 1.7A, VGS = 4.5V (F igure 9) - 0.035 0.043 Ω

D

Pad Area = 0.76 in2 (Note 2) - - 50
Pad Area = 0.027 in
Pad Area = 0.006 in

VDD = 15V, ID ≅ 1.7A, RL = 8.8Ω,
V

= 4.5V, RGS = 18Ω,

GS

(Figure 15)

2

(See TB 377) - - 191

2

(See TB 377) - - 228

--110ns

-17-ns

o
o
o

C/W
C/W
C/W

-57-ns

-32-ns

-38-ns

--105ns

©2003 Fairchild Semiconductor Corporation HUF76113DK8 Rev. B1

HUF76113DK8

Electrical Specifications T

= 25oC, Unless Othe rw is e Spec ifi ed

A

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

SWITCHING SPECIFICATIONS (VGS = 10V)

Turn-On Time t
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t
Turn-Off Time t

GATE CHARGE SPECIFICATIONS

Total Gate Charg e Q
Gate Charge at 5V Q
Threshold Gate Ch ar g e Q
Gate to Source Gate Charg e Q
Gate to Drai n “M ill er ” C ha r ge Q

CAPACITANCE SPECIFICATIONS

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C

ON

d(ON)

d(OFF)

OFF

g(TOT)VGS

g(5)

g(TH)

ISS
OSS
RSS

VDD = 15V, ID ≅ 6A, RL = 2.5Ω, VGS =
10V,
R
(Figure 16)

r

f

VGS = 0V to 5V - 8.4 10.2 nC
VGS = 0V to 1V - 0.55 0.66 nC

gs
gd

VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 13)

= 18Ω

GS

= 0V to 10V VDD = 15V, ID ≅ 1.8A,

R

= 8.3Ω

L

I

= 1.0mA

g(REF)

(Figure 14)

- - 60 ns

-6.5-ns

-33-ns

-50-ns

- 40 - ns

--135ns

- 16.0 19.2 nC

-1.50- nC

-3.90- nC

-605- pF

-275- pF

-40-pF

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Vol tage V

Reverse Recovery Time t
Reverse Recovered Charge Q

Typical Performance Curves

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

TA, AMBIENT TEMPERATURE (oC)

SD

rr

RR

ISD = 6A - - 1.25 V

= 1.8A 1.00 V

I

SD

ISD = 1.8A, dISD/dt = 100A/µs--40ns
ISD = 1.8A, dISD/dt = 100A/µs--42nC

7

125

6

5

4

3

2

, DRAIN CURRENT (A)

D

I

V

= 4.5V, R

GS

1

0

25 50 75 100 125 150

= 228oC/W

JA

θ

TA, AMBIENT TEMPERATURE (oC)

V

GS

= 10V , R

JA

θ

= 50oC/W

FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT

TEMPERATURE

©2003 Fairchild Semiconductor Corporation HUF76113DK8 Rev. B1

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

AMBIENT TEMPERATURE

Typical Performance Curves (Continued)

2

DUTY CYCLE - DESCENDING ORDER

1

0.5

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

JA

θ

0.01

Z

THERMAL IMPEDANCE

SINGLE PULSE

0.001

-5

10

10

-4

-3

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

HUF76113DK8

-2

10

t, RECTANGULAR PULSE DURATION (s)

-1

10

0

10

P

NOTES:
DUTY FACTOR: D = t

PEAK TJ = PDM x Z

1

10

R

= 228oC/W

JA

θ

DM

t

1

t

2

1/t2

x R

JA

θ

+ T

JA

A

θ

2

10

3

10

500

100

10

, PEAK CURRENT (A)

DM

I

1

10

500

100

OPERATION IN THIS

10

AREA MAY BE
LIMITED BY r

, DRAIN CURRENT (A)

D

I

VGS = 10V

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

-5

DS(ON)

-4

10

VGS = 5V

-3

10

-2

10

-1

10

t, PULSE WIDTH (s)

FIGURE 4. PEAK CURRENT CAPABILITY

50

TJ = MAX RATED

T

= 25oC

A

100µs

10

1ms

STARTING TJ = 150oC

, AVALANCHE CURRENT (A)

10ms

I

AS

R

= 228oC/W

JA

θ

0

10

If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0

= (L/R)ln[(IAS*R)/(1.3*RATED BV

t

AV

1

10

STARTING TJ = 25oC

TC = 25oC

FOR TEMPERATURES
ABOVE 25

o

C DERATE PEAK

CURRENT AS FOLLOWS:

150 - T

I = I

25

A

125

2

10

- VDD)

DSS

DSS

3

10

- VDD) +1]

V

1

, DRAIN TO SOURCE VOLTAGE (V)

V

DS

DSS(MAX)

FIGURE 5. FORWARD BIAS SAFE OPERATING AREA

= 30V

10 1001

1

0.1

1 10 100

tAV, TIME IN AVALANCHE (ms)

NO TE: Refer to Fairchild Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING

CAPABILITY

©2003 Fairchild Semiconductor Corporation HUF76113DK8 Rev. B1