Fairchild Semiconductor HUF76105DK8 Datasheet
Data Sheet January 2003
HUF76105DK8
5A, 30V, 0.050 Ohm, Dual N-Channel,
Logic Level UltraFET Power MOSFET
This N-Channel powe r MOSFET i s
®
manufactured using the innovative
UltraFET™ process. This advanced
process technology achieves the
lowest possible on-resistance per silicon area, resulting in
outstanding performance. This device is capable of
withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators, switching
converters, motor drivers, relay drivers, low-voltage bus
switches, and power management in portable and battery
operated products.
Formerly developmental ty pe TA76105.
Ordering Information
PART NUMBER PACKAGE BRAND
HUF76105DK8 MS-012AA 76105DK8
NOTE: When ordering, use the e ntire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF76105DK8T.
Features
• Logic Level Gate Drive
• 5A, 30V
• Ultra Low On-Resistance, r
• Temperatur e Compensating PSPICE
• Temperatur e Compensating SABER
DS(ON)
= 0.050Ω
®
Model
©
Model
• Thermal Impedance SPICE Model
• Thermal Impedance SABER Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D1(8)
D1(7)
S1(1)
G1(2)
Packaging
BRANDING DASH
JEDEC MS-012AA
1
2
3
4
D2(6)
D2(5)
S2(3)
G2(4)
5
©2003 Fairchild Semiconductor Corporation HUF76105DK8 Rev. B1
HUF76105DK8
Absolute Maximum Ratings T
= 25oC, Unless Otherwise Specified
A
HUF76105DK8 UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
Drain to Gat e Voltage (R
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
DGR
GS
30 V
30 V
±20 V
Drain Curr e nt
Continuous (T
= 25oC, VGS = 10V) (Figure 2) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . I
A
Continuous (TA= 100oC, VGS = 5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Continuous (TA= 100oC, VGS = 4.5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E
Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
, T
J
STG
D
D
D
DM
AS
D
5
1.4
1.3
Figure 4
Figures 6, 17, 18
2.5
0.02
-55 to 150
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
CAUTION: Stresses above those listed in “Absolute Maximum Rati ngs” may cause permane nt damage to the device. This is a stress only rating and oper ation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
L
pkg
300
260
A
A
A
W
W/oC
o
C
o
C
o
C
NOTE:
= 25oC to 125oC.
1. T
J
o
C/W measured using FR-4 boa rd at 1 seco nd.
2. 50
o
C/W measured using FR-4 board with 0.006 in2 of copper at 1000 seconds.
3. 228
Electrical Specifications T
= 25oC, Unles s Ot he r wis e Sp ec ifi ed
A
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
OFF STATE SPECIFICATIONS
Drain t o Source Breakdown Voltage BV
Zero Gat e V ol tag e D rain Current I
Gate to Sour c e Le ak ag e C urr e nt I
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage V
Drain to Source On Resistance r
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Ambient R
(V
SWITCHING SPECIFICATIONS
GS
= 4.5V)
Turn-On Time t
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t
Turn-Off Time t
DSSID
DSS
VDS = 25V, VGS = 0V - - 1 µA
V
GSS
GS(TH)VGS
DS(ON)ID
VGS = ±20V - - ±100 nA
I
D
ID = 1.3A, VGS = 4.5V (F igure 9) - 0.060 0.078 Ω
θJA
Pad Area = 0.76 in2 (Note 2) - - 50
Pad Area = 0.027 in2 (See TB 377) - - 1 91
Pad Area = 0.006 in
ON
d(ON)
d(OFF)
OFF
VDD = 15V, ID ≅ 1.3A,
R
R
(Figur e 15 )
r
f
= 250µA, VGS = 0V (Figure 12) 30 - - V
= 25V, VGS = 0V, TC = 150oC--250µA
DS
= VDS, ID = 250µA (Figure 11) 1 - 3 V
= 5A, VGS = 10V (Figures 9, 10) - 0.040 0.050 Ω
= 1.4A, VGS = 5V (Figure 9) - 0.055 0.072 Ω
o
o
2
(See TB 377) - - 2 28
o
--60ns
= 11.5Ω, VGS = 4.5V,
L
GS
= 27Ω
-12-ns
-28-ns
-31-ns
-21-ns
--80ns
C/W
C/W
C/W
©2003 Fairchild Semiconductor Corporation HUF76105DK8 Rev. B1
HUF76105DK8
Electrical Specifications T
= 25oC, Unles s Ot he r wis e Sp ec ifi ed (Continued)
A
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time t
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t
Turn-Off Time t
GATE CHARGE SPECIFICATIONS
Total Gate Charg e Q
Gate Charge at 5V Q
Threshold Gate Ch ar g e Q
Gate to Source Gate Charg e Q
Gate to Drai n “M ill er ” C ha r ge Q
CAPACITANCE SPECIFICATIONS
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
ON
d(ON)
d(OFF)
OFF
g(TOT)VGS
g(5)
g(TH)
ISS
OSS
RSS
VDD = 15V, ID ≅ 5A ,
R
R
(Figur e 16 )
r
f
VGS = 0V to 5V - 5.3 6. 4 nC
VGS = 0V to 1V - 0.35 0.45 nC
gs
gd
VDS = 25V, VGS = 0V,
f = 1MHz
(Figur e 13 )
= 3Ω, VGS = 10V,
L
= 27Ω
GS
= 0V to 10V VDD = 15V, ID ≅ 1.4A,
R
= 10.7Ω
L
I
= 1.0mA
g(REF)
(Figure 14)
--60ns
-17-ns
-21-ns
-60-ns
-20 -ns
--120ns
-911nC
-1.00- nC
-2.40- nC
-325- pF
-180- pF
-35-pF
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Vol tage V
Reverse Recovery Time t
Reverse Recovered Charge Q
Typical Performance Curves
1.2
1.0
0.8
0.6
0.4
0.2
POWER DISSIPATION MULTIPLIER
0
0 25 50 75 100 150
TA, AMBIENT TEMPERATURE (oC)
SD
rr
RR
ISD = 5A - - 1.25 V
= 1.4A 1.00 V
I
SD
ISD = 1.4A, dISD/dt = 100A/µs--39ns
ISD = 1.4A, dISD/dt = 100A/µs--42nC
6
125
5
4
3
2
, DRAIN CURRENT (A)
D
I
V
1
0
25 50 75 100 125 150
= 4.5V, R
GS
TA, AMBIENT TEMPERATURE (oC)
= 228oC/W
JA
θ
V
GS
= 10V, R
JA
θ
= 50oC/W
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
©2003 Fairchild Semiconductor Corporation HUF76105DK8 Rev. B1
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
Typical Performance Curves (Continued)
2
DUTY CYCLE - DESCENDING ORDER
1
0.5
0.2
0.1
0.05
0.02
0.01
0.1
, NORMALIZED
JA
θ
0.01
Z
THERMAL IMPEDANCE
SINGLE PULSE
0.001
-5
10
-4
10
10
-3
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
HUF76105DK8
-2
10
t, RECTANGULAR PULSE DURATION (s)
-1
10
0
10
NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z
1
10
R
= 228oC/W
JA
θ
P
DM
t
1
t
2
1/t2
x R
JA
θ
+ T
JA
A
θ
2
10
10
3
500
100
VGS = 5V
10
, PEAK CURRENT (A)
DM
I
1
10
VGS = 10V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
-5
-4
10
-3
10
FIGURE 4. PEAK CURRENT CAPABILITY
200
100
10
1
, DRAIN CURRENT (A)
D
I
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
0.1
1 10 100
DS(ON)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
V
DSS(MAX)
TJ = MAX RATED
= 25oC
T
A
100µs
1ms
10ms
= 30V
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
-2
10
t, PULSE WIDTH (s)
R
θ
= 228oC/W
JA
TA = 25oC
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
150 - T
I = I
25
-1
10
0
10
1
10
A
125
2
10
20
STARTING TJ = 25oC
10
STARTING TJ = 150oC
If R = 0
, AVALANCHE CURRENT (A)
tAV = (L)(IAS)/(1.3*RATED BV
AS
I
If R ≠ 0
= (L/R)ln[(IAS*R)/(1.3*RATED BV
t
AV
1
DSS
- VDD)
DSS
- VDD) +1]
0.01 0.1 1 10
tAV, TIME IN AVALANCHE (ms)
NO TE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
3
10
©2003 Fairchild Semiconductor Corporation HUF76105DK8 Rev. B1