Fairchild Semiconductor HUF75309T3ST Datasheet

Data Sheet December 2001

HUF75309T3ST

3A, 55V, 0.070 Ohm, N-Channel UltraFET
Power MOSFET

This N-Channel po wer MOSFET is
manufactured using the innovative
UltraFET® process. This advanced

process technology achieves the
lowest possible on-resistance per silicon area, resulting in
outstanding performance. This device is capable of
withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low­voltage bus switches, and power management in portab le
and battery operated products.

Formerly developmental type TA75309.

Ordering Information

PART NUMBER PACKAGE BRAND

HUF75309T3ST SOT-223 5309

NOTE: HUF75309T3ST is available only in tape and reel.

Features

•3A, 55V

• Ultra Low On-Resistance, r

DS(ON)

= 0.070Ω

• Diode Exhibits Both High Speed and Soft Recovery

• Temperature Compensating PSPICE

®

Model

• Thermal Impedance SPICE Model

• Peak Cu rrent vs Pulse Width Curve

• UIS Rating Curve

• Related Literature

- TB334, “Guidelines f or Solde ring Surface Mount
Components to PC Boards”

Symbol

D

G

S

Packaging

SOT-223

DRAIN
(FLANGE)

GATE
DRAIN

SOURCE

Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html

All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.

For severe environments, see our Automotive HUFA series.

©2001 Fairchild Semiconductor Corpo ration HUF75309T3ST Rev. B

HUF75309T3ST

Absolute Maximum Ratings

TA = 25oC, Unless Otherwise Specified

HUF75309T3ST UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (R

= 20kΩ) (Note 1) . . . . . . . . . . . . . V

GS

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

DSS

DGR

GS

55 V
55 V

±20V V

Drain Current

Continuous (Note 2) (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

D

DM

AS

D

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . .T

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . T

CAUTION: Stresses above those listed in “A bsolute Maximu m Rating s” may cause per manent d amage to t he device. This is a str ess on ly rating and operation o f the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

, T

J

STG

L

pkg

3

Figure 5

Figures 6, 14, 15

1.1

9.09

-55 to 150

300
260

A

W

mW/oC

o

C

o

C

o

C

NOTE:

1. T

= 25oC to 125oC.

J

Electrical Specifications

TA = 25oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate to Source Threshold Voltage V

GS(TH)VGS

Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I
Drain to Source On Resistance r

DS(ON)ID

Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t
Total Gate Charge Q

g(TOT)VGS

Gate Charge at 10V Q
Threshold Gate Charge Q

Gate to Source Gate Charge Q
Gate to Drain “Miller” Charge Q
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance Junction to Ambient R

DSSID

DSS

GSS

ON

r

f

OFF

g(10)

g(TH)

gs

gd

ISS

OSS

RSS

θJA

= 250µA, VGS = 0V (Figure 11) 55 - - V

= VDS, ID = 250µA (Figure 10) 2 - 4 V
VDS = 50V, VGS = 0V - - 1 µA
V

= 45V, VGS = 0V, TA = 150oC - - 250 µA

DS

VGS = ±20V - - 100 nA

= 3A, VGS = 10V (Figure 9) - 0.057 0.070 Ω

VDD = 30V, ID ≅ 3A, RL = 10Ω,
V

GS

= 10V, R

GS

= 28Ω

- - 45 ns

-8-ns

-20-ns

-12-ns

-28-ns

- - 65 ns

= 0V to 20V VDD = 30V, ID ≅ 3A,

R

= 10Ω

VGS = 0V to 10V - 10.7 13 nC
VGS = 0V to 2V - 0.71 0.85 nC

L

I

= 1.0mA

g(REF)

(Figure 13)

-1923nC

-1.40- nC

-4.80- nC

VDS = 25V, VGS = 0V, f = 1MHz
(Figure 12)

- 352 - pF

- 146 - pF

-30-pF
Pad Area = 0.164 in2 (See note 2) - - 110
Pad Area = 0.068 in
Pad Area = 0.026 in

2

(See TB377) - - 126

2

(See TB377) - - 143

o
o
o

C/W
C/W
C/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V
Reverse Recovery Time t
Reverse Recovered Charge Q

NOTE:

o

2. 110

C/W measured using FR-4 board with 0.164 in2 footprint for 1000 seconds.

©2001 Fairchild Semiconductor Corpo ration HUF75309T3ST Rev. B

SD
rr
RR

ISD = 3A - - 1.25 V
ISD = 3A, dISD/dt = 100A/µs--41ns
ISD = 3A, dISD/dt = 100A/µs--59nC

Typical Performance Curves

0

0

0

HUF75309T3ST

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0255075100 15

125

TA, AMBIENT TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT

TEMPERATURE

DUTY CYCLE - DESCENDING ORDER

1

0.5

0.2

0.1

0.05

0.02

0.01

0.1

4

R

= 110oC/W

θJA

3

2

, DRAIN CURRENT (A)

D

1

I

0

25 50 75 100 125 15

TA, AMBIENT TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

AMBIENT TEMPERATURE

, NORMALIZED

JA

0.01

θ

Z

THERMAL IMPEDANCE

SINGLE PULSE

0.001

-5

10

-4

10

-3

10

-2

10

t, RECTANGULAR PULSE DURATION (s)

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

100

10

1

, DRAIN CURRENT (A)

D

I

OPERATION IN THIS
AREA MAY BE

0.1

LIMITED BY r

DS(ON)

V

DSS(MAX

110100

VDS, DRAIN TO SOURCE VOLTAGE (V)

TJ = MAX RATED

= 25oC

T

A

R

θJA

100µs

1ms

) = 55V

= 110oC/W

10ms

20

P

DM

t

1

t
NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z

-1

10

50

10

0

TA = 25oC
R

= 110oC/W

θJA

1

10

θ

FOR TEMPERATURES
ABOVE 25
CURRENT AS FOLLOWS:

I = I

25

2

1/t2

x R

JA

10

+ T

JA

θ

2

o

C DERATE PEAK

150 - T

125

A

3

10

A

10

, PEAK CURRENT (A)

DM

I

1

-3

10

-2

10

-1

10

0

10

1

10

2

10

3

10

t, PULSE WIDTH (s)

FIGURE 4. FORWARD BIAS SAFE OPERAT ING AREA F IGURE 5. PEAK CURRENT CAPABILITY

©2001 Fairchild Semiconductor Corpo ration HUF75309T3ST Rev. B