Data Sheet December 2001
HUF75229P3
44A, 50V, 0.022 Ohm, N-Channel UltraFE T
Power MOSFET
This N-Channel po wer MOSFET is
manufactured using the innovative
UltraFET® process. This advanced
process technology achieves the
lowest possible on-resistance per silicon area, resulting in
outstanding performanc e. This device is capable of
withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, lowvoltage bus switches, and pow er management in portable
and battery-operated products.
Ordering Information
PART NUMBER PACKAGE BRAND
HUF75229P3 TO-220AB 75229P
NOTE: When ordering use the entire part number.
Features
• 44A, 50V
• Low On-Resistance, r
DS(ON)
= 0.022Ω
• Temperature Compensating PSPICE® Model
• Thermal Impedance SPICE Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
Packaging
JEDEC TO-220AB
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
For severe environments, see our Automotive HUFA series.
©2001 Fairchild Semiconductor Corpo ration HUF75229P3 Rev. B
HUF75229P3
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
Drain to Gate Voltage (R
= 20kΩ) (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
DGR
GS
50 V
50 V
±20 V
Drain Current
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
, T
J
STG
D
DM
AS
D
44
Figure 5
Figure 6, 14, 15
90
0.6
-55 to 175
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
CAUTION: Stresses above those listed in “A bsolute Maximu m Rating s” may cause per manent d amage to t he device. This is a str ess on ly rating and operation o f the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
L
pkg
300
260
A
W
W/oC
o
C
o
C
o
C
NOTE:
1. T
= 25oC to 150oC.
J
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BV
Gate to Source Threshold Voltage V
GS(TH)VGS
Zero Gate Voltage Drain Current I
Gate to Source Leakage Current I
Drain to Source On Resistance r
DS(ON)ID
Turn-On Time t
Turn-On Delay Time t
d(ON)
Rise Time t
Turn-Off Delay Time t
d(OFF)
Fall Time t
Turn-Off Time t
Total Gate Charge Q
g(TOT)VGS
Gate Charge at 10V Q
Threshold Gate Charge Q
DSSID
DSS
GSS
ON
r
f
OFF
g(10)
g(TH)
= 250µA, VGS = 0V (Figure 11) 50 - - V
= VDS, ID = 250µA (Figure 10) 2 - 4 V
VDS = 45V, VGS = 0V - - 1 µA
= 40V, VGS = 0V, TC = 150oC - - 250 µA
V
DS
VGS = ±20V - - ±100 nA
= 44A, VGS = 10V (Figure 9) 0.017 0.020 0.022 Ω
VDD = 30V, ID ≅ 44A,
= 0.68Ω, VGS = 10V,
R
L
= 9.1Ω
R
GS
(Figures 18, 19)
- - 105 ns
-12-ns
-58-ns
-33-ns
-33-ns
- - 100 ns
= 0V to 20V VDD = 30V,
I
≅ 44A,
VGS = 0V to 10V - 35 43 nC
VGS = 0V to 2V - 2.0 2.5 nC
D
= 0.68Ω
R
L
I
g(REF)
= 1.0mA
-6075nC
(Figures 13, 16, 17)
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R
ISS
OSS
RSS
θJC
θJA
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 12)
(Figure 3) - - 1.66
TO-220 - - 62
- 1060 - pF
- 405 - pF
-95-pF
o
C/W
o
C/W
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage V
SD
Reverse Recovery Time t
Reverse Recovered Charge Q
©2001 Fairchild Semiconductor Corpo ration HUF75229P3 Rev. B
RR
ISD = 44A - - 1.25 V
ISD = 44A, dISD/dt = 100A/µs--72ns
rr
ISD = 44A, dISD/dt = 100A/µs - - 120 nC
Typical Performance Curves
HUF75229P3
1.2
1.0
0.8
0.6
0.4
0.2
POWER DISSIPATION MULTIPLIER
0
0 25 50 75 100 150
125 17
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIP ATION vs CASE
TEMPERATURE
2
DUTY CYCLE - DESCENDING ORDER
0.5
1
0.2
0.1
0.05
0.02
0.01
50
40
30
20
, DRAIN CURRENT (A)
D
I
10
0
25 50 75 100 125 150 175
TC, CASE TEMPERATURE (oC)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
0.1
, NORMALIZED
JC
θ
Z
THERMAL IMPEDANCE
SINGLE PULSE
0.01
-5
10
-4
10
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
200
100
10
, DRAIN CURRENT (A)
D
I
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
1
DS(ON)
BV
MAX = 50V
DSS
1 10 100 20
VDS, DRAIN TO SOURCE VOLTAGE (V)
TJ = MAX RATED
T
C
= 25oC
100µs
1ms
10ms
-3
10
-2
10
t, RECTANGULAR PULSE DURATION (s)
400
100
, PEAK CURRENT (A)
DM
I
40
-5
10
NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z
-1
10
TC = 25oC
VGS = 10V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
-4
10
-3
10
t, PULSE WIDTH (s)
P
DM
t
1
t
2
1/t2
x R
JC
θ
0
10
FOR TEMPERATURES
ABOVE 25
+ T
JC
C
θ
o
C DERATE PEAK
CURRENT AS FOLLOWS:
I
=
-2
10
175 - T
I
25
10
C
150
-1
10
10
0
10
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY
©2001 Fairchild Semiconductor Corpo ration HUF75229P3 Rev. B