Fairchild Semiconductor FMS3815, FMS3810 Datasheet

www.fairchildsemi.com

FMS3810/3815

Triple Video D/A Converters

3 x 8 bit, 150 Ms/s

Features

• 8-bit resolution

• 150 megapixels per second
– 0.2% linearity error

• Sync and blank controls

• 1.0V p-p video into 37.5 Ω or 75 Ω load

• Internal bandgap voltage reference

• Double-buffered data for low distortion

• TTL-compatible inputs

• Low glitch energy

• Single +5 Volt power supply

Applications

• Video signal conversion
– RGB
– YC

C

B

R

– Composite, Y, C

• Multimedia systems

• Image processing

• True-color graphics systems

Block Diagram

Description

FMS3810/3815 products are low-cost triple D/A converters
that are tailored to fit graphics and video applications where
speed is critical. Two speed grades are available:

FMS3810 100 Ms/s
FMS3815 150 Ms/s

TTL-level inputs are converted to analog current outputs that
can drive 25–37.5 Ω loads corresponding to doubly-terminated
50–75 Ω loads. A sync current following SYNC input timing
is added to the I
inputs, setting I
BLANK = L. Although appropriate for many applications
the internal 1.235V reference voltage can be overridden by
the V

REF

input.

Few external components are required, just the current
reference resistor, current output load resistors, and
decoupling capacitors.

Package is a 48-lead LQFP. Fabrication technology is
CMOS. Performance is guaranteed from 0 to 70°C.

output. BLANK will override RGB

OG

, I

OG

OB

and I

currents to zero when

OR

SYNC

BLANK

G

7-0

B

7-0

R

7-0

CLOCK

SYNC

8

8

8

+1.235V

Ref

8 bit D/A

Converter

8 bit D/A

Converter

8 bit D/A

Converter

IO

G

IO

B

IO

R

COMP
R

REF

V

REF

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FMS3810/3815 PRODUCT SPECIFICATION

Functional Description

Within the FMS3810/3815 are three identical 10-bit D/A
converters, each with a current source output. External loads
are required to convert the current to voltage outputs. Data
inputs RGB
= H activates, sync current from I
signals.

Digital Inputs

All digital inputs are TTL-compatible. Data is registered on
the rising edge of the CLK signal. Following one stage of
pipeline delay, the analog output changes t
edge of CLK.

SYNC

SYNC and BLANK inputs control the output level (Figure 1
and Table 1) of the D/A converters during CRT retrace
intervals. BLANK forces the D/A outputs to the blanking
level while SYNC = L turns off a current source that is
connected to the green D/A converter. SYNC = H adds a 40
IRE sync pulse to the green output, SYNC = L sets the green
output to 0.0 Volts during the sync tip. SYNC and BLANK
are registered on the rising edge of CLK.

are overridden by the BLANK input. SYNC

7-0

for sync-on-green video

OS

DO

and BLANK

data: 660 mV max.

after the rising

D/A Outputs

Each D/A output is a current source. To obtain a voltage
output, a resistor must be connected to ground. Output
voltage depends upon this external resistor, the reference
voltage, and the value of the gain-setting resistor connected
between R

and GND.

REF

Normally, a source termination resistor of 75 Ohms is
connected between the D/A current output pin and GND
near the D/A converter. A 75 Ohm line may then be
connected with another 75 Ohm termination resistor at the
far end of the cable. This “double termination” presents the
D/A converter with a net resistive load of 37.5 Ohms.

The FMS3810/3815 may also be operated with a single 75
Ohm terminating resistor. To lower the output voltage swing
to the desired range, the nominal value of the resistor on

should be doubled.

R

REF

Voltage Reference

All three D/A converters are supplied with a common
voltage reference. Internal bandgap voltage reference voltage
is +1.235 Volts with a 3K Ω source resistance. An external
voltage reference may be connected to the V
overriding the internal voltage reference.

A 0.1µF capacitor must be connected between the COMP
pin and V

to stabilize internal bias circuitry and ensure

DD

low-noise operation.

REF

pin,

pedestal: 54 mV

sync: 286 mV

Figure 1. Nominal Output Levels

BLANK gates the D/A inputs and sets the pedestal voltage.
If BLANK = H, the D/A inputs are added to a pedestal which
offsets the current output. If BLANK = L, data inputs and the
pedestal are disabled.

Power and Ground

Required power is a single +5.0 Volt supply. To minimize
power supply induced noise, analog +5V should be
connected to V
capacitors placed adjacent to each V

High slew-rate of digital data makes capacitive coupling to
the outputs of any D/A converter a potential problem. Since
the digital signals contain high-frequency components of the
CLK signal, as well as the video output signal, the resulting
data feedthrough often looks like harmonic distortion or
reduced signal-to-noise performance. All ground pins should
be connected to a common solid ground plane for best
performance.

pins with 0.1 and 0.01 µF decoupling

DD

pin or pin pair.

DD

2

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PRODUCT SPECIFICATION FMS3810/3815

Table 1. Output Voltage versus Input Code, SYNC

V

= 1.235 V, R

REF

= 590 Ω , R

REF

= 37.5 Ω

L

and BLANK

Blue and Red Green

RGB7-0 (MSB…LSB)

SYNC BLANK V

OUT

SYNC BLANK V

1111 1111 X 1 0.714 1 1 1.000
1111 1111 X 1 0.714 0 1 0.714
1111 1110 X 1 0.711 1 1 0.997
1111 1101 X 1 0.709 1 1 0.995

•

•

•

•

•

•

•

•

•

•

•

•
0000 0000 X 1 0.385 1 1 0.671
1111 1111 X 1 0.383 1 1 0.669

•

•

•

•

•

•

•

•

•

•

•

•
0000 0010 X 1 0.059 1 1 0.345
0000 0001 X 1 0.057 1 1 0.343
0000 0000 X 1 0.054 1 1 0.340
0000 0000 X 1 0.054 0 1 0.054

XXXX XXXX X 0 0.000 1 0 0.286
XXXX XXXX X 0 0.000 0 0 0.000
XXXX XXXX X 1 valid 0 1 valid

OUT

•

•

•

•

Pin Assignments

LQFP Package

GND

R7R6R5R4R3R2R

484746454443424140

G
G
G
G
G

G
G
G

DD

1
2

0

3

1

4

2

5

3

6

4

7

5

8

6
7

9
10
11
12

FMS3810/3815

131415161718192021

NC

GND

GND

GND

BLANK

SYNC

V

1

B0B1B2B3B4B6B

R0GND

GND

39

38

22

23

5

B

NC

37

R

36
35

34
33
32
31
30
29
28
27

26
25

24

7

NC

REF

V

REF

COMP
IO

R

IO

G

V

DD

V

DD

IO

B
GND
GND
CLOCK

NC

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3

)

FMS3810/3815 PRODUCT SPECIFICATION

Pin Descriptions

Pin
Name

Pin Number

Value Pin Function DescriptionLQFP

Clock and Pixel I/O

CLK 26 TTL

R

7-0

G

7-0

B

7-0

47-40

9-2

23-16

TTL

Controls

SYNC 11 TTL

BLANK 10 TTL

Video Outputs

IO
IO
IO

R
G
B

33
32
29

0.714 V

Clock Input. The clock input is TTL-compatible and all pixel data is

registered on the rising edge of CLK. It is recommended that CLK be
driven by a dedicated TTL buffer to avoid reflection induced jitter,
overshoot, and undershoot.

Red, Green, and Blue Pixel Inputs. TTL-compatible RGB digital inputs

are registered on the rising edge of CLK.

Sync Pulse Input. Bringing SYNC LOW, turns off a 40 IRE (7.62 mA)

current source which forms a sync pulse on any D/A converter output
connected to IO

. SYNC is registered on the rising edge of CLK along

S

with pixel data and has the same pipeline latency as BLANK and pixel
data. SYNC does not override any other data and should be used only
during the blanking interval. If the system does not require sync pulses,
SYNC and IO

should be connected to GND.

S

Blanking Input. When BLANK is LOW, pixel inputs are ignored and the

D/A converter outputs are driven to the blanking level. BLANK is
registered on the rising edge of CLK and has the same two-pipe latency
as SYNC and Data.

Red, Green, and Blue Current Outputs. Current source outputs can

p-p

drive RS-343A/SMPTE-170M compatible levels into doubly-terminated
75 Ohm lines. Sync pulses may be added to the green output.
When SYNC is HIGH, the current added to I

OG

is:

IO

= 3.64 (V

S

REF

/ R

REF

Voltage Reference

V

REF

35 +1.235 V Voltage Reference Input/Output. Internal 1.235V voltage reference is

available on this pin. An external +1.235 Volt reference may be applied to
this pin to override the internal reference. Decoupling V

to GND with

REF

a 0.1µF ceramic capacitor is required.

R

REF

36 590 Ω Current-setting Resistor. Full-scale output current of each D/A

converter is determined by the value of the resistor connected between
R

and GND. Nominal value of R

REF

R

REF

where I

= 9.1 (V

is the full-scale (white) output current (amps) from the

FS

REF

/I

)

FS

D/A converter (without sync). Sync is 0.4 I

is found from:

REF

.

FS

D/A full-scale (white) current may also be calculated from:

I

= V

FS

Where V
(ohms) on each D/A converter. V

/R

FS

L

is the white voltage level and R

FS

FS

is the total resistive load

L

is the blank to full-scale voltage.

COMP 34 0.1 µF Compensation Capacitor. A 0.1 µF ceramic capacitor should be

connected between COMP and V

to stabilize internal bias circuitry.

DD

4

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