Fairchild Semiconductor FDZ2553N Datasheet
February 2003
S
FDZ255
3
N
FDZ2553N
Monolithic Common Drain N-Channel 2.5V Specified PowerTrench BGA MOSFET
General Description
Combining Fairchild’s advanced 2.5V specified
PowerTrench process with state-of-the-art BGA
packaging, the FDZ2553N minimizes both PCB space
and R
. This Monolithic Common Drain BGA
DS(ON)
MOSFET embodies a breakthrough in packaging
technology which enables the device to combine
excellent thermal transfer characteristics, high current
handling capability, ultra-low profile packaging, low gate
charge, and low R
DS(ON)
.
Applications
• Battery management
• Load switch
• Battery protection
D D
Pin 1
S
S
S
G
S
S
G
S S
D D D
D
S
Q2
S
S
Q1
Pin 1
Bottom
Top
Features
• 9.6 A, 20 V. R
R
• Occupies only 0.10 cm2 of PCB area:
1/3 the area of SO-8.
• Ultra-thin package: less than 0.80 mm height when
mounted to PCB.
• Outstanding thermal transfer characteristics:
significantly better than SO-8.
• Ultra-low Qg x R
• High power and current handling capability
= 14 mΩ @ VGS = 4.5 V
DS(ON)
= 20 mΩ @ VGS = 2.5 V
DS(ON)
figure-of-merit
DS(ON)
S
G
D
G
Q1
Q2
Absolute Maximum Ratings T
o
=25
C unless otherwise noted
A
Symbol Parameter Ratings Units
V
Drain-Source Voltage 20 V
DSS
V
Gate-Source Voltage ±12 V
GSS
ID Drain Current – Continuous (Note 1a) 9.6 A
– Pulsed 20
PD Power Dissipation (Steady State) (Note 1a) 2.1 W
TJ, T
Operating and Storage Junction Temperature Range –55 to +150 °C
STG
Thermal Characteristics
R
Thermal Resistance, Junction-to-Ambient (Note 1a) 60 °C/W
θJA
R
Thermal Resistance, Junction-to-Ball (Note 1) 6.3
θJB
R
Thermal Resistance, Junction-to-Case (Note 1) 0.6
θJC
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
2553N FDZ2553N 7’’ 12mm 3000 units
2003 Fairchild Semiconductor Corporation FDZ2553N Rev D2 (W)
FDZ255
3
N
Electrical Characteristics T
Symbol
Parameter Test Conditions Min Typ Max Units
= 25°C unless otherwise noted
A
Off Characteristics
BV
Drain–Source Breakdown Voltage VGS = 0 V, ID = 250 µA 20 V
DSS
∆BVDSS
∆TJ
I
Zero Gate Voltage Drain Current VDS = 16 V, VGS = 0 V 1 µA
DSS
I
GSSF
I
GSSR
Breakdown Voltage Temperature
ID = 250 µA, Referenced to 25°C 14 mV/°C
Coefficient
Gate–Body Leakage, Forward VGS = 12 V, VDS = 0 V 100 nA
Gate–Body Leakage, Reverse VGS = –12 V, VDS = 0 V –100 nA
On Characteristics (Note 2)
V
Gate Threshold Voltage VDS = VGS, ID = 250 µA 0.6 0.9 1.5 V
GS(th)
∆VGS(th)
∆TJ
R
DS(on)
I
D(on)
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
ID = 250 µA, Referenced to 25°C
VGS = 4.5 V, ID = 9.6 A
VGS = 2.5 V, ID = 7.9 A
VGS = 4.5 V, ID = 9.6 A, TJ=125°C
–3 mV/°C
11
15
15
14
20
20
mΩ
On–State Drain Current VGS = 4.5 V, VDS = 5 V 10 A
gFS Forward Transconductance VDS = 5 V, ID = 9.6 A 45 S
Dynamic Characteristics
C
Input Capacitance 1299 pF
iss
C
Output Capacitance 317 pF
oss
C
Reverse Transfer Capacitance
rss
VDS = 10 V, V
f = 1.0 MHz
= 0 V,
GS
166 pF
Switching Characteristics (Note 2)
t
Turn–On Delay Time 9.0 18 ns
d(on)
tr Turn–On Rise Time 11 20 ns
t
Turn–Off Delay Time 29 46 ns
d(off)
tf Turn–Off Fall Time
Qg Total Gate Charge 12 17 nC
Qgs Gate–Source Charge 2.3 nC
Qgd Gate–Drain Charge
VDD = 10 V, ID = 1 A,
VGS = 4.5 V, R
GEN
= 6 Ω
VDS = 10 V, ID = 9.6 A,
VGS = 4.5 V
11 20 ns
3.2 nC
Drain–Source Diode Characteristics and Maximum Ratings
IS Maximum Continuous Drain–Source Diode Forward Current 1.7 A
VSD Drain–Source Diode Forward
VGS = 0 V, IS = 1.7 A (Note 2) 0.7 1.2 V
Voltage
trr Diode Reverse Recovery Time 21 nS
Qrr Diode Reverse Recovery Charge
Notes:
1. R
is determined with the device mounted on a 1 in² 2 oz. copper pad on a 1.5 x 1.5 in. board of FR-4 material. The thermal resistance from the junction to
θJA
the circuit board side of the solder ball, R
copper chip carrier. R
(a). R
(b). R
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
= 60°C/W when mounted on a 1in2 pad of 2 oz copper, 1.5” x 1.5” x 0.062” thick PCB
θJA
= 108°C/W when mounted on a minimum pad of 2 oz copper
θJA
θJC
and R
θJB
, is defined for reference. For R
θJB
are guaranteed by design while R
IF = 9.6A,
diF/dt = 100 A/µs
, the thermal reference point for the case is defined as the top surface of the
θJC
is determined by the user's board design.
θJA
13 nC
FDZ2553N Rev D2 (W)
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