Fairchild Semiconductor FDS6912A Datasheet

June 1998

FDS6912A
Dual N-Channel, Logic Level, PowerTrenchTM MOSFET

General Description Features

These N-Channel Logic Level MOSFETs are
produced using Fairchild Semiconductor's
advanced PowerTrench process that has been
especially tailored to minimize the on-state
resistance and yet maintain superior switching
performance.

These devices are well suited for low voltage and
battery powered applications where low in-line
power loss and fast switching are required.

6 A, 30 V. R
R

Fast switching speed.
Low gate charge (typical 9 nC).

High performance trench technology for extremely low
R

.

DS(ON)

High power and current handling capability.

= 0.028 Ω @ VGS = 10 V

DS(ON)

= 0.035 Ω @ VGS = 4.5 V.

DS(ON)

SOT-23

SuperSOTTM-6

SuperSOTTM-8

SO-8 SOT-223

SOIC-16

D2

D1

D1

D2

FDS

5

6

4

3

6912A

G2

7

S2

SO-8

pin 1

Absolute Maximum Ratings T

G1

S1

= 25oC unless other wise noted

A

Symbol Parameter FDS6912A Units

V

DSS

V

GSS

I

D

Drain-Source Voltage 30 V
Gate-Source Voltage ±20 V
Drain Current - Continuous (Note 1a) 6 A

- Pulsed 20

P

D

Power Dissipation for Single Operation (Note 1a) 2 W
(Note 1b) 1.6
(Note 1c) 0.9

TJ,T

Operating and Storage Temperature Range -55 to 150 °C

STG

THERMAL CHARACTERISTICS

R

JA

θ

R

JC

θ

Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W

8

2

1

© 1998 Fairchild Semiconductor Corporation

FDS6912A Rev.C

Electrical Characteristics (T

= 25 OC unless otherwise noted )

A

Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS

BV

∆BV

I

DSS

I

GSSF

I

GSSR

DSS

DSS

Drain-Source Breakdown Voltage VGS = 0 V, I D = 250 µA 30 V
Breakdown Voltage Temp. Coefficient

/∆T

J

Zero Gate Voltage Drain Current

ID = 250 µA, Referenced to 25 oC
VDS = 24 V, V

GS

= 0 V

23

1 µA

TJ = 55°C
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse

VGS = -20 V, V

DS

= 0 V

mV /oC

10 µA

-100 nA

ON CHARACTERISTICS (Note 2)

V

∆V

R

GS(th)

GS(th)

DS(ON)

Gate Threshold Voltage VDS = VGS, ID = 250 µA 1 1.5 3 V
Gate Threshold Voltage Temp. Coefficient

/∆T

J

Static Drain-Source On-Resistance

ID = 250 µA, Referenced to 25 oC
VGS = 10 V, I D = 6 A

-4

0.023 0.028

mV /oC

TJ =125°C 0.036 0.044

0.029 0.035

18 S

I
g

D(ON)

FS

VGS = 4.5 V, I D = 5 A
On-State Drain Current VGS = 10 V, VDS = 5 V 20 A
Forward Transconductance

VDS = 15 V, I D= 6 A

DYNAMIC CHARACTERISTICS

C

iss

C

oss

C

rss

Input Capacitance VDS = 15 V, VGS = 0 V,
Output Capacitance 185 pF

f = 1.0 MHz

830 pF

Reverse Transfer Capacitance 80 pF

SWITCHING CHARACTERISTICS (Note 2)

t
t

t
t
Q
Q
Q

D(on)

r

D(off)

f

Turn - On Delay Time
Turn - On Rise Time

VDS= 15 V, I D = 1 A

VGS = 10 V , R

GEN

= 6 Ω

Turn - Off Delay Time 18 29 ns
Turn - Off Fall Time 5 12 ns

g

gs

gd

Total Gate Charge VDS = 15 V, I D = 7.5 A, 9 13 nC
Gate-Source Charge

V

= 5 V

GS

Gate-Drain Charge 3.1 nC

6 12 ns

10 18 ns

2.8 nC

DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

I

S

V

Notes:

1. R

SD

JA

θ

design while R

Maximum Continuous Drain-Source Diode Forward Current 1.3 A
Drain-Source Diode Forward Voltage

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R

is determined by the user's board design.

CA

θ

VGS = 0 V, IS = 1.3 A

(Note 2)

0.73 1.2 V

is guaranteed by

JC

θ

Ω

a. 78OC/W on a 0.5 in

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

pad of 2oz copper.

2

b. 125OC/W on a 0.02 in

pad of 2oz copper.

2

c. 135OC/W on a 0.003 in

pad of 2oz copper.

2

FDS6912A Rev.C