Fairchild Semiconductor FDG6306P Datasheet
FDG6306P
FDG6306P
P-Channel 2.5V Specified PowerTrench MOSFET
February 2001
General Description
This P-Channel 2.5V specified MOSFET is a rugged
gate version of Fairchild Semiconductor’s advanced
PowerTrench process. It has been optimized for power
management applications with a wide range of gate
drive voltage (2.5V – 12V).
Applications
• Battery management
• Load switch
Features
• –0.6 A, –20 V. R
R
• Low gate charge
• High performance trench technology for extremely
low R
• Compact industry standard SC70-6 surface mount
package
DS(ON)
= 420 m Ω @ VGS = –4.5 V
DS(ON)
= 630 mΩ @ VGS = –2.5 V
DS(ON)
S
G
S
1 or 4
6 or 3
D
D
G
2 or 5
5 or 2
G
D
Pin 1
SC70-6
G
S
The pinouts are symmetrical; pin 1 and pin 4 are interchangeable.
Absolute Maximum Ratings T
o
=25
C unle ss otherwise noted
A
D
3 or 6
4 or 1
S
Symbol Parameter Ratings Units
V
Drain-Source Voltage –20 V
DSS
V
Gate-Source Voltage ± 12 V
GSS
ID Drain Current – Continuous (Note 1) –0.6 A
– Pulsed –2.0
PD Power Dissipation for Single Operation (Note 1) 0.3 W
TJ, T
Operating and Storage Junction Temperature Range –55 to +150 °C
STG
Thermal Characteristics
R
Thermal Resistance, Junction-to-Ambient (Note 1) 415 °C/W
θJA
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
2001 Fairchild Semiconductor Corporation FDG6306P Rev C(W)
.06 FDG6306P 7’’ 8mm 3000 units
FDG6306P
Electrical Characteristics T
Symbol
Parameter Test Conditions Min Typ Max Units
= 25°C unless otherwise noted
A
Off Characteristics
BV
Drain–Source Breakdown
DSS
VGS = 0 V, ID = –250 µA
–20 V
Voltage
∆BVDSS
∆TJ
I
Zero Gate Voltage Drain Current VDS = –16 V, VGS = 0 V –1
DSS
I
GSSF
I
GSSR
Breakdown Voltage Temperature
ID = –250 µA, Referenced to 25°C
Coefficient
Gate–Body Leakage, Forward VGS = –12 V, VDS = 0 V –100 nA
Gate–Body Leakage, Reverse VGS = 12 V, VDS = 0 V 100 nA
–14
mV/°C
µA
On Characteristics (Note 2)
V
Gate Threshold Voltage
GS(th)
∆VGS(th)
∆TJ
R
DS(on)
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
VDS = VGS, ID = –250 µA
ID = –250 µA, Referenced to 25°C
VGS = –4.5 V, ID = –0.6 A
VGS = –2.5 V, ID = –0.5 A
VGS = –4.5 V, ID = –0.6 A, TJ=125°C
I
On–State Drain Current VGS = –4.5 V, VDS = –5 V –2 A
D(on)
–0.6 –1.2 –1.5 V
3
300
470
400
420
630
700
mV/°C
M Ω
gFS Forward Transconductance VDS = –5 V, ID = –0.6 A 1.8 S
Dynamic Characteristics
C
Input Capacitance 114 pF
iss
C
Output Capacitance 24 pF
oss
C
Reverse Transfer Capacitance
rss
VDS = –10 V, V
f = 1.0 MHz
= 0 V,
GS
9 pF
Switching Characteristics (Note 2)
t
Turn–On Delay Time 5.5 11 ns
d(on)
tr Turn–On Rise Time 14 25 ns
t
Turn–Off Delay Time 6 12 ns
d(off)
tf Turn–Off Fall Time
Qg Total Gate Charge 1.4 2.0 nC
Qgs Gate–Source Charge 0.3 nC
Qgd Gate–Drain Charge
VDD = –10 V, ID = 1 A,
VGS = –4.5 V, R
GEN
= 6 Ω
VDS = –10 V, ID = –0.6 A,
VGS = –4.5 V
1.7 3.4 ns
0.4 nC
Drain–Source Diode Characteristics and Maximum Ratings
IS Maximum Continuous Drain–Source Diode Forward Current –0.25 A
VSD Drain–Source Diode Forward
Voltage
Notes:
1. R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
θJA
the drain pins. R
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
is guaranteed by design while R
θJC
θJA
VGS = 0 V, IS = –0.25 A(Note 2) –0.77 –1.2 V
is determined by the user's board design. R
= 415°C/W when mounted on a minimum pad .
θJA
FDG6306P Rev C (W)
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