Fairchild Semiconductor FAN5091 Datasheet

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FAN5091

Two Slice Interleaved Synchronous Buck Converter

Features

• Programmable output from 1.10V to 1.85V in 25mV steps
using an integrated 5-bit DAC

• Two interleaved synchronous slices for maximum
performance

• 100nsec response time

• Built-in current sharing between slices

• Remote sense

• Programmable Active Droop



(Voltage Positioning)

• Programmable frequency from 200KHz to 2MHz

• Adaptive delay gate switching

• Integrated high-current gate drivers

• Integrated Power Good, OV, UV, Enable/Soft Start
functions

• Drives N-channel MOSFETs

• Operation optimized for 5V operation

• High efficiency mode (E*) at light load

• Overcurrent protection using MOSFET sensing

• 24 pin TSSOP package

Applications

• Power supply for Pentium

• Power supply for Athlon

• VRM for Pentium IV processor

• Programmable step-down power supply



IV



Description

The FAN5091 is a synchronous multi-slice DC-DC controller
IC which provides a highly accurate, programmable output
voltage for all high-performance processors. Two interleaved
synchronous buck regulator slices with built-in current shar­ing operate 180° out of phase to provide the fast transient
response needed to satisfy high current applications while
minimizing external components. The FAN5091 features
remote voltage sensing and Programmable Active Droop
for 100nsec converter transient response with minimum out­put capacitance. It has integrated high-current gate drivers,
with adaptive delay gate switching, eliminating the need for
external drive devices. The FAN5091 uses a 5-bit D/A con­verter to program the output voltage from 1.10V to 1.85V in
25mV steps with an accuracy of 1%. The FAN5091 uses a
high level of integration to deliver load currents in excess of
50A from a 5V source with minimal external circuitry. The
FAN5091 also offers integrated functions including Power
Good, Output Enable/Soft Start, under- voltage lockout,
over-voltage protection, and adjustable current limiting with
independent current sense on each slice. It is available in a
24 pin TSSOP package.



Block Diagram

-

+

-

+

GNDA

­+

+12V

+

-

7

18

Digital

Control

Digital

Control

ENABLE/SS

ILIM

+12V

+12V

20

+12V

13

14

15

17

16

+12V

12

11

10

8

9

+5V

+5V

REV. 1.0.0 5/10/01

Bypass

6

23

OSC

-

+

5-Bit
DAC

2 3 22

145

VID2

VID1

VID4

VID3

VID0

Pentium is a registered trademark of Intel Corporation. Athlon is a registered trademark of AMD. Programmable Active Droop is a trademark of Fairchild Semiconductor.

24

Power

Good

19

PWRGD

5V Reg

21

DROOP/E*

VO

FAN5091 PRODUCT SPECIFICATION

Pin Assignments

VID0
VID1
VID2
VID3

VID4

BYPASS

AGND

LDRVB

PGNDB

SWB

HDRVB

BOOTB

1

2
3

4
5
6
7
8
9
10
11
12

FAN5091

Pin Definitions

Pin Number Pin Name Pin Function Description

1-5 VID0-4

6 BYPASS

7 AGND

8 LDRVB

9 PGNDB

10 SWB

11 HDRVB

12 BOOTB

13 BOOTA

14 HDRVA

15 SWA

16 PGNDA

17 LDRVA

18 VCC

19 PWRGD

Voltage Identification Code Inputs. These open collector/TTL compatible

inputs will program the output voltage over the ranges specified in Table 1.
Pull-ups are internal to the controller.

5V Rail. Bypass this pin with a 1 µ F ceramic capacitor to AGND.

Analog Ground. Return path for low power analog circuitry. This pin should be

connected to a low impedance system ground plane to minimize ground loops.

Low Side FET Driver for B. Connect this pin to the gate of an N-channel

MOSFET for synchronous operation. The trace from this pin to the MOSFET gate
should be <0.5 " .

Power Ground B. Return pin for high currents flowing in low-side MOSFET.

Connect directly to low-side MOSFET source.

High side driver source and low side driver drain switching node B. Gate

drive return for high side MOSFET, and negative input for low-side MOSFET
current sense.

High Side FET Driver B. Connect this pin to the gate of an N-channel MOSFET.

The trace from this pin to the MOSFET gate should be <0.5 " .

Bootstrap B. Input supply for high-side MOSFET.

Bootstrap A. Input supply for high-side MOSFET.

High Side FET Driver A. Connect this pin to the gate of an N-channel MOSFET.

The trace from this pin to the MOSFET gate should be <0.5 " .

High side driver source and low side driver drain switching node A. Gate

drive return for high side MOSFET, and negative input for low-side MOSFET
current sense.

Power Ground A. Return pin for high currents flowing in low-side MOSFET.

Connect directly to low-side MOSFET source.

Low Side FET Driver for A. Connect this pin to the gate of an N-channel

MOSFET for synchronous operation. The trace from this pin to the MOSFET gate
should be <0.5 " .

VCC. Internal IC supply. Connect to system 12V supply, and decouple with a

0.1 µ F ceramic capacitor.

Power Good Flag. An open collector output that will be logic LOW if the output

voltage is not within +10/-15% of the nominal output voltage setpoint.

24
23
22

21
20
19
18

17
16
15
14
13

VFB
RT
ENABLE/SS

DROOP/E*
ILIM
PWRGD
VCC
LDRVA
PGNDA
SWA
HDRVA
BOOTA

2

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°

°

°

13 °

° C

PRODUCT SPECIFICATION FAN5091

Pin Number Pin Name Pin Function Description

20 ILIM

21 DROOP/E*

Current Limit. A resistor from this pin to ground sets the over current trip level.

Droop Control/Energy Star Mode Control. A resistor from this pin to ground

sets the amount of droop by controlling the gain of the current sense amplifier.
When this pin is pulled high to BYPASS, the slice A drivers are turned off for
Energy-star operation.

22 ENABLE/SS Output Enable/Softstart. A logic LOW on this pin will disable the output. An

internal current source allows for open collector control. This pin also doubles as
soft start.

23 RT

24 VFB

Frequency Set. A resistor from this pin to ground sets the switching frequency.

Voltage Feedback. Connect to the desired regulation point at the output of the

converter.

Absolute Maximum Ratings

Parameter Min. Typ. Max. Unit

Supply Voltage VCC 15 V

Supply Voltages BOOTA, BOOTB 18 V

Voltage Identification Code Inputs, VID0-VID4 6 V

VFB, ENABLE/SS, PWRGD, DROOP/E* 6 V

SWA, SWB -3 15 V

PGNDA, PGNDB to AGND -0.5 0.5 V

Gate Drive Current, peak pulse 3 A

Junction Temperature, T

J

Storage Temperature -65 150

Lead Soldering Temperature, 10 seconds 300

Power Dissipation, P

Thermal Resistance Junction-to-Case, Θ

D

JC

-55 150

950 mW

C

C

C

C/W

Recommended Operating Conditions

Parameter Conditions Min. Typ. Max. Units

Output Driver Supply, BOOT 10.8 12 13.2 V

Input Logic HIGH 2.4 V

Input Logic LOW 0.8 V

Ambient Operating Temperature 0 70

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3

•

•

•

•

∆

Ω

•

•

FAN5091 PRODUCT SPECIFICATION

Electrical Specifications

(V

= 12V,V

CC

The • denotes specifications which apply over the full operating temperature range.

Parameter Conditions Min. Typ. Max. Units

Output Voltage See Table 1

Output Current 50 A

Initial Voltage Setpoint I

Output Temperature Drift T

Line Regulation V

3

Droop

Programmable Droop Range -10 0 %Vout

Total Output Variation,
Steady State

Total Output Variation, Transient

Response Time

Gate Drive On-Resistance 1.0

Upper Drive Low Voltage V

Upper Drive High Voltage V

Lower Drive Low Voltage I

Lower Drive High Voltage V

Output Driver Rise & Fall Time See Figure 3 20 nsec

Current Mismatch R

Output Overvoltage Detect

Efficiency I

Oscillator Frequency RT = 41.2K Ω

Oscillator Range RT = 125K Ω to 12.5 K Ω

Maximum Duty Cycle RT = 125K Ω

Minimum LDRV on-time RT = 12.5K Ω

Input LOW current, VID pins V

Soft Start Current 10 µA

Enable Threshold ON

BYPASS Voltage 4.75 5 5.25 V

BYPASS Capacitor 100 nF

PWRGD Threshold Logic LOW, minimum

PWRGD Hysteresis 20 mV

PWRGD Output Voltage I

PWRGD Delay High → Low 500 µsec

12V UVLO

UVLO Hysteresis 0.5 V

12V Supply Current HDRV and LDRV Open 20 mA

Over Temperature Shutdown 150 °C

Over Temperature Hysteresis 40 °C

= 1.500V, and T

OUT

1

= +25°C using circuit in Figure 1, unless otherwise noted.)

A

1.100 1.850 V

= 5A 1.485 1.500 1.515 V

LOAD

= 0 to 70°C +5 mV

A

= 11.4V to 12.6V

CC

I

= 0.8A to I

LOAD

I

= 0.8A to I

LOAD

2

I

= 0.8A to I

LOAD

V

= 10mV 100 nsec

out

–V

HDRV

BOOT

sink

CC

DS,on

SW

–V

HDRV

= 10µA 0.2 V

–V

LDRV

(A) = R

at I

at I

max

max

max

= 10µA 0.2 V

sink

at I

source

DS,on

= 10µA 0.5 V

source

= 10µA 0.5 V

(B), I

LOAD

= I

max

-90 -100 -110 mV

1.430 1.570 V

1.430 1.570 V

+130 µV

5%

2.1 2.3 V

= I

LOAD

I

= 2A (E*-mode)

LOAD

max

85
70

450 600 750 KHz

200 2000 KHz

90 %

330 nsec

= 0.4V 50 µA

VID

OFF 0.4

•

81

Logic LOW, maximum

= 4mA 0.4 V

sink

•

106

85

110

8.5 9.5 10.5 V

1.0 V

89

%V

114

%

out

•

4

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PRODUCT SPECIFICATION FAN5091

Notes:

1. Steady State Voltage Regulation includes Initial Voltage Setpoint, Output Ripple and Output Temperature Drift and is

measured at the converter’s VFB sense point.

2. As measured at the converter’s VFB sense point. For motherboard applications, the PCB layout should exhibit no more than

0.5m Ω trace resistance between the converter’s output capacitors and the CPU. Remote sensing should be used for optimal
performance.

3. Using the VFB pin for remote sensing of the converter’s output at the load, the converter will be in compliance with Intel’s

VRM 9.0 specification of +70, -70mV.

Table 1. Output Voltage Programming Codes

VID4 VID3 VID2 VID1 VID0 V

11111OFF

111101.100V

111011.125V

111001.150V

110111.175V

110101.200V

110011.225V

110001.250V

101111.275V

101101.300V

101011.325V

101001.350V

100111.375V

100101.400V

100011.425V

100001.450V

011111.475V

011101.500V

011011.525V

011001.550V

010111.575V

010101.600V

010011.625V

010001.650V

001111.675V

001101.700V

001011.725V

001001.750V

000111.775V

000101.800V

000011.825V

000001.850V

OUT

to CPU

Note:

1. 0 = VID pin is tied to GND.

1 = VID pin is open.

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5

FAN5091 PRODUCT SPECIFICATION

Typical Operating Characteristics

(VCC = 12V, and TA = +25°C using circuit in Figure 2, unless otherwise noted.)

EFFICIENCY VS. OUTPUT CURRENT

90
85

E-*

80
75
70
65
60

EFFICIENCY (%)

55
50
45
40

01020304050

TRANSIENT RESPONSE, 50A to 0.5A

OUTPUT CURRENT (A)

2-Slice

TRANSIENT RESPONSE, 0.5A TO 50A

1.590V

(50mV / DIV)

OUT

V

TIME (20µs/DIVISION)

HIGH-SIDE GATE DRIVES, NORMAL OPERATION

5V/DIVISION

1.550V

1.480V

(50mV / div)

OUT

V

TIME (20µs/DIVISION)

HIGH-SIDE GATE DRIVES, E*-MODE

5V/DIVISION

1.590V

1.550V

1.480V

TIME (500ns/DIVISION)

TIME (500ns/DIVISION)

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PRODUCT SPECIFICATION FAN5091

Typical Operating Characteristics (Continued)

OUTPUT RIPPLE VOLTAGE

10mV/DIVISION

TIME (1µs/DIVISION)

GATE DRIVE FALL TIME

GATE DRIVE RISE TIME

5V/DIVISION

TIME (50ns/DIVISION)

ADAPTIVE GATE DELAY

5V/DIVISION

TIME (10ns/DIVISION)

CURRENT SHARING BETWEEN INDUCTORS

5A/DIVISION

TIME (500ns/DIVISION)

10V/DIVISION 5V/DIVISION

TIME (50ns/DIVISION)

POWER GOOD DURING DYNAMIC

VOLTAGE ADJUSTMENT

5V/DIVISION 50mV/DIVISION

TIME (200µs/DIVISION)

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