Fairchild Semiconductor FAN5071 Datasheet

www.fairchildsemi.com

FAN5071

High Performance Programmable Synchronous
DC-DC Controller for Multi-Voltage Platforms

Features

• Output programmable in 25mV steps from 1.05V to

1.825V using a dynamically programmable integrated
5-bit DAC

• Controls adjustable linears for Vclock (2.5V),
Vnorthbridge (1.8V) or Vagp (selectable 1.5V/3.3V), and
Vadj (1.2V nominal)

• Remote sense

• Programmable Active Droop

™

up to 200mV

• Drives N-Channel MOSFETs

• Overcurrent protection using MOSFET sensing

• Overvoltage protection including startup

• 85% efficiency typical at full load

• Integrated Power Good and Enable/Soft Start functions

• Linears start instantly

• Meets Intel VRM8.5 specifications using minimum
number of external components

• 24 pin SOIC package

Applications

• Power supply for Pentium

• VRM for Pentium III processor

• Programmable multi-output power supply

®

III Platforms

Block Diagram

+3.3V

+1.2V/Adj

+2.5V

9

+

REF

-

10

VCCP

11

+

-

12

OSC

PWRGD,
OCL

REF

PWRGD,
OCL

OCL

-

+

Description

The FAN5071 is a synchronous mode DC-DC controller IC
which provides a highly accurate, programmable set of output
voltages for multi-voltage platforms such as the Intel Pentium III,
and provides a complete solution for all Intel VRM8.5 CPU
applications, and for other high-performance processors. The
FAN5071 features remote voltage sensing, independently
adjustable current limit, and a proprietary wide-range Pro­grammable Active Droop
response and VRM8.5 compliance. The FAN5071 uses a 5-bit
D/A converter to dynamically program the output voltage dur­ing operation from 1.05V to 1.825V in 25mV steps. The
FAN5071 uses a high level of integration to deliver load cur­rents in excess of 28A from a 5V source with minimal exter­nal circuitry. Synchronous-mode operation offers optimum
efficiency over the entire specified output voltage range. An
on-board precision low TC reference achieves 0.8% voltage
regulation without expensive external components. The
FAN5071 includes linear regulator controllers for Vclock
(2.5V),Vnorthbridge (1.8V) or Vagp (selectable 1.5V/3.3V),
and Vadjustable (1.2V nominal) each adjustable with an
external divider. The FAN5071 also offers integrated functions
including open-collector Power Good, Output Enable/Soft

+5V

VCCA

21

-

+

-

+

™

for optimal converter transient

19

R

D

+12V

18

20

24
1

R

VCCP
HIDRV

+5V

S

15

14

3.3/1.5V

Pentium is a registered trademark of Intel Corporation. Programmable Active Droop is a trademark of Fairchild Semiconductor.

13

5-Bit

DAC

87654

VID2

VID0

VID1

V

PWRGD, OCL

VID4

VID3

-

+

1.24V

Reference

-

+

3

GNDA

Digital

Control

16

ENABLE/SS

Powe r

Good

2

23

22

17

LODRV

GNDP

PWRGD

VCC

REV. 1.0.4 1/29/02

2

FAN5071

.

.

Start and current limiting. The linears start instantly, not

Pin Assignments

waiting for softstart. The FAN5071 is available in a 24 pin
SOIC package.

HIDRV

SW

GNDA

VID4
VID3
VID2

VID1

VID0

VADJGATE

VADJFB

VCKGATE

VCKFB

1
2
3
4
5
6
7
8
9
10
11
12

FAN5071

24
23
22
21
20
19
18
17
16
15
14
13

Pin Definitions

Pin Number Pin Name Pin Function Description

1 HIDRV

2SW

3 GNDA

4-8 VID4-0

9 VADJGATE Gate Driver for VADJ Transistor. For Adjustable output.

10 VADJFB Voltage Feedback for VADJ.

11 VCKGATE Gate Driver for VCK Transistor. For 2.5V output.

12 VCKFB

13 VAGPFB Voltage Feedback for VAGP.

14 VAGPGATE Gate Driver for VAGP Transistor. For 3.3/1.5V output.

15 TYPEDET Type Detect. Sets 3.3V or 1.5V for AGP.

16 ENABLE/SS Output Enable. A logic LOW on this pin will disable all outputs. An internal current

17 PWRGD Power Good Flag. An open collector output that will be logic LOW if any output

18 ILIM

19 DROOP Droop Set. Use this pin to set magnitude of active droop.

20 VFB

21 VCCA

22 GNDP

23 LODRV V

24 VCCP

High Side FET Driver. Connect this pin to the gate of an N-channel MOSFET. The

trace from this pin to the MOSFET gate should be <0.5".

High Side Driver Source and Low Side Driver Drain Switching Node. Together

with DROOP and ILIM pins allows FET sensing for V

current.

CC

Analog Ground. Return path for low power analog circuitry. This pin should be

connected to a low impedance system ground plane to minimize ground loops.

Voltage Identification Code Inputs. These open collector/TTL compatible inputs

will program the output voltage over the ranges specified in Table 1.

Voltage Feedback for VCK.

source allows for open collector control. This pin also doubles as soft start for the
switcher.

voltage is not within ±14% of the nominal output voltage setpoint.

V

Current Feedback. Pin 18 is used in conjunction with pin 2 as the input for the

CC

V

current feedback control loop. Layout of these traces is critical to system

CC

performance. See Application Information for details.

Vcc Voltage Feedback. Pin 20 is used as the input for the V

voltage feedback

CC

control loop. See Application Information for details regarding correct layout.

Analog V

Connect to system 5V supply and decouple with a 0.1µF ceramic

CC

capacitor.

Power Ground. Return pin for high currents flowing in pin 24 (V

Low Side FET Driver. Connect this pin to the gate of an N-channel MOSFET

CC

CCP

).

for synchronous operation. The trace from this pin to the MOSFET gate should be
<0.5".

Power V

For all FET drivers. Connect to system 12V supply through a 33 Ω , and

CC

decouple with a 1µF ceramic capacitor.

VCCP
LODRV
GNDP
VCCA
VFB
DROOP
ILIM
PWRGD
SS/ENABLE
TYPEDET
VAGPGATE
VAGPFB

REV. 1.0.4 1/29/02

PRODUCT SPECIFICATION FAN5071

Absolute Maximum Ratings

Supply Voltage V

Supply Voltage V

to GND 15V

CCP

to GND 13.5V

CCA

Voltage Identification Code Inputs, VID0-VID4 VCCA

All Other Pins 13.5V

Junction Temperature, T

J

150°C

Storage Temperature -65 to 150°C

Lead Soldering Temperature, 10 seconds 300°C

Thermal Resistance Junction-to-case, Θ

Note 1: Component mounted on demo board in free air.

1

JA

75°C/W

Recommended Operating Conditions

Parameter Conditions Min. Typ. Max. Units

Supply Voltage V

CCA

Input Logic HIGH 2.0 V

Input Logic LOW 0.8 V

Ambient Operating Temperature 0 70 °C

Output Driver Supply, V

CCP

4.50 5 5.25 V

10.8 12 13.2 V

Electrical Specifications

(V

= 5V, V

CCA

The • denotes specifications which apply over the full operating temperature range.

Parameter Conditions Min. Typ. Max. Units

V

Regulator

CC

Output Voltage See Table I • 1.05 1.825 V

Output Current 28 A

Initial Voltage Setpoint I

Output Temperature Drift T

Line Regulation V

Internal Droop Impedance

Maximum Programmable Droop • 200 mV

Output Ripple 20MHz BW, I

Total Output Variation, Steady State

Total Output Variation, Transient

Short Circuit Detect Current • 45 50 60 µA

Efficiency I

Output Driver Rise & Fall Time See Figure 3 50 nsec

Output Driver Deadtime See Figure 3 50 nsec

Duty Cycle 0 100 %

5V UVLO • 3.76 4 4.24 V

12V UVLO • 7.65 8.5 9.35 V

Soft Start Current 5 10 17 µA

= 12V, V

CCP

= 1.425V, and T

OUT

3

2

= +25°C using circuits in Figure 1, unless otherwise noted.)

A

= 0.8A, V

LOAD

= 0 to 70°C, V

A

= 4.75V to 5.25V • +10 mV/V

IN

I

= 0.8A to 30A 13.0 14.4 15.8 K Ω

LOAD

1

V

= 1.425V

VID

I

= 0.8A to I

LOAD

= 18A, V

LOAD

= 1.425V 1.453 1.465 1.477 V

VID

= 1.425V • -6 mV

VID

= 28A 20 mVpk

LOAD

3

, V

max

VID

= 1.425V

VID

= 1.425V 83 %

• 1.360 1.490 V

• 1.335 1.515 V

REV. 1.0.4 1/29/02

3

FAN5071

4

≤

≤

≤

≤

Electrical Specifications

(V

CCA

= 5V, V

= 12V, V

CCP

= 1.425V, and T

OUT

(Continued)

= +25°C using circuits in Figure 1, unless otherwise noted.)

A

The • denotes specifications which apply over the full operating temperature range.

Parameter Conditions Min. Typ. Max. Units

Adjustable Linear Regulator

Output Voltage I

Over Current Trip Level 80 %V

2A • 1.188 1.212 1.236 V

LOAD

O

VCLK Linear Regulator

Output Voltage I

Over Current Trip Level 80 %V

2A • 2.375 2.5 2.625 V

LOAD

O

VAGP Linear Regulator

Output Voltage I

Output Voltage I

Over Current Trip Level 80 %V

2A, TYPEDET = 0V • 1.425 1.5 1.575 V

LOAD

2A, TYPEDET = OPEN • 3.135 3.3 3.465 V

LOAD

O

Common Functions

Oscillator Frequency • 255 300 345 kHz

PWRGD Threshold

4

Switcher Logic HIGH [V

Logic LOW [V

+ 85mV]

VID

–155mV]

VID

•

88

•

80

112
120

%

PWRGD Delay Switcher HIGH → LOW 6 µsec

PWRGD Hysteresis Switcher 25 mV

PWRGD Threshold

4

Linear

All Outputs • 80 %V

out

Regulators

Notes:

1. Steady State Voltage Regulation includes Initial Voltage Setpoint, Droop, Output Ripple and Output Temperature Drift and is

measured at the converter’s VFB sense point.

2. As measured at the converter’s VFB sense point. For motherboard applications, the PCB layout should exhibit no more than

0.5m Ω trace resistance between the converter’s output capacitors and the CPU. Remote sensing should be used for optimal
performance.

3. Using the VFB pin for remote sensing of the converter’s output at the load, and the appropriate droop, the converter will be in

compliance with Intel’s VRM 8.5 specification. If Intel specifications on maximum plane resistance from the converter’s output
capacitors to the CPU are met, the specifications at the capacitors will also be met.

4. PWRGD will be high only if BOTH the linears and the switcher conditions are met. PWRGD will be low if EITHER condition is met.

REV. 1.0.4 1/29/02

FAN5071

Table 1. Output Voltage Programming Codes for FAN5071

VID25mV VID3 VID2 VID1 VID0 Nominal V

001001.050V

101001.075V

000111.100V

100111.125V

000101.150V

100101.175V

000011.200V

100011.225V

000001.250V

100001.275V

011111.300V

111111.325V

011101.350V

111101.375V

011011.400V

111011.425V

011001.450V

111001.475V

010111.500V

110111.525V

010101.550V

110101.575V

010011.600V

110011.625V

010001.650V

110001.675V

001111.700V

101111.725V

001101.750V

101101.775V

001011.800V

101011.825V

OUT

5

Note:

1. 0 = processor pin is tied to GND.

1 = processor pin is pulled up to 3.3V.

REV. 1.0.4 1/29/02