Preliminary
© 2000 Fairchild Semiconductor Corporation DS012447 www.fairchildsemi.com
May 2000
Revised May 2000
74LVTH16500 Low Voltage 18-Bit Universal Bus Transceivers
74LVTH16500
Low Voltage 18-Bit Universal Bus Transceivers
with 3-STATE Outputs (Preliminary)
General Description
The LVTH16500 is an 18-bit universal bus transceiver
combining D-type latches and D-type flip-flops to allow
data flow in transparent, latched, and clocked modes.
Data flow in each dir ection is controlled by o utput-enable
(OEAB and OEBA
), latch-enable (LEAB and LEBA), and
clock (CLKAB
and CLKBA) inputs.
The LVTH16500 data inputs includ e bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
The transceiver is designed for low voltage (3.3V) V
CC
applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH16500 is fab ricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining low
power dissipation.
Features
■ Input and output interface capability to systems at
5V V
CC
■ Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
■ Live insertion/extraction per mitted
■ Power Up/Down high impedance provides glitch-free
bus loading
■ Outputs source/sink −32 mA/+64 mA
■ Functionally compatible with the 74 series 16500
■ Latch-up performance exce eds 500 mA
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix “X” to the ordering code.
Order Number Package Numb er Package Description
74LVTH16500MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
74LVTH16500MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide