Fairchild Semiconductor 74LVTH16500MTDX, 74LVTH16500MTD, 74LVTH16500MEAX, 74LVTH16500MEA Datasheet
Preliminary
© 2000 Fairchild Semiconductor Corporation DS012447 www.fairchildsemi.com
May 2000
Revised May 2000
74LVTH16500 Low Voltage 18-Bit Universal Bus Transceivers
74LVTH16500
Low Voltage 18-Bit Universal Bus Transceivers
with 3-STATE Outputs (Preliminary)
General Description
The LVTH16500 is an 18-bit universal bus transceiver
combining D-type latches and D-type flip-flops to allow
data flow in transparent, latched, and clocked modes.
Data flow in each dir ection is controlled by o utput-enable
(OEAB and OEBA
), latch-enable (LEAB and LEBA), and
clock (CLKAB
and CLKBA) inputs.
The LVTH16500 data inputs includ e bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
The transceiver is designed for low voltage (3.3V) V
CC
applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH16500 is fab ricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining low
power dissipation.
Features
■ Input and output interface capability to systems at
5V V
CC
■ Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
■ Live insertion/extraction per mitted
■ Power Up/Down high impedance provides glitch-free
bus loading
■ Outputs source/sink −32 mA/+64 mA
■ Functionally compatible with the 74 series 16500
■ Latch-up performance exce eds 500 mA
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix “X” to the ordering code.
Order Number Package Numb er Package Description
74LVTH16500MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
74LVTH16500MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Preliminary
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74LVTH16500
Connection Diagram Pin Descriptions
Function Table
(Note 1)
H = HIGH Voltage Level L = LOW Voltage L ev el
X = Immaterial Z = High Impedance
↓ = HIGH-to-LOW Clock Transition
Note 1: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA
,
LEBA, and CLKBA
.
Note 2: Output level be fore the indicated steady-st ate input conditions
were established.
Note 3: Output level be fore the indicated steady-st ate input conditions
were established, provided that CLKAB
was LOW before LEAB went LOW.
Functional Description
For A-to-B da t a fl ow, the dev i ce ope r at e s in th e tr ans p ar en t
mode when LEAB is H IGH. When LEAB is LOW, the A
data is latched if CLKAB
is held at a HIGH or LOW logic
level. If LEAB is LOW, the A bus data is stored in the latch/
flip-flop on the HIGH -to-LOW tra nsition of CLKA B
. Output-
enable OEAB is active-HIGH. When OEAB is HIGH, the
outputs are active. When OEAB is LOW, the outputs are in
the high-impedance state.
Data flow for B-to-A is similar to that of A -to-B but uses
OEBA
, LEBA, and CLKBA. The output enables are com-
plementary (OEAB is active-HIGH and OEBA
is active-
LOW).
Logic Diagram
Pin Names Description
A
1–A18
Data Register A Inputs/3-STATE Outputs
B
1–B18
Data Register B Inputs/3-STATE Outputs
CLKAB
, CLKBA Clock Pulse Inputs
LEAB, LEBA Latch Enable Inputs
OEAB, OEBA
Output Enable Inputs
Inputs
Output
B
OEAB LEAB CLKAB
A
LXXX Z
HHXL L
HHXH H
HL↓ LL
HL↓ HH
HLHXB
0
(Note 2)
HLLXB
0
(Note 3)
Preliminary
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74LVTH16500
Absolute Maximum Ratings(Note 4)
Recommended Operating Conditions
Note 4: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indica te d m ay adversely affect devic e reliability. Functional operation under absolute maximum rated conditions is not imp lied.
Note 5: I
O
Absolute Maximum Rating must be observed.
Symbol Parameter Value Conditions Units
V
CC
Supply Voltage −0.5 to +4.6 V
V
I
DC Input Voltage −0.5 to +7.0 V
V
O
DC Output Voltage −0.5 to +7.0 Output in 3-STATE V
−0.5 to +7.0 Output in HI GH or LOW State ( Note 5) V
I
IK
DC Input Diode Current −50 VI < GND mA
I
OK
DC Output Diode Current −50 VO < GND mA
I
O
DC Output Current 64 VO > VCCOutput at HIGH State
mA
128 V
O
> VCCOutput at LOW State
I
CC
DC Supply Current per Supply Pin ±64 mA
I
GND
DC Ground Current per Ground Pin ±128 mA
T
STG
Storage Temperature −65 to +150 °C
Symbol Parameter Min Max Units
V
CC
Supply Voltage 2.7 3.6 V
V
I
Input Voltage 0 5.5 V
I
OH
HIGH-Level Output Curren t −32 mA
I
OL
LOW-Level Output Current 64 mA
T
A
Free-Air Operating Temperature −40 85 °C
∆t/∆V Input Edge Rate, V
IN
= 0.8V – 2.0V, VCC = 3.0V 0 10 ns/V
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