Fairchild Semiconductor 74F191SJX, 74F191SJ, 74F191SCX, 74F191SC, 74F191PC Datasheet
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© 1999 Fairchild Semiconductor Corporation DS009495 www.fairchildsemi.com
April 1988
Revised July 1999
74F191 Up/Down Binary Counter with Preset and Ripple Clock
74F191
Up/Down Binary Counter with Preset and Ripple Clock
General Description
The 74F191 is a reversible modulo-16 b inary coun ter featuring synchronous count ing and as ynchron ous pre settin g.
The preset featur e allows the 74F191 to be used in programmable dividers. T he Cou nt E nable in put, th e Terminal
Count output and Ripple Clock output make possible a
variety of methods of implem enti ng multista ge coun ters. In
the counting modes, state changes are i nitiated by the rising edge of the clock.
Features
■ High-Speed—125 MHz typical count frequency
■ Synchronous counting
■ Asynchronous parallel load
■ Cascadable
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74F191SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F191SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F191PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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74F191
Unit Loading/Fan Out
Functional Description
The 74F191 is a synchronous up/down 4-bit binary
counter. It contains four edge-triggered flip-flops, with internal gating and s teering logic to provide individual preset,
count-up and count-down operations.
Each circuit has an asynchronous parallel load capability
permitting the counter to be preset to any desire d number.
When the Parallel Load (PL
) input is LOW, information
present on the Parallel Data inputs (P
0–P3
) is loaded into
the counter and appears on the Q outputs. T his operatio n
overrides the counting functions, as indicated in the Mode
Select Table.
A HIGH signal on the CE
input inhibits c oun ti ng . Wh en C E
is LOW, internal state changes are initiated synchronousl y
by the LOW-to-HIGH transition of the clock input. The
direction of countin g is determined by th e U
/D input signal,
as indicated in the Mode Select Table. CE
and U/D can be
changed with the clo ck in either state, provided only that
the recommended setup and hold times are observed.
Two types of outputs are pro vided as overflow/underflow
indicators. The Terminal Count (TC) output is normally
LOW and goes HIGH when a circuit reaches zero in the
count-down mo d e or r e ach es 15 in t h e c ou nt- u p mo de . T he
TC output will then remain HIGH until a state change
occurs, whether by count ing or presetting or until U
/D is
changed. The TC output should not be used as a clock signal because it is subject to decoding spikes.
The TC signal is also use d internally to ena ble the Ripple
Clock (RC
) output. The RC output is normally HIGH. When
CE
is LOW and TC is HIGH, the RC output will go LOW
when the clock next goes LOW and will stay LOW u ntil the
clock goes HIGH ag ain. This feature simplifies the desi gn
of multistage counters, as indicated in Figure 1 and
Figure 2. In Figure 1, each RC
output is used as the cl ock
input for the next higher stage. This configuration is particularly advantageous when the clock source has a limited
drive capability, since it drives only the first stage. To prevent counting in all sta ges it is onl y n ece ssar y to inh i bit th e
first stage, since a HIGH signal on CE
inhibits the R C out-
put pulse, as indicated in the RC
Truth Table. A disadvantage of this configuration, in some applications, is the
timing skew between st ate changes in the first and last
stages. This represen ts the cumulative delay of the cl ock
as it ripples through the preceding stages.
A method of causing state changes to occur simultaneously in all stages is shown in Figur e 2. All clock inputs
are driven in pa rallel and the RC
outputs propagate the
carry/borrow signals in ripple fashion. In this configuration
the LOW state du rat io n of the c lock mus t be lon g eno ugh to
allow the negative-g oin g e dge of the carry/borrow signa l to
ripple through to the last stage before the clock goes HIGH.
There is no such restriction on the HIG H state dura tion of
the clock, since the RC
output of any device goe s HIGH
shortly after its CP input goes HIGH.
The configuration shown in Figure 3 avoids ri pple delays
and their associat ed restrictio ns. The CE
input for a given
stage is formed by combinin g the TC signals from all the
preceding stages. Note that in order to inhibit countin g an
enable signal must be included in each carry gate. The
simple inhibit scheme of Figure 1 and Figure 2 doesn't
apply, because the TC output of a given stage is not
affect ed by its own CE
.
Mode Select Table
RC
Truth Table
*TC is generated internally
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
= LOW Pulse
Pin Names Description
U.L.
Input I
IH/IIL
HIGH/LOW
Output I
OH/IOL
CE Count Enable Input (Active LOW) 1.0/3.0 20 µA/−1.8 mA
CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA
P
0–P3
Parallel Data Inputs 1.0/1.0 20 µA/−0.6 mA
PL
Asynchronous Parallel Load Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA
U
/D Up/Down Count Control Input 1.0/1.0 20 µA/−0.6 mA
Q
0–Q3
Flip-Flop Outputs 50/33.3 −1 mA/20 mA
RC
Ripple Clock Output (Active LOW) 50/33.3 −1 mA/20 mA
TC Terminal Count Output (Active HIGH) 50/33.3 −1 mA/20 mA
Inputs
Mode
PL
CE U/D CP
HL L
Count Up
HL H
Count Down
L X X X Preset (Asyn.)
H H X X No Change (Hold)
Inputs Output
CE
TC* CP RC
LH
HXX H
XLX H
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74F191
FIGURE 1. n-Stage Counter Using Ripple Clock
FIGURE 2. Synchronous n-Stage Counter Using Ripple Carry/Borrow
FIGURE 3. Synchronous n-Stage Counter with Gated Carry/Borrow
Logic Diagram
Please note that this d iagram is provided only f or t he understanding of lo gic operations and should not be used to estimat e propagation delays.
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