Fairchild Semiconductor 74ALVC16827 Datasheet

74ALVC16827
Low Voltage 20-Bit Buffer/Line Driver

with 3.6V Tolerant Inputs and Outputs

74ALVC16827 Low Voltage 20-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs

November 2001
Revised November 2001

General Description

The ALVC16827 contains twenty n on -inve rti n g b uffers wit h
3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver carrying parity. The device is byte controlled. Each
byte has NOR output enables for maximum control flexibil­ity.

The 74ALVC16827 is designed for low voltage (1.65V to

3.6V) V
The 74ALVC16827 is fabricated w ith an advanc ed CMOS

technology to achieve high speed operation while maintain­ing low CMOS power dissipation.

applications with I/O capability up to 3.6V.

CC

Features

■ 1.65V to 3.6V VCC supply operation

■ 3.6V tolerant inputs and outputs

■ t

PD

3.0 ns max for 3.0V to 3.6V V

3.5 ns max for 2.3V to 2.7V VCC

6.0 ns max for 1.65V to 1.95V V

■ Power-off high impedance inputs and outputs

■ Supports live insertion and withdrawal (Note 1)

■ Uses patented noise/EMI reductio n circuitr y

■ Latchup conforms to JEDEC JED78

■ ESD performance:

Human body model
Machine model

Note 1: To ensure the high-impedance state d uring power up or power
down, OE

should be tied to VCC through a pull-up r esistor; the min imum
value of the res istor is d eter mine d by the cu rre nt-sou rcin g ca pa bility of t he
driver.

> 200V

CC

CC

> 2000V

Ordering Code:

Order Number Package Number Package Description

74ALVC16827MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol Pin Descriptions

Pin Names Description

OE
I

0–I19

O

0–O19

n

Output Enable Input (Active LOW)

Inputs
Outputs

© 2001 Fairchild Semiconductor Corporation DS500697 www.fairchildsemi.com

Connection Diagram Truth Tables

OE

1

LL L L

74ALVC16827

LL H H
HX X Z
XH X Z

OE

3

LL L L
LL H H
HX X Z
XH X Z

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance

Functional Description

The 74ALVC16827 contains twenty non-inverting buffers
with 3-STATE outputs. The device is byte controlled with
each byte functionin g identically, but independent of each
other. The control pins may be sh orted together to ob tain
full 16-bit operation. The 3-STA TE outputs are controlled by
Output Enable (OE

LOW, O

0—O10

or OE2 are HIGH, the standard outputs are in the high
impedance mode b ut this does not interfere with enter ing

new data into the in puts. The same applies for byte two
with OE

and OE4.

3

Inputs Outputs
OE

2

I0–I

9

O0–O

9

Inputs Outputs
OE

4

) inputs. When OE1, and OE2 are

n

I0–I

9

O10–O

19

are in the 2- state mode. When e ither OE

1

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Logic Diagrams