Fairchild Semiconductor 74ALVC16601 Datasheet

October 2001 Revised October 2001

74ALVC16601 Low Voltage 18-Bit Universal Bus Transceivers

with 3.6V Tolerant Inputs and Outputs

74ALVC16601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs

General Description

The ALVC16601 is an 18-bit universal bus transceiver which combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.

Data flow in each dir ection is controlled by output-enable (OEAB

and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH-toLOW logic level. If LEA B is LOW, the A bus data is s tored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. When OEAB OEAB

is HIGH, the outputs are in the high-impedance

state. Data flow for B to A is similar to tha t of A to B but uses

OEBA

, LEBA, CLKBA and CLKENBA.

The ALVC16601 is designed for low voltage (1.65V to

3.6V) V The ALVC16601 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintaining low CMOS power dissipation.

applications with I/O capability up to 3.6V.

is LOW, the outputs are active. When

and CLKENBA)

Features

■ 1.65V–3.6V VCC supply operation

■ 3.6V tolerant inputs and outputs

(A to B, B to A)

■ t

3.4 ns max for 3.0V to 3.6V V

4.0 ns max for 2.3V to 2.7V V

7.0 ns max for 1.65V 1.95V V

■ Power-down high impedance inputs and outputs

■ Supports live insertion/withdrawal (Note 1)

■ Uses patented noise/EMI reductio n circuitr y

■ Latchup conforms to JEDEC JED78

■ ESD performance:

Human body model Machine model

■ Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary)

Note 1: To ensure the high-impedance state d uring power up or power down, OE

should be tied to VCC through a pull-up r esistor; the min imum

value of the res istor is d eter mine d by the cu rre nt-sou rcin g ca pa bility of t he driver.

>200V

Ordering Code:

Order Number Package Number Package Description

74ALVC16601GX (Note 2)

74ALVC16601MTD (Note 3)

Note 2: BGA package available in Tape and Reel only. Note 3: Devices also available in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

BGA54A

(Preliminary)

MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL]

CC CC CC

> 2000V

Connection Diagrams

Pin Descriptions

74ALVC16601

Pin Assignment for TSSOP

Pin Assignment for FBGA

(Top Thru View)

Pin Names Descriptio n

OEAB

, OEBA Output Enable Inputs (Active LOW) LEAB, LEBA Latch Enable Inputs CLKAB, CLKBA Clock Inputs CLKENAB A B

, CLKENBA Clock Enable Inputs

1–A18 1–B18

Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs

FBGA Pin Assignments

123 4 56

A A B A C A D A E A F A G A

H A J A

A1OEAB CLKENAB B

A3LEAB CLKAB B

A5V

A7GND GND B

A9GND GND B9B

10 12A11 14A13VCC

16A15 17A18

GND GND B

OEBA CLKBA B

LEBA CLKENBA B

1 3

5 7

11B12

13B14 15B16 18B17

B B B B

Truth Table

(Note 4)

Inputs Outputs

CLKENAB

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance

Note 4: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA LEBA, CLKBA, and C LKENBA

Note 5: Output level be fore the indicated steady-s tate input conditions were established.

Note 6: Output level be fore the indicated steady-s tate input conditions were established, prov ided that CLK AB was HIGH before LEAB went LOW.

OEAB LEAB CLKAB A

XHXXXZ XLHXLL XLHXHH HLLXXB HLLXXB LLL LLL

↑ LL ↑ HH

LLLLXB LLLHXB

(Note 5)

(Note 6)

2 4 6 8

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Logic Diagram

74ALVC16601

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