Fairchild Semiconductor 74ACQ373PC, 74ACQ373CW, 74ACQ373SJX, 74ACQ373SJ, 74ACQ373SCX Datasheet
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© 1999 Fairchild Semiconductor Corporation DS010237 www.fairchildsemi.com
July 1989
Revised November 1999
74ACQ373 • 74ACTQ373 Quiet Series Octal Transparent Latch with 3-STATE Outputs
74ACQ373 • 74ACTQ373
Quiet Series Octal Transparent Latch
with 3-STATE Outputs
General Description
The ACQ/ACTQ373 consists of eight latches with 3-STATE
outputs for bus organized system applications. The latches
appear transparent to the data w hen Latch En able (LE) i s
HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on the bus when
the Output Enable (OE) is LOW. When OE is HIGH, the
bus output is in the HIGH impedance state.
The ACQ/ACTQ373 utilizes Fairchild Quiet Series technology to guarantee quiet output switching and improve
dynamic threshold performance. features GTO output
control and undershoot corrector in addition to a split
ground bus for superior performance.
Features
■ ICC and IOZ reduced by 5 0%
■ Guaranteed simultaneous switching noise level and
dynamic threshold performan ce
■ Guarante ed pin-to-pin s kew AC performance
■ Improved latch up immunity
■ Eight latches in a single package
■ 3-STATE outputs drive bus lines or buffer memory
address registers
■ Outputs source/sink 24 mA
■ Faster prop delays than the standard AC/ACT373
Ordering Code:
Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code.
Connection Diagram Pin Descriptions
FACT, Qui et Series , FACT Quiet Series, an d GTO are trademarks of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74ACQ373SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACQ373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACQ373PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001m 0.300” Wide
74ACTQ373SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACTQ373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACQT373QSC MQA20 20-Lead Quarter Size Outline Packag e (QS OP ), JED EC MO -13 7, 0.15 0” Wide
74ACTQ373PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001m 0.300” Wide
Pin Names Description
D
0–D7
Data Inputs
LE Latch Enable Input
OE
Output Enable Input
O
0–O7
3-STATE Latch Outputs
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74ACQ373 • 74ACTQ373
Logic Symbols
IEEE/IEC
Functional Description
The ACQ/ACTQ373 conta ins eight D-type latches with 3STATE standard outputs. When the Latch Enable (LE)
input is HIGH, data on the D
n
inputs enters the lat ches. In
this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When
LE is LOW, the latches store the information that was
present on the D inputs at setup tim e preced ing th e HIGHto-LOW transition of LE. The 3-STATE standard outputs
are controlled by the Output Enabl e (OE
) input. When OE
is LOW, the standard outputs are in the 2-state mode.
When OE
is HIGH, the standard outpu ts are in the high
impedance mode b ut this does not i nterfere with enter ing
new data into the latches.
Tr uth Table
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O
0
= Previous O0 before HIGH-to-LOW transition of Latch Enable
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs Outputs
LE OE
D
n
O
n
X H X Z
H L L L
H L H H
L L X O
0
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74ACQ373 • 74ACTQ373
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute max imum ratings are those values beyond which damage
to the device may occu r. The databook spe cificatio ns shou ld be met, wit hout exception, to ensure that the system de sign is relia ble over its p ower
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside datab ook s pecifications.
DC Electrical Characteristics for ACQ
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= −0.5V −20 mA
V
I
= VCC + 0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to VCC + 0.5V
DC Output Diode Current (I
OK
)
V
O
= −0.5V −20 mA
V
O
= VCC + 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to VCC + 0.5V
DC Output S ource
or Sink Current (I
O
) ±50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
) ±50 mA
Storage Temperature (T
STG
) −65°C to +150°C
DC Latchup Source
or Sink Current ±300 mA
Junction Temperature (T
J
)
PDIP 140°C
Supply Voltage (V
CC
)
ACQ 2.0V to 6.0V
ACTQ 4.5V to 5.5V
Input Voltage (V
I
) 0V to V
CC
Output Voltage (VO) 0V to V
CC
Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate ∆V/∆t
ACQ Devices
V
IN
from 30% to 70% of V
CC
VCC @ 3.0V, 4.5V, 5.5V 125 mV/ns
Minimum Input Edge Rate ∆V/∆t
ACTQ Devices
V
CC
@ 4.5V, 5.5V 125 mV/ns
Symbol Parameter
V
CC
TA = +25°C TA = −40°C to +85°C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum HIGH Level 3.0 1.5 2.1 2.1 V
OUT
= 0.1V
Input Voltage 4.5 2.25 3.15 3.15 V or VCC − 0.1V
5.5 2.75 3.85 3.85
V
IL
Maximum LOW Level 3.0 1.5 0.9 0.9 V
OUT
= 0.1V
Input Voltage 4.5 2.25 1.35 1.35 V or VCC − 0.1V
5.5 2.75 1.65 1.65
V
OH
Minimum HIGH Level 3.0 2.99 2.9 2.9
Output Voltage 4.5 4.49 4.4 4.4 V I
OUT
= −50 µA
5.5 5.49 5.4 5.4
V
IN
= VIL or V
IH
3.0 2.56 2.46 IOH = −12 mA
4.5 3.86 3.76 V IOH = −24 mA
5.5 4.86 4.76 I
OH
= −24 mA (Note 2)
V
OL
Maximum LOW Level 3.0 0.002 0.1 0.1
Output Voltage 4.5 0.001 0.1 0.1 V I
OUT
= 50 µA
5.5 0.001 0.1 0.1
VIN = VIL or V
IH
3.0 0.36 0.44 IOL = 12 mA
4.5 0.36 0.44 V IOL = 24 mA
5.5 0.36 0.44 IOL = 24 mA (Note 2)
IIN (Note 4) Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 µAVI = VCC, GND
I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
= 1.65V Max
I
OHD
Output Current (Note 3) 5.5 −75 mA V
OHD
= 3.85V Min
I
CC
(Note 4) Maximum Quiescent Supply Current 5.5 4.0 40.0 µAVIN = VCC or GND
I
OZ
Maximum 3-STATE VI (OE) = VIL, V
IH
Leakage Current 5.5 ±0.25 ±2.5 µAVI = VCC, GND
VO = VCC, GND
V
OLP
Quiet Output
5.0 1.1 1.5 V
Figure 1, Figure 2
Maximum Dynamic V
OL
(Note 5)(Note 6)
V
OLV
Quiet Output
5.0 −0.6 −1.2 V
Figure 2, Figure 2
Maximum Dynamic V
OL
(Note 5)(Note 6)
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